JPH11191670A - Printed wiring board and manufacture thereof - Google Patents
Printed wiring board and manufacture thereofInfo
- Publication number
- JPH11191670A JPH11191670A JP36721897A JP36721897A JPH11191670A JP H11191670 A JPH11191670 A JP H11191670A JP 36721897 A JP36721897 A JP 36721897A JP 36721897 A JP36721897 A JP 36721897A JP H11191670 A JPH11191670 A JP H11191670A
- Authority
- JP
- Japan
- Prior art keywords
- protective layer
- opening
- core material
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Wire Bonding (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ベアチップのよう
な電子部品を実装するいわゆるビルトアップ基板のよう
なプリント配線基板及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board such as a so-called built-up board on which electronic components such as bare chips are mounted, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】一般に、電子機器にあっては、各種の電
子部品等の回路素子を実装するためのプリント配線基板
が使用されているが、近年の小型化及び高集積化の要請
により、プリント配線基板自体の小型化及び省スペース
化が求められている。このような状況下において、従
来、一般的なＩＣチップなどの電子部品には接続用の多
数の足の長いリードが設けられ、このリードを屈曲させ
た状態でプリント配線基板にハンダ付けして実装されて
いるが、この時の占有スペースをより小さくするため
に、ＩＣチップに足の長いリードを設けないで代わりに
バンプ部を設け、このバンプ部をプリント配線基板のラ
ンド部にハンダにより直接接合することにより、省スペ
ース化を図ることが行なわれている。このようなバンプ
部を設けたＩＣチップをここではベアチップと称す。2. Description of the Related Art In general, in electronic equipment, printed wiring boards for mounting various electronic components and other circuit elements are used, but due to recent demands for miniaturization and high integration, printed wiring boards have been used. There is a demand for miniaturization and space saving of the wiring board itself. Under such circumstances, conventionally, a general electronic component such as an IC chip is provided with a large number of long legs for connection, and soldered to a printed wiring board in a state where the leads are bent and mounted. However, in order to reduce the occupied space at this time, a long bump is provided instead of a long lead on the IC chip, and this bump is directly joined to the land of the printed wiring board by soldering. By doing so, space saving can be achieved. The IC chip provided with such a bump portion is referred to as a bare chip here.
【０００３】このベアチップを従来のプリント配線基板
に接続する時の状況を説明する。図４はプリント配線基
板とベアチップの実装直前の状態を示す図、図５はプリ
ント配線基板の拡大平面図である。ベアチップ１はその
下面に突起状の多数のバンプ部２を有している。図示例
ではこのバンプ部２は５個しか記載していないが、実際
には、数１０個から数１００個程度設けられ、また、各
バンプ部２のピッチＬ１は２００μｍ程度に設定されて
いる。The situation when connecting the bare chip to a conventional printed wiring board will be described. FIG. 4 is a diagram showing a state immediately before mounting the printed wiring board and the bare chip, and FIG. 5 is an enlarged plan view of the printed wiring board. The bare chip 1 has a large number of projecting bumps 2 on its lower surface. Although only five bumps 2 are shown in the illustrated example, in practice, several tens to several hundreds are provided, and the pitch L1 of each bump 2 is set to about 200 μm.
【０００４】一方、このベアチップ１を実装するプリン
ト配線基板３は、板状の例えばエポキシ樹脂よりなる絶
縁性のコア材４の表面に例えば銅よりなる導体パターン
５を積層して、この上に例えばフォトソルダーレジスト
よりなる絶縁性の保護層６を所定の厚さで形成してい
る。そして、ベアチップ１のバンプ部２を接続する部分
に対応させて、保護層６は局部的に微細な円形状に或い
は楕円形状に取り除かれて内部の導体パターン４の一部
を形成するランド部７が露出されている。ベアチップ１
の各バンプ部２は、各対応するランド部７にリフロー等
を用いたハンダにより接続されることになる。図６は１
つのランド部の拡大図を示しており、実際には銅よりな
るランド部７の表面には酸化防止用の金属膜、例えば金
メッキ膜８が施され、この上にハンダ９が盛られてい
る。On the other hand, a printed wiring board 3 on which the bare chip 1 is mounted is formed by laminating a conductor pattern 5 made of, for example, copper on a surface of a plate-shaped insulating core material 4 made of, for example, an epoxy resin. An insulating protective layer 6 made of a photo solder resist is formed with a predetermined thickness. The protection layer 6 is locally removed into a fine circular or elliptical shape corresponding to the portion of the bare chip 1 to which the bump portion 2 is connected, and the land 7 forms a part of the internal conductor pattern 4. Is exposed. Bare chip 1
The bump portions 2 are connected to the corresponding land portions 7 by soldering using reflow or the like. FIG.
An enlarged view of one land portion is shown. In practice, a metal film for preventing oxidation, for example, a gold plating film 8 is applied to the surface of the land portion 7 made of copper, and solder 9 is piled on this.
【０００５】[0005]
【発明が解決しようとする課題】ところで、ランド部７
の近傍の開口部の形状は好ましくは図７に示すような形
状が望ましい。すなわち、図７は図５中のプリント配線
基板の拡大断面図を示し、図７（Ａ）は図５中のＡ−Ａ
線矢視断面図、図７（Ｂ）は図５中のＢ−Ｂ線矢視断面
図である。ここで、ランド部７を露出させるための保護
層６の開口部１０の開口端１１はコア材４の平面に対し
て略垂直であるのが望ましいが、実際には図８或いは図
９に示すようにこの開口端１１は垂直にはならずテーパ
面となってしまう。すなわち、光硬化性のフォトソルダ
ーレジストよりなる保護層６に開口部１０を形成するに
は、図示しないマスクを用いてこの開口部を１０以外の
部分に光を照射して露光することにより開口部１０以外
の部分を硬化し、その後、開口部１０の部分の保護層を
現像により除去している。The land 7
Is preferably a shape as shown in FIG. That is, FIG. 7 is an enlarged sectional view of the printed wiring board in FIG. 5, and FIG.
FIG. 7B is a sectional view taken along line BB in FIG. 5. Here, it is desirable that the opening end 11 of the opening 10 of the protective layer 6 for exposing the land portion 7 is substantially perpendicular to the plane of the core material 4, but in practice it is shown in FIG. 8 or FIG. Thus, the opening end 11 does not become vertical but becomes a tapered surface. That is, in order to form the opening 10 in the protective layer 6 made of a photocurable photo-solder resist, the opening is exposed by irradiating light to portions other than 10 using a mask (not shown). Portions other than 10 are cured, and then the protective layer in the portion of the opening 10 is removed by development.
【０００６】この場合、保護層６自体の厚さは、例えば
３０μｍ程度とかなり厚いことから露光条件や用いたフ
ォトソルダーレジストの種類等に起因して、図８に示す
ように開口端１１がランド部７に向けて傾斜してにじみ
でたり、逆に図９に示すように開口端１１が下に行く程
内側へ傾斜して食い込んで来たりする場合があった。こ
のような保護層６のにじみだしや食い込みは、デザイン
ルールがそれ程小さくない場合には、問題とはならなか
ったが、基板の小型化及びチップサイズの小型化によっ
て高密度化が行なわれると、次のような問題が発生し
た。すなわち、微細化がより推進された状況下において
は、図８に示すようににじみだし（かぶり）が生ずる
と、これが障害となってランド部７の表面に腐食防止用
の金メッキ膜８が十分に形成できずにこれが剥がれ易く
なる。In this case, the thickness of the protective layer 6 itself is considerably large, for example, about 30 μm, so that the opening end 11 has a land as shown in FIG. 8 due to the exposure conditions and the type of the photo solder resist used. In some cases, the ink may incline toward the part 7 and bleed, or conversely, as shown in FIG. Such bleeding or penetration of the protective layer 6 did not cause a problem if the design rule was not so small. However, when the density was increased by downsizing the substrate and the chip size, The following problems occurred. That is, in a situation where the miniaturization is further promoted, if bleeding (fogging) occurs as shown in FIG. 8, this becomes an obstacle, and the gold plating film 8 for corrosion prevention is sufficiently formed on the surface of the land portion 7. This tends to peel off without being formed.
【０００７】また、図９に示すように開口端１１が内部
に食い込んでくると、金属コーティング液がしみ込み易
くなって、この保護膜６が非常に剥がれ易くなってしま
うばかりか、ハンダ付け時におけるフラックスの濡れ性
も劣化してしまうという問題があった。本発明は、以上
のような問題点に着目し、これを有効に解決すべく創案
されたものであり、その目的はランド部を露出させる保
護層の開口部の開口端の形状を工夫することにより、保
護層の剥がれを防止すると共に例えば金メッキ膜などの
金属膜の付着形成やフラックスの浸透も容易に行なうこ
とができるプリント配線基板とその製造方法を提供する
ことにある。When the opening end 11 bites into the inside as shown in FIG. 9, the metal coating liquid easily penetrates, and not only does this protective film 6 become very easy to peel off, but also when soldering. However, there is a problem that the wettability of the flux deteriorates. The present invention pays attention to the above problems, and has been made in order to effectively solve the problems. The purpose is to devise the shape of the opening end of the opening of the protective layer that exposes the land. Accordingly, it is an object of the present invention to provide a printed wiring board and a method of manufacturing the same, which can prevent peeling of a protective layer and can easily form and adhere a metal film such as a gold plating film and permeate flux.
【０００８】[0008]
【課題を解決するための手段】本発明は、上記問題点を
解決するために、板状のコア材の表面に、電子部品をハ
ンダ付けするためのランド部を含む導体パターンを形成
し、このコア材の表面に前記ランド部を露出させるよう
に開口した状態で前記導体パターンを覆うように所定の
厚さの保護層を形成してなるプリント配線基板におい
て、前記保護層は、前記ランド部の開口部において前記
コア材の表面に対して略垂直になされた開口端を有する
第１の保護層と、この第１の保護層の上に形成されて外
側に対して拡開するように上向き傾斜された開口端を有
する第２の保護層とよりなるようにしたものである。According to the present invention, in order to solve the above problems, a conductor pattern including a land portion for soldering an electronic component is formed on a surface of a plate-like core material. In a printed wiring board formed with a protective layer having a predetermined thickness so as to cover the conductor pattern in a state where the land is opened so as to expose the land on the surface of a core material, the protective layer is formed of the land. A first protective layer having an opening end substantially perpendicular to the surface of the core material at the opening; and an upper slope formed on the first protective layer and expanding upward to expand outward. And a second protective layer having a defined opening end.
【０００９】これにより、ランド部を露出させる保護層
の開口部において、第１の保護層の開口端は厚さ方向へ
略垂直に形成され、第２の保護層の開口端は上方へ行く
程、拡開しているので、保護層自体の剥がれが抑制さ
れ、しかもランド部表面における金メッキ膜などの金属
膜のコーティングも阻害することがない。また、フラッ
クスに対する濡れ性も改善できるので、この開口部内へ
フラックスを浸透させる際にも、これを容易に浸透させ
ることが可能となる。ここで、保護層としては、光照射
により感光されるフォトソルダーレジストを用いること
ができる。Thus, in the opening of the protective layer that exposes the land, the opening end of the first protective layer is formed substantially perpendicularly to the thickness direction, and the opening end of the second protective layer goes upward. Because of the expansion, the peeling of the protective layer itself is suppressed, and the coating of a metal film such as a gold plating film on the surface of the land is not hindered. In addition, since the wettability with respect to the flux can be improved, the flux can easily penetrate into the opening. Here, as the protective layer, a photo solder resist that is exposed by light irradiation can be used.
【００１０】また、本発明方法は、板状のコア材の表面
に、電子部品をハンダ付けするためのランド部を含む導
体パターンを形成し、このコア材の表面に前記ランド部
を露出させるように開口した状態で前記導体パターンを
覆うように所定の厚さの保護層を形成してなるプリント
配線基板の製造方法において、前記コア材の表面に、前
記ランド部を含む導体パターンを形成する工程と、前記
コア材の表面に前記導体パターンを覆って第１の保護層
を形成する工程と、この第１の保護層に、前記ランド部
を露出させるために前記コア材の表面に対して略垂直と
なるような開口端を有するような開口部を形成する第１
の開口工程と、前記ランド部を含んで前記コア材の表面
を覆って第２の保護層を形成する工程と、この第２の保
護層に、前記ランド部を露出させるために外部に対して
拡開するように上向き傾斜された開口端を有するような
開口部を形成する第２の開口工程とを有するようにした
ものである。In the method of the present invention, a conductor pattern including a land portion for soldering an electronic component is formed on a surface of a plate-shaped core material, and the land portion is exposed on the surface of the core material. Forming a conductive pattern including the land on a surface of the core material in a method of manufacturing a printed wiring board comprising forming a protective layer having a predetermined thickness so as to cover the conductive pattern in an opened state. Forming a first protective layer on the surface of the core material so as to cover the conductor pattern; and forming the first protective layer on the surface of the core material to expose the lands. First forming an opening having an opening end that is vertical
An opening step, a step of forming a second protective layer covering the surface of the core material including the land portion, and a step of exposing the land portion to the outside to expose the land portion to the second protective layer. And a second opening step of forming an opening having an opening end inclined upward so as to expand.
【００１１】この場合、前記第１及び第２の開口工程の
後に、前記保護層を硬化させる硬化工程を加えるように
するのがよい。In this case, it is preferable to add a curing step of curing the protective layer after the first and second opening steps.
【００１２】また、前記開口端の角度調整は、前記フォ
トソルダーレジストに照射される光の積算光量を調整す
ることにより行なうことができる。Further, the angle adjustment of the opening end can be performed by adjusting the integrated light amount of light applied to the photo solder resist.
【００１３】[0013]
【発明の実施の形態】以下に、本発明に係るプリント配
線基板及びその製造方法の一実施例を添付図面に基づい
て詳述する。図１は本発明のプリント配線基板を示す部
分拡大断面図である。尚、先に説明した従来のプリント
配線基板と同一部分については同一符号を付して説明す
る。図１において、プリント配線基板１５は、例えばエ
ポキシ樹脂よりなる板状の絶縁性材料よりなるコア材４
を有しており、電子部品が実装される側の表面には例え
ば銅よりなる導体パターン５（図５参照）が形成され、
更に、この導体パターン５を含むコア材４の表面を覆う
ようにして保護層６が形成される。また、導体パターン
５のランド部７に対応する保護層６には、例えば所定の
直径の円形の開口部１０が形成されており、内部のラン
ド部７を露出させている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a printed wiring board according to the present invention and a method for manufacturing the same will be described below in detail with reference to the accompanying drawings. FIG. 1 is a partially enlarged sectional view showing a printed wiring board of the present invention. The same parts as those of the above-described conventional printed wiring board are denoted by the same reference numerals and described. In FIG. 1, a printed wiring board 15 is made of a core material 4 made of a plate-shaped insulating material made of, for example, epoxy resin.
And a conductor pattern 5 (see FIG. 5) made of, for example, copper is formed on the surface on the side on which the electronic component is mounted,
Further, a protective layer 6 is formed so as to cover the surface of the core material 4 including the conductor pattern 5. The protective layer 6 corresponding to the land 7 of the conductor pattern 5 has a circular opening 10 having a predetermined diameter, for example, to expose the internal land 7.
【００１４】本実施例では、上記保護層６は、コア材表
面と直接接触する第１の保護層６Ａとこの上に積層され
る第２の保護層６Ｂとよりなり、これらの両保護層６
Ａ、６Ｂは例えば光照射によって硬化されるフォトソル
ダーレジストにより構成される。特に、第１の保護層６
Ａの開口部１０の開口端１６は下層のコア材４の表面に
対して略垂直の角度となるように設定され、これに続く
第２の保護層６Ａの開口部１０の開口端１７は、外側
（図１中では上側）に対して拡開するように上向き傾斜
されている。この開口端１７の傾斜角θは、後述するよ
うにフラックスの浸透を容易にするため４５度程度が望
ましい。In the present embodiment, the protective layer 6 comprises a first protective layer 6A which is in direct contact with the surface of the core material and a second protective layer 6B laminated thereon.
A and 6B are made of, for example, a photo solder resist cured by light irradiation. In particular, the first protective layer 6
The opening end 16 of the opening 10 of A is set so as to be substantially perpendicular to the surface of the core material 4 in the lower layer, and the opening end 17 of the opening 10 of the second protective layer 6A following this is It is inclined upward so as to expand toward the outside (the upper side in FIG. 1). The inclination angle θ of the opening end 17 is desirably about 45 degrees in order to facilitate flux penetration as described later.
【００１５】図示例では、１つしかランド部７を記載し
ていないが、先に図４及び図５を参照して説明したよう
にこのランド部は電子部品である例えばベアチップ１の
バンプ部２の数量に対応させて多数個設けられ、また、
ランド部７のピッチ（図示せず）もバンプ部２のピッチ
Ｌ１に対応しているのは勿論である。ここで、バンプ部
２のピッチＬ１はランド部７のピッチと同じで例えば、
従来は２００μｍ程度であったが、最近は１５０μｍ程
度になって微細化が進んでいる。そして、開口部１０の
底部の直径Ｌ２は２００μｍ程度、ランド部７の幅Ｗ１
は９０μｍ程度、第１の保護層６Ａの厚さＴ１及び第２
の保護層６Ｂの厚さＴ２はそれぞれ共に１５μｍ程度で
ある。In the illustrated example, only one land portion 7 is described. However, as described above with reference to FIGS. 4 and 5, this land portion is an electronic component such as a bump portion 2 of a bare chip 1. A large number is provided corresponding to the quantity of
Needless to say, the pitch (not shown) of the land portions 7 also corresponds to the pitch L1 of the bump portions 2. Here, the pitch L1 of the bumps 2 is the same as the pitch of the lands 7, for example,
Conventionally, it was about 200 μm, but recently, it has been reduced to about 150 μm and miniaturization has been advanced. The diameter L2 of the bottom of the opening 10 is about 200 μm, and the width W1 of the land 7 is
Is about 90 μm, the thickness T1 of the first protective layer 6A and the second
Each of the protective layers 6B has a thickness T2 of about 15 μm.
【００１６】このように、ランド部７を露出させる開口
部１０の上層の第２の保護層６Ｂの開口端１７を上向き
に拡開するように形成したので、開口部１０の間口が広
くなってハンダ接続時にこの内部にフラックスを浸透さ
せる際にも、このフラックスに対する濡れ性が向上し、
容易に浸透させることが可能となる。更に、下層の第１
の保護層６Ａの開口端１６は、コア材４の厚さ方向へ沿
うように略垂直になされているので、この保護層６全体
が剥がれることを防止できるのみならず、ランド部７の
表面へのかぶりもなくなるので、ランド部表面への金メ
ッキ膜の形成も容易に行なうことが可能となり、金メッ
キ膜をランド部表面に強固に付着させることができる。As described above, since the opening end 17 of the second protective layer 6B, which is the upper layer of the opening 10 exposing the land portion 7, is formed to expand upward, the frontage of the opening 10 becomes wider. Even when the flux penetrates into this inside at the time of solder connection, the wettability to this flux is improved,
It can be easily penetrated. Furthermore, the lower first layer
Since the opening end 16 of the protective layer 6A is formed substantially perpendicularly along the thickness direction of the core material 4, not only the entire protective layer 6 can be prevented from peeling off, but also Since the fogging is also eliminated, it is possible to easily form a gold plating film on the surface of the land portion, and it is possible to firmly attach the gold plating film to the surface of the land portion.
【００１７】次に、このプリント配線基板の製造方法に
ついて図２及び図３を参照して具体的に説明する。ま
ず、図２（Ａ）に示すように、板状の絶縁性のコア材４
の表面全体に例えば銅箔２０を所定の厚さでメッキし、
これをパターンエッチング形成することにより、ランド
部７を含む導体パターン５を形成する（図２（Ｂ）参
照）。Next, a method of manufacturing the printed wiring board will be specifically described with reference to FIGS. First, as shown in FIG. 2A, a plate-shaped insulating core material 4 is formed.
For example, copper foil 20 is plated on the entire surface with a predetermined thickness,
This is subjected to pattern etching to form the conductor pattern 5 including the land portion 7 (see FIG. 2B).
【００１８】次に、図２（Ｃ）に示すように、この導体
パターン５を含むコア材１の表面全体に例えばフォトソ
ルダーレジスト２１を乾燥後の厚さが所定の厚さ、例え
ば１５μｍ程度となるように塗布して熱により乾燥硬化
する。そして、次に図２（Ｄ）に示すように開口部１０
に対応する部分に直径α（＝Ｌ２）の第１マスク２２を
設置して所定の時間だけ露光する。この時の露光時間
は、厚さ１５μｍ程度のフォトソルダーレジスト２１の
露光境界面が略垂直となるような露光積算量となるよう
に設定する。フォトソルダーレジスト２１として、例え
ばＰＳＲ−２２００（商品名）を用いた場合には、積算
光量は略１５０ｍＪ（ジュール）／ｃｍ2程度である。Next, as shown in FIG. 2C, the thickness of the photo solder resist 21 after drying, for example, over the entire surface of the core material 1 including the conductor pattern 5 is set to a predetermined thickness, for example, about 15 μm. And then dried and cured by heat. Then, as shown in FIG.
The first mask 22 having a diameter α (= L2) is set in a portion corresponding to the above, and is exposed for a predetermined time. The exposure time at this time is set such that the exposure integration amount is such that the exposure boundary surface of the photo solder resist 21 having a thickness of about 15 μm is substantially vertical. When, for example, PSR-2200 (trade name) is used as the photo solder resist 21, the integrated light amount is approximately 150 mJ (joule) / cm 2 .
【００１９】このように、露光して次に現像を行なうこ
とにより、図２（Ｅ）に示すように露光されなかったフ
ォトソルダーレジストを除去して開口部１０の下段を形
成すると同時にフォトソルダーレジスト２１を硬化させ
ることによって、第１の保護層６Ａを形成する。ここ
で、必要ならば、図２（Ｆ）に示すように全体に熱を加
えて第１の保護層６Ａをより確実に硬化させるようにし
てもよい。In this manner, by performing exposure and subsequent development, the unexposed photo solder resist is removed as shown in FIG. By curing 21, the first protective layer 6A is formed. Here, if necessary, as shown in FIG. 2 (F), heat may be applied to the entirety to cure the first protective layer 6A more reliably.
【００２０】次に、図３（Ａ）に示すように開口部１０
及び第１の保護層６Ａを含むコア材４の表面全体に、前
述したと同じ特性のフォトソルダーレジスト２３を乾燥
後の厚さが所定の厚さ、例えば１５μｍ程度となるよう
に塗布して熱により硬化する。そして、図３（Ｂ）に示
すように開口部１０に対応する部分に、先の第１マスク
２２の直径αよりも僅かに大きな直径βの第２マスク２
４を設置して所定の時間だけ露光する。この時の露光時
間は、第１マスク２２の時とは異なり、厚さ１５μｍ程
度のフォトソルダーレジスト２３の露光境界面が図中上
方に向けて拡開された傾斜面となるような露光積算量と
なるように設定する。この場合には、積算光量は、第１
の保護層６Ａの場合よりも僅かに多く、例えば２５０ｍ
Ｊ（ジュール）／ｃｍ2 程度である。Next, as shown in FIG.
A photo solder resist 23 having the same characteristics as described above is applied to the entire surface of the core material 4 including the first protective layer 6A so that the thickness after drying becomes a predetermined thickness, for example, about 15 μm. To cure. Then, as shown in FIG. 3B, a second mask 2 having a diameter β slightly larger than the diameter α of the first mask 22 is provided in a portion corresponding to the opening 10.
4 is set and exposed for a predetermined time. The exposure time at this time is different from that of the first mask 22 in that the exposure integration amount is such that the exposure boundary surface of the photo solder resist 23 having a thickness of about 15 μm becomes an inclined surface that is expanded upward in the drawing. Set so that In this case, the integrated light amount is the first
Slightly more than the case of the protective layer 6A, for example, 250 m
It is about J (joule) / cm 2 .
【００２１】このように露光積算量を多くする程、露光
境界面における熱が第２マスク２４の下方側に位置する
フォトソルダーレジスト２３にも侵入する傾向となり、
結果的に、図３（Ｂ）に示すように露光部分が厚み方向
に深くなるに従って、内側へ、すなわち第２マスク２４
の下方側へ侵入してくることになる。このように、露光
して次に現像を行なうことにより、図３（Ｃ）に示すよ
うに露光されなかったフォトソルダーレジストを除去し
て開口部１０の上段を形成すると同時にフォトソルダー
レジストを硬化させることによって第２の保護層６Ｂを
形成する。ここで必要ならば図３（Ｄ）に示すように全
体に熱を加えて第２の保護層６Ｂをより確実に硬化させ
るようにしてもよい。以上の操作により、図１に示すよ
うなプリント配線基板１５を完成することができる。そ
の後、必要ならば、先に説明したように露出している銅
製のランド部７の表面の酸化を防止するためにこのラン
ド部７の表面に金メッキ膜等の金属膜を形成するのは勿
論である。As the exposure integration amount increases, heat at the exposure boundary surface also tends to penetrate into the photo solder resist 23 located below the second mask 24,
As a result, as shown in FIG. 3B, as the exposed portion becomes deeper in the thickness direction, the second mask 24
Will invade the lower side of. In this manner, by performing exposure and subsequent development, as shown in FIG. 3C, the unexposed photo solder resist is removed to form the upper stage of the opening 10 and at the same time, the photo solder resist is cured. Thereby, the second protective layer 6B is formed. Here, if necessary, as shown in FIG. 3 (D), heat may be applied to the whole to more reliably cure the second protective layer 6B. By the above operation, the printed wiring board 15 as shown in FIG. 1 can be completed. Thereafter, if necessary, a metal film such as a gold plating film is formed on the surface of the land portion 7 to prevent oxidation of the exposed surface of the copper land portion 7 as described above. is there.
【００２２】ここで、第１及び第２の保護層６Ａ、６Ｂ
を形成する時に用いるフォトソルダーレジストはそれぞ
れ厚さが１５μｍ程度であって非常に薄いので、露光時
において露光される部分とマスクにより露光されない部
分との境界面の形状を、積算光量をコントロールするこ
とにより容易に調整することがでる。例えば積算光量の
コントロールにより第１の保護層６Ａの場合には、開口
端１６をコア材表面に対して略垂直に形成することがで
き、また、第２の保護層６Ｂの場合には開口端１７を上
方へ拡開するように上向き傾斜させて形成することがで
きる。Here, the first and second protective layers 6A and 6B
Since the thickness of the photo solder resist used when forming the mask is about 15 μm and is very thin, the shape of the boundary surface between the part exposed at the time of exposure and the part not exposed by the mask should be controlled by the integrated light amount. Can be adjusted more easily. For example, in the case of the first protective layer 6A, the opening end 16 can be formed substantially perpendicular to the core material surface by controlling the integrated light amount, and in the case of the second protective layer 6B, the opening end 16 can be formed. 17 can be formed to be inclined upward so as to expand upward.
【００２３】また、ここでは第１及び第２の保護層６
Ａ、６Ｂを形成するフォトソルダーレジストは同じ組成
のものを用いたが、両保護層６Ａ、６Ｂ間で、フォトソ
ルダーレジストに含まれる光硬化剤等の含有量を異なら
せるなど、異なった組成のレジストを用いてもよい。例
えば、光硬化剤等の含有量を多くすれば、短時間の露光
で所望の形状の開口部１０を形成することができる。
尚、ここで説明した数値例は単に一例を示したに過ぎ
ず、これらに限定されないのは勿論である。Here, the first and second protective layers 6
The photo solder resist for forming A and 6B had the same composition, but had a different composition between the two protective layers 6A and 6B, for example, by changing the content of the photo-curing agent contained in the photo solder resist. A resist may be used. For example, if the content of the photocuring agent or the like is increased, the opening 10 having a desired shape can be formed by short-time exposure.
It should be noted that the numerical examples described here are merely examples, and the present invention is not limited to them.
【００２４】[0024]
【発明の効果】以上説明したように、本発明のプリント
配線基板及びその製造方法によれば、次のように優れた
作用効果を発揮することができる。導体パターンを保護
する保護層を第１と第２の保護層で形成して、ランド部
を露光させる開口部の開口端に関して、下層の開口端を
コア材表面に対して略垂直とし、上層の開口端を外側に
向けて拡開するように傾斜させるようにしたので、従来
のプリント配線基板で発生していた保護層のにじみだし
（かぶり）や金属コーティング液のしみ込みを防止する
ことができる。従って、保護層のにじみだしが抑制でき
ることから、後工程で行なわれるランド部表面への金メ
ッキ膜等の金属膜の付着を容易に且つ強固に行なうこと
ができる。また、金属コーティング液のしみ込みを防止
できることから保護膜自体の剥がれも防止することがで
きる。更には、開口部の間口が広くなることから、開口
部内にフラックスも入り易くなってその濡れ性も改善す
ることができる。As described above, according to the printed wiring board and the method of manufacturing the same of the present invention, the following excellent operational effects can be exhibited. A protective layer for protecting the conductor pattern is formed of the first and second protective layers, and with respect to the opening end of the opening for exposing the land, the opening end of the lower layer is made substantially perpendicular to the surface of the core material. Since the opening end is inclined so as to expand outward, the bleeding (fogging) of the protective layer and seepage of the metal coating liquid which occur in the conventional printed wiring board can be prevented. . Therefore, since the oozing of the protective layer can be suppressed, it is possible to easily and firmly attach a metal film such as a gold plating film to the surface of the land in a later step. Further, since the permeation of the metal coating liquid can be prevented, peeling of the protective film itself can also be prevented. Furthermore, since the frontage of the opening is widened, flux easily enters the opening and the wettability can be improved.
【図１】図１は本発明のプリント配線基板を示す部分拡
大断面図である。FIG. 1 is a partially enlarged sectional view showing a printed wiring board of the present invention.
【図２】プリント配線基板の製造方法を説明する図であ
る。FIG. 2 is a diagram illustrating a method for manufacturing a printed wiring board.
【図３】プリント配線基板の製造方法を説明する図であ
る。FIG. 3 is a diagram illustrating a method for manufacturing a printed wiring board.
【図４】プリント配線基板とベアチップの実装直前の状
態を示す図である。FIG. 4 is a diagram showing a state immediately before mounting a printed wiring board and a bare chip.
【図５】プリント配線基板の拡大平面図である。FIG. 5 is an enlarged plan view of a printed wiring board.
【図６】１つのランド部を示す拡大図である。FIG. 6 is an enlarged view showing one land portion.
【図７】ランド部の近傍の開口部の好ましい形状を示す
拡大断面図である。FIG. 7 is an enlarged sectional view showing a preferred shape of an opening near a land.
【図８】ランド部の近傍の開口部の好ましくない形状を
示す拡大断面図である。FIG. 8 is an enlarged sectional view showing an unfavorable shape of an opening near a land.
【図９】ランド部の近傍の開口部の好ましくない形状を
示す拡大断面図である。FIG. 9 is an enlarged sectional view showing an unfavorable shape of an opening near a land.
１…ベアチップ、２…バンプ部、４…コア材、５…導体
パターン、６…保護層、６Ａ…第１の保護層、６Ｂ…第
２の保護層、７…ランド部、８…金メッキ膜、１０…開
口部、１５…プリント配線基板、１６，１７…開口端、
２１，２３…フォトソルダーレジスト、２２…第１マス
ク、２４…第２マスク。DESCRIPTION OF SYMBOLS 1 ... Bear chip, 2 ... Bump part, 4 ... Core material, 5 ... Conductor pattern, 6 ... Protective layer, 6A ... First protective layer, 6B ... Second protective layer, 7 ... Land part, 8 ... Gold plating film, 10 opening, 15 printed wiring board, 16, 17 opening end,
21, 23: photo solder resist, 22: first mask, 24: second mask.
Claims (6)
ダ付けするためのランド部を含む導体パターンを形成
し、このコア材の表面に前記ランド部を露出させるよう
に開口した状態で前記導体パターンを覆うように所定の
厚さの保護層を形成してなるプリント配線基板におい
て、前記保護層は、前記ランド部の開口部において前記
コア材の表面に対して略垂直になされた開口端を有する
第１の保護層と、この第１の保護層の上に形成されて外
側に対して拡開するように上向き傾斜された開口端を有
する第２の保護層とよりなることを特徴とするプリント
配線基板。1. A conductor pattern including a land portion for soldering an electronic component is formed on a surface of a plate-shaped core material, and the conductor pattern is opened on the surface of the core material so as to expose the land portion. In a printed wiring board formed with a protective layer having a predetermined thickness so as to cover the conductor pattern, the protective layer has an opening substantially perpendicular to a surface of the core material at an opening of the land. A first protective layer having an end; and a second protective layer formed on the first protective layer and having an open end inclined upward so as to expand toward the outside. Printed wiring board.
ルダーレジストよりなることを特徴とする請求項１記載
のプリント配線基板。2. The printed wiring board according to claim 1, wherein said first and second protective layers are made of a photo solder resist.
ダ付けするためのランド部を含む導体パターンを形成
し、このコア材の表面に前記ランド部を露出させるよう
に開口した状態で前記導体パターンを覆うように所定の
厚さの保護層を形成してなるプリント配線基板の製造方
法において、前記コア材の表面に、前記ランド部を含む
導体パターンを形成する工程と、前記コア材の表面に前
記導体パターンを覆って第１の保護層を形成する工程
と、この第１の保護層に、前記ランド部を露出させるた
めに前記コア材の表面に対して略垂直となるような開口
端を有するような開口部を形成する第１の開口工程と、
前記ランド部を含んで前記コア材の表面を覆って第２の
保護層を形成する工程と、この第２の保護層に、前記ラ
ンド部を露出させるために外部に対して拡開するように
上向き傾斜された開口端を有するような開口部を形成す
る第２の開口工程とを有することを特徴とするプリント
配線基板の製造方法。3. A conductor pattern including a land portion for soldering an electronic component is formed on the surface of a plate-shaped core material, and the conductor pattern is opened on the surface of the core material so as to expose the land portion. In a method for manufacturing a printed wiring board, comprising forming a protective layer having a predetermined thickness so as to cover the conductor pattern, a step of forming a conductor pattern including the land portion on a surface of the core material; Forming a first protective layer on the surface of the core material so as to cover the conductor pattern, and forming the first protective layer on the first protective layer so as to be substantially perpendicular to the surface of the core material so as to expose the lands. A first opening step of forming an opening having an opening end;
Forming a second protective layer covering the surface of the core material including the land portion, and expanding the second protective layer to the outside in order to expose the land portion to the second protective layer. A second opening step of forming an opening having an opening end inclined upward.
記保護層を硬化させる硬化工程を加えるようにしたこと
を特徴とする請求項３記載のプリント配線基板の製造方
法。4. The method according to claim 3, wherein a curing step of curing the protective layer is added after the first and second opening steps.
ルダーレジストよりなることを特徴とする請求項３また
は４記載のプリント配線基板の製造方法。5. The method according to claim 3, wherein the first and second protective layers are made of a photo solder resist.
ルダーレジストに照射される光の積算光量を調整するこ
とにより行なわれることを特徴とする請求項５記載のプ
リント配線基板の製造方法。6. The method for manufacturing a printed wiring board according to claim 5, wherein the angle adjustment of the opening end is performed by adjusting an integrated light amount of light applied to the photo solder resist.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36721897A JP3856414B2 (en) | 1997-12-25 | 1997-12-25 | Printed wiring board manufacturing method and printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP36721897A JP3856414B2 (en) | 1997-12-25 | 1997-12-25 | Printed wiring board manufacturing method and printed wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11191670A true JPH11191670A (en) | 1999-07-13 |
| JP3856414B2 JP3856414B2 (en) | 2006-12-13 |
Family
ID=18488772
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP36721897A Expired - Lifetime JP3856414B2 (en) | 1997-12-25 | 1997-12-25 | Printed wiring board manufacturing method and printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3856414B2 (en) |
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| CN107969076B (en) * | 2013-05-22 | 2020-04-28 | 三菱制纸株式会社 | Method for manufacturing wiring substrate |
| JP2015216332A (en) * | 2013-05-22 | 2015-12-03 | 三菱製紙株式会社 | Method for manufacturing wiring board |
| TWI700974B (en) * | 2013-06-14 | 2020-08-01 | 日商三菱製紙股份有限公司 | Process for producing wiring substrate |
| CN107846786A (en) * | 2013-06-14 | 2018-03-27 | 三菱制纸株式会社 | The manufacture method of circuit board |
| JP2016006809A (en) * | 2013-06-14 | 2016-01-14 | 三菱製紙株式会社 | Wiring board manufacturing method |
| CN105309053A (en) * | 2013-06-14 | 2016-02-03 | 三菱制纸株式会社 | Method for manufacturing wiring board |
| KR20160020407A (en) * | 2013-06-14 | 2016-02-23 | 미쓰비시 세이시 가부시키가이샤 | Method for manufacturing wiring board |
| CN107846786B (en) * | 2013-06-14 | 2021-03-05 | 三菱制纸株式会社 | Method for manufacturing wiring substrate |
| WO2017170261A1 (en) * | 2016-03-28 | 2017-10-05 | 富士通株式会社 | Wiring board, electronic device, and wiring board manufacturing method |
| JP2017183337A (en) * | 2016-03-28 | 2017-10-05 | 富士通株式会社 | Wiring board, electronic device, and method of manufacturing wiring board |
| CN108781513A (en) * | 2016-03-28 | 2018-11-09 | 富士通株式会社 | The manufacturing method of wiring substrate, electronic device and wiring substrate |
| US10770386B2 (en) | 2016-03-28 | 2020-09-08 | Fujitsu Interconnect Technologies Limited | Wiring board, electronic device, and wiring board manufacturing method |
| JP2020113681A (en) * | 2019-01-15 | 2020-07-27 | 株式会社京写 | Print circuit board |
| WO2023239224A1 (en) * | 2022-06-10 | 2023-12-14 | 엘지이노텍 주식회사 | Circuit board, and semiconductor package comprising same |
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