US20230207444A1 - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- US20230207444A1 US20230207444A1 US18/171,156 US202318171156A US2023207444A1 US 20230207444 A1 US20230207444 A1 US 20230207444A1 US 202318171156 A US202318171156 A US 202318171156A US 2023207444 A1 US2023207444 A1 US 2023207444A1
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- semiconductor device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 259
- 238000000034 method Methods 0.000 title description 61
- 238000004519 manufacturing process Methods 0.000 title description 51
- 239000011347 resin Substances 0.000 claims abstract description 128
- 229920005989 resin Polymers 0.000 claims abstract description 128
- 238000007789 sealing Methods 0.000 claims abstract description 69
- 239000002184 metal Substances 0.000 claims description 22
- 229910052751 metal Inorganic materials 0.000 claims description 22
- 239000010949 copper Substances 0.000 claims description 16
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 7
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 238000007747 plating Methods 0.000 description 57
- 230000015572 biosynthetic process Effects 0.000 description 35
- 239000000758 substrate Substances 0.000 description 35
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 14
- 239000000463 material Substances 0.000 description 11
- 230000008569 process Effects 0.000 description 11
- 239000010936 titanium Substances 0.000 description 10
- 238000009713 electroplating Methods 0.000 description 9
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 8
- 238000005520 cutting process Methods 0.000 description 8
- 238000007772 electroless plating Methods 0.000 description 8
- 239000010931 gold Substances 0.000 description 8
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 7
- 238000007788 roughening Methods 0.000 description 7
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 6
- 229910045601 alloy Inorganic materials 0.000 description 6
- 239000000956 alloy Substances 0.000 description 6
- 230000000694 effects Effects 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229920001721 polyimide Polymers 0.000 description 5
- 239000009719 polyimide resin Substances 0.000 description 5
- 239000000945 filler Substances 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 239000011521 glass Substances 0.000 description 3
- 230000007261 regionalization Effects 0.000 description 3
- 239000000057 synthetic resin Substances 0.000 description 3
- 229920003002 synthetic resin Polymers 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- 229910020836 Sn-Ag Inorganic materials 0.000 description 2
- 229910020935 Sn-Sb Inorganic materials 0.000 description 2
- 229910020988 Sn—Ag Inorganic materials 0.000 description 2
- 229910008757 Sn—Sb Inorganic materials 0.000 description 2
- 238000007664 blowing Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 230000018109 developmental process Effects 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 239000011259 mixed solution Substances 0.000 description 2
- 239000005011 phenolic resin Substances 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 239000004071 soot Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49861—Lead-frames fixed on or encapsulated in insulating substrates
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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- H01L21/4857—Multilayer substrates
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
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- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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Definitions
- the present disclosure relates to a semiconductor device including a semiconductor element, and also to a method for manufacturing the semiconductor device.
- leadless package semiconductor devices such as a small outline non-leaded package (SON package) and a quad flat non-leaded package (QFN package).
- Leadless package semiconductor devices have terminals for external connection, which do not protrude from the sealing resin that seals semiconductor elements. For this reason, the semiconductor devices of this type are advantageous in reducing the size and thickness of the semiconductor devices.
- Such a leadless package semiconductor device is disclosed in JP-A-2016-18846, for example.
- the semiconductor device disclosed in JP-A-2016-18846 includes a semiconductor element, a lead frame, a plurality of wires, and a sealing resin.
- the lead frame is made of copper, for example.
- the lead frame includes a die pad and a plurality of leads.
- the die pad supports the semiconductor element.
- the plurality of leads are electrically connected to the semiconductor element via the plurality of wires.
- the plurality of leads are terminals for external connection when the semiconductor device is mounted on the circuit board of an electronic device or the like.
- the sealing resin covers the semiconductor element.
- a lead frame is formed by processing a metal plate (e.g., copper plate).
- a semiconductor device having such a lead frame has room for improvement in thickness reduction.
- the present disclosure is conceived in view of the above problem, and an object thereof is to provide a thinner semiconductor device and a method for manufacturing the semiconductor device.
- a semiconductor device including: a semiconductor element having an element front surface and an element back surface that face opposite from each other in a thickness direction; an internal electrode electrically connected to the semiconductor element; a sealing resin covering the semiconductor element and a portion of the internal electrode; and an external electrode exposed from the sealing resin and electrically connected to the internal electrode.
- the internal electrode includes a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface facing the element back surface and a wiring layer back surface facing opposite from the wiring layer front surface in the thickness direction.
- the columnar portion protrudes in the thickness direction from the wiring layer front surface.
- the columnar portion has an exposed side surface that faces in a first direction orthogonal to the thickness direction and that is exposed from the sealing resin.
- the external electrode includes a first cover portion covering the exposed side surface.
- a method for manufacturing a semiconductor device includes: preparing a support substrate; forming an internal electrode including a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface and a wiring layer back surface that face opposite from each other in a thickness direction, and the wiring layer back surface faces the support substrate, and the columnar portion protrudes from the wiring layer front surface; conductively bonding a semiconductor element to the wiring layer; forming a sealing resin to cover the semiconductor element and the wiring layer front surface; removing the support substrate; forming an exposed side surface of the columnar portion, where the exposed side surface faces in a first direction orthogonal to the thickness direction and is exposed from the sealing resin; and forming an external electrode to cover the exposed side surface.
- FIG. 1 is a plan view showing a semiconductor device according to a first embodiment
- FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment
- FIG. 3 is a side view showing the semiconductor device according to the first embodiment
- FIG. 4 is a sectional view along line IV-IV in FIG. 1 ;
- FIG. 5 is a main-part enlarged sectional view showing a part of the cross section in FIG. 4 ;
- FIG. 6 is a main-part enlarged sectional view showing a part of the cross section in FIG. 4 ;
- FIG. 7 is a sectional view showing a step of a method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 8 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 9 is a plan view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 10 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 11 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 12 is a plan view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 13 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 14 is a plan view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 15 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 16 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 17 is a plan view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 18 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 19 is a plan view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 20 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 21 is a plan view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 22 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 23 is a plan view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 24 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 25 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 26 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 27 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 28 is a bottom view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 29 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 30 is a bottom view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 31 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 32 is a bottom view showing a step of the method for manufacturing the semiconductor device in FIG. 1 ;
- FIG. 33 is a main-part enlarged sectional view showing a semiconductor device according to a variation of the first embodiment
- FIG. 34 is a sectional view showing a semiconductor device according to a second embodiment
- FIG. 35 is a sectional view showing a semiconductor device according to a third embodiment.
- FIG. 36 is a sectional view showing a semiconductor device according to a fourth embodiment.
- FIG. 37 is a sectional view showing a step of a method for manufacturing the semiconductor device in FIG. 36 ;
- FIG. 38 is a sectional view showing a step of the method for manufacturing the semiconductor device in FIG. 36 ;
- FIG. 39 is a sectional view showing a semiconductor device according to a variation of the fourth embodiment.
- FIG. 40 is a plan view showing a semiconductor device according to a fifth embodiment.
- FIG. 41 is a sectional view along line F-F in FIG. 40 ;
- FIG. 42 is a sectional view showing a semiconductor device according to a sixth embodiment.
- FIG. 43 is a sectional view showing a step of a method for manufacturing the semiconductor device in FIG. 42 ;
- FIG. 44 is a plan view showing a semiconductor device according to a variation
- FIG. 45 is a plan view showing a semiconductor device according to a variation.
- FIG. 46 is a plan view showing a semiconductor device according to a variation
- FIG. 47 is a plan view showing a semiconductor device according to a variation.
- FIG. 48 is a sectional view along line G-G in FIG. 47 .
- FIGS. 1 to 6 show a semiconductor device according to a first embodiment of the present disclosure.
- a semiconductor device A 1 according to the present embodiment includes a semiconductor element 1 , an internal electrode 2 , external electrodes 3 , an insulating film 41 , conductive bonding members 5 , and a sealing resin 6 .
- FIG. 1 is a plan view showing the semiconductor device A 1 .
- FIG. 1 omits the sealing resin 6 .
- FIG. 2 is a bottom view showing the semiconductor device A 1 .
- FIG. 3 is a side view showing the semiconductor device A 1 .
- FIG. 3 shows a side surface of the semiconductor device A 1 as viewed in x direction which is described below.
- FIG. 4 is a sectional view along line IV-IV in FIG. 1 .
- FIG. 5 is a main-part enlarged sectional view showing a part of the cross section in FIG. 4 .
- FIG. 6 is a main-part enlarged sectional view showing a part of the cross section in FIG. 4 .
- the z direction is the thickness direction of the semiconductor device A 1 .
- the x direction is the horizontal direction in the plan view of the semiconductor device A 1 .
- the y direction is the vertical direction in the plan view of the semiconductor device A 1 .
- the x direction and the z direction correspond to the “first direction” and the “thickness direction” in the claims.
- the semiconductor device A 1 is a resin package mounted on a surface of a circuit board in any of various electronic devices. As shown in FIGS. 1 and 2 , the semiconductor device A 1 has a rectangular shape as viewed in the z direction (hereinafter, also referred to as “plan view”). The semiconductor device A 1 in the present embodiment is of a SON package type.
- the semiconductor element 1 is the functional center of the semiconductor device A 1 .
- the semiconductor element 1 is an integrated circuit (IC) such as a large scale integration circuit (LSI).
- the semiconductor element 1 may be a voltage control element such as a low drop out regulator (LDO), an amplifier element such as an operational amplifier, or a discrete semiconductor element such as a diode.
- LDO low drop out regulator
- the semiconductor element 1 is rectangular in plan view.
- the semiconductor element 1 is mounted on the internal electrode 2 .
- the semiconductor element 1 overlaps with the insulating film 41 in plan view.
- the semiconductor element 1 is mounted by flip-chip bonding.
- the semiconductor element 1 has an element front surface 11 and an element back surface 12 .
- the element front surface 11 and the element back surface 12 are spaced apart and face opposite from each other in the z direction.
- the element front surface 11 and the element back surface 12 are both flat.
- the element back surface 12 is formed with electrode pads 13 and a passivation film 14 .
- Each of the electrode pads 13 is rectangular in plan view. As shown in FIG. 6 , the electrode pads 13 are bonded to the respective conductive bonding members 5 .
- Each of the electrode pads 13 includes a first conductive portion 131 and a second conductive portion 132 .
- the first conductive portion 131 is made of aluminum (Al), for example.
- the second conductive portion 132 is composed of a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer that are mutually laminated.
- the Ni layer of the second conductive portion 132 is in contact with the first conductive portion 131 . Since the electrode pads 13 include the second conductive portions 132 , the first conductive portions 131 which are made of Al are prevented from permeating into the conductive bonding members 5 .
- the passivation film 14 covers the element back surface 12 to protect the semiconductor element 1 .
- the passivation film 14 is formed by mutually laminating a Si 3 N 4 layer formed by a plasma CVD method, for example, and a polyimide resin layer formed by coating.
- the passivation film 14 is open in multiple locations (four locations in the present embodiment), and the electrode pads 13 are exposed from the respective openings.
- the internal electrode 2 is a conductor disposed inside the semiconductor device A 1 .
- the internal electrode 2 is electrically connected to the semiconductor element 1 .
- the internal electrode 2 includes wiring layers 21 and columnar portions 22 .
- Each of the wiring layers 21 is composed of a seed layer 210 a and a plating layer 210 b that are mutually laminated.
- the seed layer 210 a is composed of a first layer that contains titanium (Ti) as a main component, and a second layer that contains copper (Cu) as a main component.
- the seed layer 210 a has a thickness of approximately 200 to 800 nm.
- the plating layer 210 b contains Cu as a main component.
- the plating layer 210 b has a dimension of approximately 20 to 50 ⁇ m in the z direction (hereinafter, the dimension being also referred to as “thickness”). Note that the seed layer 210 a and the plating layer 210 b are not limited to those described above in terms of material and thickness.
- the seed layer 210 a and the plating layer 210 b correspond to the “second seed layer” and the “second plating layer” in the claims, respectively.
- Each of the wiring layers 21 includes a wiring-layer front surface 211 , a wiring-layer back surface 212 , and an end surface 213 .
- the wiring-layer front surface 211 faces the element back surface 12 of the semiconductor element 1 in the z direction.
- the semiconductor element 1 is mounted on the wiring-layer front surface 211 via the conductive bonding member 5 .
- the wiring-layer front surface 211 is partially covered with the sealing resin 6 .
- the wiring-layer back surface 212 faces opposite from the wiring-layer front surface 211 in the z direction.
- the wiring-layer back surface 212 has an electrode cover region 212 a and an insulating-film cover region 212 b .
- the electrode cover region 212 a is a region of the wiring-layer back surface 212 , and is covered with the external electrode 3 .
- the insulating-film cover region 212 b is a region of the wiring-layer back surface 212 , and is covered with the insulating film 41 .
- the electrode cover region 212 a is a region of the wiring-layer back surface 212 other than the insulating-film cover region 212 . Furthermore, the electrode cover region 212 a is located more outward in the z direction than the insulating-film cover region 212 b. Accordingly, the wiring-layer back surface 212 has a step.
- the end surface 213 intersects with the wiring-layer back surface 212 and faces outward in the x direction. In the illustrated example, the end surface 213 also intersects with the wiring-layer front surface 211 . The end surface 213 is covered with the external electrode 3 . Accordingly, the end surface 213 is not visible from outside the semiconductor device A 1 .
- the columnar portions 22 protrude from the wiring layers 21 (wiring-layer front surfaces 211 ) in the z direction.
- the internal electrode 2 has four columnar portions 22 .
- Each of the columnar portions 22 has a rectangular columnar shape having a rectangular cross section along the x-y plane. Note that each of the columnar portions 22 may have another shape such as a cylindrical shape or a polygonal columnar shape.
- the columnar portions 22 are larger in dimension than the wiring layers 21 in z direction.
- Each of the columnar portions 22 is composed of a seed layer 220 a and a plating layer 220 b that are mutually laminated.
- the seed layer 220 a is composed of a first layer that contains Ti as a main component, and a second layer that contains Cu as a main component.
- the seed layer 220 a has a thickness of approximately 200 to 800 nm.
- the plating layer 220 b contains Cu as a main component. Accordingly, the plating layer 210 b and the plating layer 220 b are made of the same material.
- the plating layer 220 b has a thickness of approximately 50 to 100 ⁇ m. Note that the seed layer 220 a and the plating layer 220 b are not limited to those described above in terms of material and thickness.
- the seed layer 220 a and the plating layer 220 b correspond to the “first seed layer” and the “first plating layer” in the claims, respectively.
- each of the columnar portions 22 has a base end surface 221 , a top surface 222 , an exposed side surface 223 , and a resin abutment side surface 224 .
- the base end surface 221 is in contact with the wiring layer 21 .
- the base end surface 221 is flat.
- the top surface 222 faces opposite from the base end surface 221 in the z direction.
- the top surface 222 is flat.
- the top surface 222 is covered with the sealing resin 6 .
- the top surface 222 overlaps with the semiconductor element 1 as viewed in the x direction. In other words, the top surface 222 is arranged between the element front surface 11 and the element back surface 12 in the z direction.
- the exposed side surface 223 and resin abutment side surface 224 of each columnar portion 22 face in either one of the x direction and the y direction that are orthogonal to the z direction. In the present embodiment, the exposed side surface 223 faces outward in the x direction.
- the exposed side surface 223 is exposed from the sealing resin 6 .
- the exposed side surface 223 is flush with the end surface 213 .
- the resin abutment side surface 224 abuts on and is covered with the sealing resin 6 .
- the internal electrode 2 has a dimension d 1 in the z direction as shown in FIG. 5 , and the dimension d 1 may be set to 100 ⁇ m or greater. Alternatively, the dimension d 1 in the z direction maybe approximately 100 to 150 ⁇ m.
- surfaces that abut on the sealing resin 6 i.e., the wiring-layer front surfaces 211 , the top surfaces 222 , and the resin abutment side surfaces 224 ) are roughened to have a roughness of 2 to 3 ⁇ m through a roughening process in the manufacturing method described below.
- the surfaces that abut on the sealing resin 6 are rougher than the wiring-layer back surfaces 212 , but smoother than the exposed side surfaces 223 .
- the exposed side surfaces 223 are rougher than the surfaces that abut on the sealing resin 6 .
- the external electrodes 3 are conductors electrically connected to the internal electrode 2 , and are exposed to the outside of the semiconductor device A 1 .
- the external electrodes 3 are terminals used when the semiconductor device A 1 is mounted on a circuit board.
- the external electrodes 3 are formed by electroless plating.
- Each of the external electrodes 3 is composed of a Ni layer, a Pd layer, and a Au layer that are mutually laminated.
- the Ni layer is in contact with the internal electrode 2 , and has a thickness of approximately 5 ⁇ m.
- the Au layer is exposed to the outside, and has a thickness of approximately 0.01 to 0.02 ⁇ m.
- the pd layer is interposed between the Ni layer and the Au layer, and has a thickness of approximately 0.01 to 0.02 ⁇ m. Note that the external electrodes 3 are not limited in terms of quantity, thickness, material, and forming method.
- each of the external electrodes 3 includes a first cover portion 31 , a second cover portion 32 , and a third cover portion 33 .
- the first cover portion 31 covers the exposed side surface 223 of the columnar portion 22 .
- the second covering portion 32 covers the end surface 213 of the wiring layer 21 .
- the third cover portion 33 covers a portion (electrode cover region 212 a ) of the wiring-layer back surface 212 of the wiring layer 21 .
- two external electrodes 3 are seen on each of the two side surfaces of the semiconductor device A 1 that face in the x direction, and four external electrodes 3 are seen from the bottom surface of the semiconductor device A 1 .
- the first cover portion 31 , the second cover portion 32 , and the third cover portion 33 are formed integrally.
- the external electrodes 3 are insulated from each other by the insulating film 41 .
- the insulating film 41 is made of an insulating material, such as a polyimide resin or a phenol resin.
- the insulating film 41 is provided at the bottom surface of the semiconductor device A 1 .
- the insulating film 41 is arranged lower than the sealing resin 6 in the z direction. As shown in FIG. 1 , the insulating film 41 is rectangular in plan view. Note that the insulating film 41 may have a shape other than a rectangle in plan view.
- the insulating film 41 corresponds to the “first insulating film” in the claims.
- the insulating film 41 has an insulating film front surface 411 and an insulating film back surface 412 that face opposite from each other in the z direction.
- the insulating film front surface 411 faces in the same direction as the element front surface 11 of the semiconductor element 1 , and faces the element back surface 12 of the semiconductor element 1 .
- the insulating film back surface 412 faces in the same direction as the element back surface 12 .
- the insulating film front surface 411 is in contact with portions (insulating-film cover regions 212 b ) of the wiring-layer back surfaces 212 of the wiring layers 21 .
- the insulating film back surface 412 is flush with portions (electrode cover regions 212 a ) of the wiring-layer back surfaces 212 of the wiring layers 21 .
- the conductive bonding members 5 are conductive members interposed between the wiring layers 21 of the internal electrode 2 and the electrode pads 13 of the semiconductor element 1 .
- Each of the conductive bonding members 5 is made of a Ni layer in contact with the wiring layer 21 , and a solder layer in contact with the Ni layer.
- the solder layer is made of an alloy containing tin (Sn). Examples of such an alloy include lead-free solder such as a Sn—Sb-based alloy or a Sn—Ag-based alloy, and solder containing lead (Pb).
- the semiconductor element 1 is fixed to the wiring layers 21 (internal electrode 2 ) by the conductive bonding members 5 .
- the sealing resin 6 may be a synthetic resin containing black epoxy resin as a main component. As shown in FIG. 4 , the sealing resin 6 covers the semiconductor element 1 , a portion of the internal electrode 2 , and the conductive bonding members 5 .
- the sealing resin 6 has a resin front surface 61 , a resin back surface 62 , and a plurality of resin side surfaces 63 .
- the resin front surface 61 faces in the same direction as the element front surface 11 .
- the resin back surface 62 faces in the same direction as the element back surface 12 .
- the resin back surface 62 is in contact with the internal electrode 2 and the insulating film 41 .
- the resin side surfaces 63 are orthogonal to the resin front surface 61 and the resin back surface 62 .
- the sealing resin 6 has two resin side surfaces 63 facing opposite from each other in the x direction, and another two resin side surfaces 63 facing opposite from each other in the y direction.
- two external electrodes 3 are exposed from each of the two resin side surfaces 63 facing in the x direction, as shown in FIG. 3 . In plan view, the external electrodes 3 are located more outward of the semiconductor device A 1 than the two resin side surfaces 63 facing in the x direction.
- FIGS. 7 to 32 are plan views showing steps of the method for manufacturing the semiconductor device A 1
- FIGS. 28 , 30 , and 32 are bottom views showing steps of the method for manufacturing the semiconductor device A 1 .
- the rest of the figures are sectional views showing steps of the method for manufacturing the semiconductor device A 1 .
- the cross-sections shown in these figures correspond to the cross-section shown in FIG. 4 .
- the cross-sections in FIGS. 25 - 27 , FIG. 29 , and FIG. 31 are shown upside down in the z direction with respect to the other sectional views.
- a support substrate 800 is prepared (support substrate preparation step).
- the support substrate 800 has a front surface 800 a and a back surface 800 b facing in the z direction.
- the support substrate 800 may be a glass substrate or a silicon (Si) substrate.
- the support substrate 800 is a glass substrate having a light-transmissive property.
- the support substrate 800 has a thickness of approximately 0.5 ⁇ m.
- a temporary fixing member 801 is formed on the support substrate 800 (temporary fixing member forming step). In this step, the temporary fixing member 801 is formed to cover the entirety of the front surface 800 a. Then, as shown in FIG.
- a sputter film 802 is formed on the temporary fixing member 801 (sputter film formation step). In this step, the sputter film 802 is formed to cover the entirety of the temporary fixing member 801 .
- the sputter film 802 is a metal film containing Ti as a main component.
- insulating films 841 are formed, as shown in FIGS. 8 and 9 (insulating film formation step).
- One of the insulating films 841 correspond to the insulating film 41 of the semiconductor device A 1 .
- Each of the insulating films 841 is made of a photosensitive resin material such as a polyimide resin or a phenol resin.
- the insulating films 841 are formed on the sputter film 802 with use of a spin coater (rotary coating device), for example, as shown in FIG. 8 .
- a film-like photosensitive resin material may be attached.
- patterning may be performed by exposing and developing the photosensitive resin material.
- the insulating films 841 are formed as shown in FIGS.
- the sputter film 802 has portions covered with the insulating films 841 and portions exposed from the insulating films 841 .
- the portions where the sputter film 802 is exposed from the insulating films 841 will ultimately become portions corresponding to the electrode cover regions 212 a of the wiring layers 21 in the semiconductor device A 1 .
- a seed layer 820 a is formed as shown in FIG. 10 (preceding seed layer formation step). Portions of the seed layer 820 a will ultimately correspond to portions of the internal electrode 2 (specifically, the seed layers 210 a of the wiring layers 21 ) in the semiconductor device A 1 .
- the seed layer 820 a is formed by sputtering.
- the seed layer 820 a is formed across all surfaces on the front surface 800 a side of the support substrate 800 .
- the seed layer 820 a is composed of a Ti layer and a Cu layer that are mutually laminated. In the preceding seed layer formation step, the Ti layer is first formed to be in contact with the insulating films 841 and the sputter film 802 , and the Cu layer is then formed on the Ti layer.
- plating layers 820 b are formed (preceding plating layer formation step).
- the plating layers 820 b correspond to portions of the internal electrode 2 (specifically, the plating layers 210 b of the wiring layers 21 ) of the semiconductor device A 1 .
- the plating layers 820 b are formed by pattern formation through photolithography and electrolytic plating.
- a resist layer (not shown) for forming the plating layers 820 b is first formed through photolithography.
- a photosensitive resist is applied to cover the entire surface of the seed layer 820 a, and the photosensitive resist is patterned by exposure and development.
- the patterning exposes portions of the seed layer 820 a (portions for forming the plating layers 820 b ). Then, the plating layers 820 b are formed on the exposed portions of the seed layer 820 a through electrolytic plating using the seed layer 820 a as a conductive path. Subsequently, the resist layer is removed to thereby form the plating layers 820 b as shown in FIGS. 11 and 12 .
- unnecessary portions of the seed layer 820 a that are not covered with the plating layers 820 b are all removed (preceding seed layer removal step).
- the unnecessary portions of the seed layer 820 a are removed by wet etching.
- the wet etching is performed with use of a mixed solution of sulfuric acid (H 2 SO 4 ) and hydrogen peroxide (H 2 O 2 ).
- H 2 SO 4 sulfuric acid
- H 2 O 2 hydrogen peroxide
- wiring layers 821 which are composed of seed layers 820 a and the plating layers 820 b, are formed.
- the wiring layers 821 correspond to the wiring layers 21 of the internal electrode 2 of the semiconductor device A 1 . Accordingly, the wiring layers 821 are formed through a wiring layer formation step that includes the preceding seed layer formation step, the preceding plating layer formation step, and the preceding seed layer removal step.
- a seed layer 820 c is formed as shown in FIG. 15 (succeeding seed layer formation step). Portions of the seed layer 820 c will ultimately correspond to portions of the internal electrode 2 (specifically, the seed layers 220 a of the columnar portions 22 ) in the semiconductor device A 1 .
- the seed layer 820 c is formed by sputtering.
- the seed layer 820 c is formed across all surfaces on the front surface 800 a side of the support substrate 800 .
- the seed layer 820 c is composed of a Ti layer and a Cu layer that are mutually laminated.
- the Ti layer is formed to be in contact with either the insulating films 841 or the plating layers 820 b , and the Cu layer is then formed to be in contact with the Ti layer.
- plating layers 820 d are formed (succeeding plating layer formation step).
- the plating layers 820 d correspond to portions of the internal electrode 2 (specifically, the plating layers 220 b of the columnar portions 22 ) of the semiconductor device A 1 .
- the plating layers 820 d are formed by pattern formation through photolithography and electrolytic plating.
- a resist layer (not shown) for forming the plating layers 820 d is first formed through photolithography.
- a photosensitive resist is applied to cover the entire surface of the seed layer 820 c, and the photosensitive resist is patterned by exposure and development.
- the patterning exposes portions of the seed layer 820 c (portions for forming the plating layers 820 d ). Then, the plating layers 820 d are formed on the exposed portions of the seed layer 820 c through electrolytic plating using the seed layer 820 c as a conductive path. Subsequently, the resist layer is removed to thereby form the plating layers 820 d as shown in FIGS. 16 and 17 .
- conductive bonding members 85 are formed (conductive bonding members formation step).
- the conductive bonding members 85 correspond to the conductive bonding members 5 of the semiconductor device A 1 .
- the conductive bonding members 85 are formed by pattern formation through photolithography and electrolytic plating.
- a resist layer (not shown) for forming the conductive bonding members 85 is first formed on the seed layer 820 c, and the resist layer is patterned. The patterning exposes portions of the seed layer 820 c (portions for forming the conductive bonding members 85 ). Then, the conductive bonding members 85 are formed on the exposed portions through electrolytic plating using the seed layer 820 c as a conductive path.
- first conductive layers are formed to be in contact with the seed layer 820 c, and second conductive layers are then formed to be in contact with the first conductive layers.
- each of the first conductive layers contains Ni as a main component
- each of the second conductive layers contains lead-free solder such as a Sn—Ag-based alloy or a Sn—Sb-based alloy. Subsequently, the resist layer is removed.
- columnar portions 822 that are composed of seed layers 820 c and the plating layers 820 d , are formed.
- the columnar portions 822 correspond to the columnar portions 22 of the internal electrode 2 in the semiconductor device A 1 . Accordingly, the columnar portions 822 are formed through a columnar portion formation step that includes the succeeding seed layer formation step, the succeeding plating layer formation step, and the succeeding seed layer removal step. Since the wiring layers 821 and the columnar portions 822 are included in an internal electrode 82 , a step of forming the internal electrode 82 (internal electrode formation step) includes the wiring layer formation step and the columnar portion formation step.
- a chemical solution used for the roughening process is not particularly limited as long as the solution reacts with the material (Cu) of the internal electrode 82 (the wiring layers 821 and the columnar portions 822 ).
- the surfaces of the wiring layers 821 and the columnar portions 822 are roughened.
- the roughness of the surfaces is approximately 2 to 3 ⁇ m, for example.
- semiconductor elements 81 are mounted (semiconductor element mounting step). Note that in FIG. 22 and the subsequent figures, the seed layers 820 a and the plating layers 820 b are collectively shown as the wiring layers 821 with no distinction therebetween. Similarly, the seed layers 820 c and the plating layers 820 d are collectively shown as the columnar portions 822 with no distinction therebetween.
- One of the semiconductor elements 81 corresponds to the semiconductor element 1 in the semiconductor device A 1 .
- the semiconductor element mounting step is performed through flip chip bonding (FCB). First, flux is applied to electrode pads (not shown) of the semiconductor elements 81 .
- the semiconductor elements 81 are temporarily attached to the conductive bonding members 85 via a flip chip bonder.
- the conductive bonding members 85 are sandwiched between the wiring layers 821 and the semiconductor elements 81 .
- the conductive bonding members 85 are melted by reflow.
- the conductive bonding members 85 are cooled and solidified, after which mounting of the semiconductor elements 81 is completed.
- a sealing resin 86 is formed to cover the semiconductor elements 81 (sealing resin formation step), as shown in FIG. 24 .
- the sealing resin 86 corresponds to the sealing resin 6 of the semiconductor device A 1 .
- the sealing resin 86 is a synthetic resin having an electrically insulating property, such as a synthetic resin containing a black epoxy resin as a main component.
- the sealing resin 86 is formed over the support substrate 800 such that the semiconductor elements 81 are completely covered without exposure.
- the sealing resin 86 formed in this step has a resin front surface 861 . As shown in FIG. 24 , the wiring layers 821 and the columnar portions 822 are also covered with the sealing resin 86 .
- the sealing resin 86 may be ground from the resin front surface 861 to reduce the thickness of the sealing resin 86 . During this process, the sealing resin 86 may be ground until the upper surfaces of the semiconductor elements 81 are exposed from the sealing resin 86 .
- the support substrate 800 is peeled off (support substrate peeling step).
- a dicing tape 804 is attached to the resin front surface 861 , as shown in FIG. 25 .
- laser irradiation is performed from the back surface 800 b of the support substrate 800 , for example.
- the laser beam passes through the support substrate 800 to irradiate the temporary fixing member 801 . This weakens the adhesive strength of the temporary fixing member 801 , allowing the support substrate 800 to be peeled off.
- the temporary fixing member 801 partially remains (e.g., as soot) after the support substrate 800 is peeled off, the remaining bits of the temporary fixing member 801 may be removed by plasma. As a result of the above process, the support substrate 800 and the temporary fixing member 801 are removed as shown in FIG. 26 .
- the support substrate peeling step may be performed through a method other than laser irradiation. For example, an element such as the support substrate 800 may be peeled off by blowing air in the x direction (horizontal direction in FIG. 25 ). Alternatively, an element such as the support substrate 800 can be peeled off by heating and softening the temporary fixing member 801 .
- the support substrate 800 be made of a material having an appropriate light-transmissive property, so that the laser beam can pass through the support substrate 800 .
- the support substrate 800 maybe a Si substrate instead of a glass substrate.
- the sputter film 802 is removed (sputter film removal step), as shown in FIGS. 27 and 28 .
- insulating film back surfaces 841 b of the insulating films 841 and wiring layer back surfaces 821 b of the wiring layers 821 are exposed.
- the sealing resin 86 is cut along the x and y directions so as to be divided into a plurality of pieces that respectively include the semiconductor elements 81 .
- the step of cutting the sealing resin 86 is performed by blade dicing.
- the cutting is performed along the cut line CL shown in FIGS. 27 and 28 to obtain the plurality of pieces respectively including the semiconductor elements 81 .
- the width in the lateral direction is the thickness of the dicing blade.
- the dicing tape 804 is not completely cut in the z direction (although it is cut slightly), as shown in FIG. 27 .
- external electrodes 83 are formed (external electrode formation step).
- the external electrodes 83 correspond to the external electrodes 3 of the semiconductor device A 1 .
- the external electrode formation step is performed through electroless plating.
- a Ni layer, a Pd layer, and a Au layer are deposited in the stated order by electroless plating.
- the Ni layer is formed to be in contact with and cover the surfaces of the wiring layers 821 and the surfaces of the columnar portions 822 that are respectively exposed from the insulating films 841 and the sealing resin 86 .
- the Pd layer is formed on the Ni layer, and then the Au layer is formed on the Pd layer.
- the external electrodes 83 are not deposited on the insulating films 841 .
- the external electrodes 83 are formed as shown in FIGS. 31 and 32 .
- the semiconductor device A 1 as shown in FIGS. 1 to 6 is manufactured through the above-described steps.
- the semiconductor device A 1 includes the internal electrode 2 formed by electrolytic plating, and the external electrodes 3 formed by electroless plating.
- the semiconductor device A 1 uses wires formed by plating, and do not use any lead frame formed with a metal plate.
- the wires formed by plating can be reduced in thickness as compared to the lead frame structure. This allows for thinning of the semiconductor device A 1 .
- the number of terminals has increased, and this necessitates miniaturization of internal electrodes and the like. In such a case, using a lead frame limits miniaturization because such a frame is created by processing a metal plate.
- the internal electrode 2 is formed by plating to allow miniaturization. This makes it possible to manufacture a semiconductor device having a larger number of terminals.
- the internal electrode 2 includes the wiring layers 21 that each have the end surface 213 exposed from the resin side surface 63 , and the columnar portion 22 that each have the exposed side surface 223 exposed from the resin side surface 63 .
- the external electrodes 3 each include the first cover portion 31 that covers the exposed side surface 223 , and the second cover portion 32 that covers the end surface 213 .
- portions of the external electrodes 3 formed on the side surfaces (side surfaces facing in the x direction in the present embodiment) of the semiconductor device A 1 can have a larger dimension in the z direction than in the case where the columnar portions 22 are not provided.
- the semiconductor device A 1 is mounted on a circuit board or the like by using solder.
- portions of the external electrodes 3 formed on the side surfaces of the semiconductor device A 1 will simply be the second cover portions 32 .
- the dimension of the second cover portions 32 alone in the z direction is not large enough to easily form soldering fillets when the semiconductor device A 1 is mounted on a circuit board.
- the present embodiment makes it possible to increase the dimension of the external electrodes 3 in the z direction which are formed on the side surfaces of the semiconductor device A 1 . In this way, solder fillets can be formed when the semiconductor device A 1 is mounted on a circuit board or the like. As a result, the mounting strength of the semiconductor device A 1 with respect to the circuit board can be enhanced. Furthermore, the connection state of solder can be visually checked from the side surfaces of the semiconductor device A 1 .
- a roughening process is performed during the manufacturing process of the semiconductor device A 1 .
- the roughening process causes the wiring-layer front surfaces 211 , the top surfaces 222 , and the resin abutment side surfaces 224 to be roughened. This structure can enhance the adhesion between the internal electrode 2 and the sealing resin 6 .
- the angle formed between each pair of the wiring-layer back surfaces 212 and the end surfaces 213 is approximately orthogonal.
- a protrusion may be formed at a junction between any pair of the wiring-layer back surfaces 212 and the end surfaces 213 .
- FIG. 33 shows a main-part enlarged sectional view when such a protrusion is created.
- FIG. 33 corresponds to the main-part enlarged sectional view in FIG. 5 .
- a protrusion 214 protrudes from the wiring-layer back surface 212 of the wiring layer 21 in the z direction.
- the external electrode 3 is formed to cover the protrusion 214 .
- the protrusion 214 may have a shape other than the one shown in FIG. 33 .
- the protrusion 214 may protrude in a direction other than the z direction, such as the x direction or the y direction.
- the external electrodes 3 are exposed from the insulating film 41 when the semiconductor device A 1 is viewed from the bottom surface (see FIG. 2 ).
- other elements such as a portion of the resin back surface 62 , may be exposed from the insulating film 41 .
- FIG. 34 shows a semiconductor device according to a second embodiment.
- a semiconductor device A 2 according to the present embodiment differs from the semiconductor device A 1 (first embodiment) in further including a metal layer 7 .
- FIG. 34 is a sectional view showing the semiconductor device A 2 .
- the cross-section shown in FIG. 34 corresponds to the cross-section shown in FIG. 4 for the first embodiment.
- the insulating film 41 has an opening 413 .
- the opening 413 continues from the insulating film front surface 411 to the insulating film back surface 412 in the z direction.
- the opening 413 is rectangular in plan view, but may have any other shape in other embodiments.
- the opening 413 is formed by patterning in the insulating film formation step described above.
- the internal electrode 2 further includes a filler portion 23 .
- the filler portion 23 is a portion of the internal electrode 2 that fills the opening 413 of the insulating film 41 .
- the filler portion 23 is formed in the wiring layer formation step described above.
- the metal layer 7 is made of a conductive metal material.
- the metal layer 7 is formed by electroless plating as in the external electrodes 3 .
- the metal layer 7 is composed of a Ni layer, a Pd layer, and a Au layer that are mutually laminated. Note that the material and forming method of the metal layer 7 are not limited to those described above.
- the metal layer 7 is in contact with the filler portion 23 and exposed to the outside of the semiconductor device A 2 .
- the semiconductor device A 2 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A 2 can be made thinner.
- the semiconductor device A 2 includes the metal layer 7 .
- the semiconductor element 1 When the semiconductor device A 2 is energized, the semiconductor element 1 generates heat. The heat generated from the semiconductor element 1 is transferred to the metal layer 7 and released to the outside. Accordingly, the metal layer 7 functions as a heat dissipator in the semiconductor device A 2 .
- the metal layer 7 is made of metal and has conductivity. Accordingly, the metal layer 7 can also be used as a terminal for external connection.
- the metal layer 7 is formed by electroless plating as in the external electrodes 3 . Accordingly, the external electrodes 3 and the metal layer 7 can be formed at the same time.
- FIG. 35 shows a semiconductor device according to a third embodiment.
- a semiconductor device A 3 according to the present embodiment differs from the semiconductor device A 1 (first embodiment) in further including an insulating film 42 .
- FIG. 35 is a sectional view showing the semiconductor device A 3 .
- the cross-section shown in FIG. 35 corresponds to the cross-section shown in FIG. 4 for the first embodiment.
- the insulating film 42 is made of an insulating material, such as a polyimide resin.
- the insulating film 42 is sandwiched between the internal electrode 2 and the sealing resin 6 .
- the insulating film 42 may be formed by photolithography.
- the insulating film 42 is formed after the roughening process and before the semiconductor element mounting step. This means that the insulating film 42 is formed after the conductive bonding members 5 ( 85 ) are formed. Accordingly, the insulating film 42 has through-holes 421 filled with the conductive bonding members 5 .
- the insulating film 42 corresponds to the “second insulating film” in the claims.
- the semiconductor device A 3 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A 3 can be made thinner.
- the insulating film 42 has the through-holes 421 , and portions of the conductive bonding members 5 fill the through-holes 421 .
- the conductive bonding members 85 are softened by ref low in the semiconductor element mounting step. In this process, the softened conductive bonding members 85 may spread along the wiring-layer front surfaces 211 . However, in the present embodiment, the wiring-layer front surfaces 211 are covered with the insulating film 42 . This prevents the conductive bonding members 5 ( 85 ) from spreading along the wiring-layer front surfaces 211 .
- FIG. 36 shows a semiconductor device according to a fourth embodiment.
- a semiconductor device A 4 according to the present embodiment differs from the semiconductor device A 1 (first embodiment) in that the resin side surfaces 63 of the sealing resin 6 have dents.
- FIG. 36 is a sectional view showing the semiconductor device A 4 .
- the cross-section shown in FIG. 36 corresponds to the cross-section shown in FIG. 4 for the first embodiment.
- each of the resin side surfaces 63 includes a resin side surface first portion 631 and a resin side surface second portion 632 , as shown in FIG. 36 .
- the resin side surface first portion 631 and the resin side surface second portion 632 are both flat.
- the resin side surface first portion 631 is arranged more outward than the resin side surface second portion 632 in plan view.
- the resin side surface second portion 632 is flush with the exposed side surface 223 of the columnar portion 22 and the end surface 213 of the wiring layer 21 .
- FIGS. 37 and 38 are sectional views showing steps of manufacturing the semiconductor device A 4 .
- steps from the support substrate preparation step (see FIG. 7 ) through the sputter film removal step (see FIGS. 27 and 28 ) are performed in the same manner as in the first embodiment. Note that in the present embodiment, it is not necessary to attach the dicing tape 804 in the support substrate peeling step. Subsequently, grooves 89 are formed as shown in FIG. 37 .
- the step of forming the grooves 89 may be performed through half-cut dicing using a dicing blade. In the half-cut dicing, the sealing resin 86 is not completely cut in the z direction so as to form the grooves 89 .
- the depth of the grooves 89 is determined by the cut amount during the half-cut dicing, and the width of the grooves 89 is determined by the thickness of the dicing blade.
- the end surfaces 821 c of the wiring layers 821 and the exposed side surfaces 822 c of the columnar portions 822 which are exposed from the sealing resin 86 , are formed by half-cut dicing.
- the external electrodes 83 are formed.
- the external electrode formation step is performed through electroless plating in the same manner as in the first embodiment.
- the external electrodes 83 are formed to cover the respective surfaces of the wiring layers 821 and the columnar portions 822 that are exposed from the sealing resin 86 .
- the sealing resin 86 is cut along the cut line CL 2 shown in FIG. 38 so as to be divided into a plurality of pieces that respectively include the semiconductor elements 81 .
- the dicing blade used when cutting along the cut line CL 2 is thinner than the dicing blade used during the half -cut dicing described above.
- the semiconductor device A 4 as shown in FIG. 36 is manufactured through the above-described steps. That is, the semiconductor device A 4 is manufactured to include the resin side surfaces 63 of the sealing resin 6 that have dents.
- the semiconductor device A 4 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A 4 can be made thinner.
- the dicing tape 804 is not attached in the support substrate peeling step.
- the sealing resin 86 is completely cut along the z direction. Accordingly, it is necessary to use the dicing tape 804 to hold the individual pieces together for the external electrode formation step (electroless plating).
- the pieces of the sealing resin 86 are continuous and do not fall apart even without the dicing tape 804 during the external electrode formation step. Accordingly, the dicing tape 804 is not necessary in the method for manufacturing the semiconductor device A 4 .
- the resin side surfaces 63 have dents.
- the exposed side surfaces 223 of the columnar portions 22 may have dents.
- FIG. 39 shows the case where the exposed side surfaces 223 have dents.
- FIG. 39 is a sectional view showing a semiconductor device according to such a variation as described above, and corresponds to FIG. 36 .
- each of the exposed side surfaces 223 includes an exposed side surface first portion 223 a and an exposed side surface second portion 223 b.
- the exposed side surface first portion 223 a and the exposed side surface second portion 223 b are both flat.
- the exposed side surface first portion 223 a is arranged more outward than the exposed side surface second portion 223 b in plan view.
- the exposed side surface first portion 223 a is flush with the resin side surface 63 .
- the exposed side surface second portion 223 b is flush with the end surface 213 of the wiring layer 21 .
- the exposed side surface first portion 223 a is not covered with the external electrode 3
- the exposed side surface second portion 223 b is covered with the external electrode 3 .
- the exposed side surface 223 is created by forming a shallower groove 89 (see FIG. 37 ) during the half-cut dicing.
- the amount of cut during the half-cut dicing is reduced so as not to completely cut the columnar portion 822 in the z direction.
- the exposed side surfaces 223 that each include the exposed side surface first portion 223 a and the exposed side surface second portion 223 b are formed.
- FIGS. 40 and 41 show a semiconductor device according to a fifth embodiment.
- a semiconductor device A 5 according to the present embodiment differs from the semiconductor device A 1 (first embodiment) in that the columnar portions 22 include protrusions 225 .
- FIG. 40 is a plan view showing the semiconductor device A 5 .
- FIG. 40 omits the sealing resin 6 .
- FIG. 41 is a sectional view along line F-F in FIG. 40 .
- the columnar portions 22 include the protrusions 225 .
- the protrusions 225 protrude from the respective resin abutment side surfaces 224 facing in the y direction in plan view.
- two protrusions 225 protrude from two respective resin abutment side surfaces 224 facing in the y direction.
- Each of the protrusions 225 has an engagement surface 225 a.
- the engagement surface 225 a protrudes from the resin abutment side surface 224 .
- the engagement surface 225 a and the resin abutment side surface 224 form a right angle.
- the engagement surface 225 a is orthogonal to the resin abutment side surface 224 .
- the engagement surface 225 a maybe inclined to the resin abutment side surface 224 .
- the engagement surface 225 a faces outward in the x direction in plan view. Accordingly, the engagement surface 225 a is parallel to a y-z plane.
- the engagement surface 225 a is in contact with the sealing resin 6 . In the x direction, the sealing resin 6 is interposed between the engagement surface 225 a and the resin side surface 63 .
- the semiconductor device A 5 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A 5 can be made thinner.
- the columnar portions 22 include the protrusions 225 .
- the protrusions 225 have the engagement surfaces 225 a.
- Each of the engagement surfaces 225 a protrudes from the resin abutment side surface 224 and is in contact with the sealing resin 6 .
- the engagement surface 225 a is caught by the sealing resin 6 . Accordingly, the semiconductor device A 5 prevents the internal electrode 2 from slipping out in the x direction.
- FIG. 42 shows a semiconductor device according to a sixth embodiment.
- a semiconductor device A 6 according to the present embodiment differs from the semiconductor device A 1 (first embodiment) in that the columnar portions 22 include protrusions 226 .
- FIG. 42 is a sectional view showing a semiconductor device A 6 .
- the cross-section shown in FIG. 42 corresponds to the cross-section shown in FIG. 4 for the first embodiment.
- the top surfaces 222 of the columnar portions 22 are curved as shown in FIG. 42 .
- the columnar portions 22 include protrusions 226 as shown in FIG. 42 .
- the protrusions 226 protrude from the respective resin abutment side surfaces 224 in plan view.
- Each of the protrusions 226 has an engagement surface 226 a.
- the engagement surface 226 a protrudes from the resin abutment side surface 224 .
- the engagement surface 226 a and the resin abutment side surface 224 form a right angle.
- the engagement surface 226 a is orthogonal to the resin abutment side surface 224 .
- the engagement surface 226 a maybe inclined to the resin abutment side surface 224 .
- the engagement surface 226 a faces downward in the z direction (downward in FIG. 42 ). Accordingly, the engagement surface 226 a is parallel to a x-y plane.
- the engagement surface 226 a is in contact with the sealing resin 6 .
- FIG. 43 is a diagram for explaining a method for forming the protrusions 226 .
- FIG. 43 shows a succeeding plating layer formation step of the manufacturing method according to the present embodiment.
- a resist layer 805 is patterned by photolithography in areas other than the areas on which the plating layers 820 d are to be formed, in the same manner as in the first embodiment. Thereafter, the plating layers 820 d are laminated by electrolytic plating. In this process, the electrolytic plating is continued until thickness of each of the plating layers exceeds the thickness of the patterned resist layer 805 , so that the plating layers 820 d grow along the top surface of the resist layer 805 . Then, the resist layer 805 is removed to thereby form the protrusions 226 of the columnar portions 22 .
- the semiconductor device A 6 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A 6 can be made thinner.
- the columnar portions 22 include the protrusions 226 .
- the protrusions 226 have the engagement surfaces 226 a.
- Each of the engagement surfaces 226 a protrudes from the resin abutment side surface 224 and is in contact with the sealing resin 6 .
- the engagement surface 226 a is caught by the sealing resin 6 . Accordingly, the semiconductor device A 6 prevents the internal electrode 2 from slipping out in the z direction.
- FIGS. 44 to 46 are plan views.
- the conductive bonding members 5 and the sealing resin 6 are omitted, and the semiconductor element 1 is indicated by an imaginary line (two-dot chain line).
- regions 19 indicated by imaginary lines may be provided with elements such as resistors, capacitors, or other semiconductor elements.
- first to sixth embodiments have given an example of a SON resin package having terminals on two side surfaces of the semiconductor device (two resin side surfaces 63 facing in the x direction in the above examples), other examples are also possible.
- one wiring layer 21 is provided in the z direction.
- a plurality of wiring layers 21 may be provided in the z direction.
- FIGS. 47 and 48 show a semiconductor device having a multi-layer structure with two wiring layers 21 (a first wiring layer 21 A and a second wiring layer 21 B) in the z direction.
- FIG. 47 is a plan view showing the semiconductor device.
- FIG. 47 omits the sealing resin 6 .
- FIG. 48 is a sectional view along line G-G in FIG. 47 .
- the internal electrode 2 includes first wiring layers 21 A, second wiring layers 21 B, and columnar portions 22 .
- Parts of the first wiring layers 21 A and the second wiring layers 21 B are in contact with each other, whereas the other parts of these layers 21 A and 21 B are insulated from each other by an insulating film 43 .
- the insulating film 43 is made of a polyimide resin, for example.
- the columnar portions 22 protrude from the second wiring layers 21 B in the z direction. In this way, the columnar portions 22 may also be provided for the semiconductor device with a multi-layer structure where the plurality of wiring layers 21 are provided in the z direction.
- the semiconductor device according to the present disclosure and the method for manufacturing the semiconductor device are not limited to those described in the above embodiments. Various design changes can be made to the specific structures of the elements of the semiconductor device according to the present disclosure, and to the details of the steps of the method for manufacturing the semiconductor device.
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Abstract
A semiconductor device includes a semiconductor element, an internal electrode connected to the semiconductor element, a sealing resin covering the semiconductor element and a portion of the internal electrode, and an external electrode exposed from the sealing resin and connected to the internal electrode. The internal electrode includes a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface facing the back surface of the semiconductor element and a wiring layer back surface facing opposite from the wiring layer front surface in the thickness direction. The columnar portion protrudes in the thickness direction from the wiring layer front surface. The columnar portion has an exposed side surface facing in a direction perpendicular to the thickness direction. The external electrode includes a first cover portion covering the exposed side surface.
Description
- The present disclosure relates to a semiconductor device including a semiconductor element, and also to a method for manufacturing the semiconductor device.
- In recent years, there have been leadless package semiconductor devices such as a small outline non-leaded package (SON package) and a quad flat non-leaded package (QFN package). Leadless package semiconductor devices have terminals for external connection, which do not protrude from the sealing resin that seals semiconductor elements. For this reason, the semiconductor devices of this type are advantageous in reducing the size and thickness of the semiconductor devices. Such a leadless package semiconductor device is disclosed in JP-A-2016-18846, for example.
- The semiconductor device disclosed in JP-A-2016-18846 includes a semiconductor element, a lead frame, a plurality of wires, and a sealing resin. The lead frame is made of copper, for example. The lead frame includes a die pad and a plurality of leads. The die pad supports the semiconductor element. The plurality of leads are electrically connected to the semiconductor element via the plurality of wires. The plurality of leads are terminals for external connection when the semiconductor device is mounted on the circuit board of an electronic device or the like. The sealing resin covers the semiconductor element.
- In conventional semiconductor devices, a lead frame is formed by processing a metal plate (e.g., copper plate). A semiconductor device having such a lead frame has room for improvement in thickness reduction.
- The present disclosure is conceived in view of the above problem, and an object thereof is to provide a thinner semiconductor device and a method for manufacturing the semiconductor device.
- According to an aspect of the present disclosure, there is provided a semiconductor device including: a semiconductor element having an element front surface and an element back surface that face opposite from each other in a thickness direction; an internal electrode electrically connected to the semiconductor element; a sealing resin covering the semiconductor element and a portion of the internal electrode; and an external electrode exposed from the sealing resin and electrically connected to the internal electrode. The internal electrode includes a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface facing the element back surface and a wiring layer back surface facing opposite from the wiring layer front surface in the thickness direction. The columnar portion protrudes in the thickness direction from the wiring layer front surface. The columnar portion has an exposed side surface that faces in a first direction orthogonal to the thickness direction and that is exposed from the sealing resin. The external electrode includes a first cover portion covering the exposed side surface.
- According to another aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device. The method includes: preparing a support substrate; forming an internal electrode including a wiring layer and a columnar portion, where the wiring layer has a wiring layer front surface and a wiring layer back surface that face opposite from each other in a thickness direction, and the wiring layer back surface faces the support substrate, and the columnar portion protrudes from the wiring layer front surface; conductively bonding a semiconductor element to the wiring layer; forming a sealing resin to cover the semiconductor element and the wiring layer front surface; removing the support substrate; forming an exposed side surface of the columnar portion, where the exposed side surface faces in a first direction orthogonal to the thickness direction and is exposed from the sealing resin; and forming an external electrode to cover the exposed side surface.
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FIG. 1 is a plan view showing a semiconductor device according to a first embodiment; -
FIG. 2 is a bottom view showing the semiconductor device according to the first embodiment; -
FIG. 3 is a side view showing the semiconductor device according to the first embodiment; -
FIG. 4 is a sectional view along line IV-IV inFIG. 1 ; -
FIG. 5 is a main-part enlarged sectional view showing a part of the cross section inFIG. 4 ; -
FIG. 6 is a main-part enlarged sectional view showing a part of the cross section inFIG. 4 ; -
FIG. 7 is a sectional view showing a step of a method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 8 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 9 is a plan view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 10 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 11 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 12 is a plan view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 13 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 14 is a plan view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 15 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 16 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 17 is a plan view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 18 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 19 is a plan view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 20 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 21 is a plan view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 22 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 23 is a plan view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 24 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 25 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 26 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 27 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 28 is a bottom view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 29 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 30 is a bottom view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 31 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 32 is a bottom view showing a step of the method for manufacturing the semiconductor device inFIG. 1 ; -
FIG. 33 is a main-part enlarged sectional view showing a semiconductor device according to a variation of the first embodiment; -
FIG. 34 is a sectional view showing a semiconductor device according to a second embodiment; -
FIG. 35 is a sectional view showing a semiconductor device according to a third embodiment; -
FIG. 36 is a sectional view showing a semiconductor device according to a fourth embodiment; -
FIG. 37 is a sectional view showing a step of a method for manufacturing the semiconductor device inFIG. 36 ; -
FIG. 38 is a sectional view showing a step of the method for manufacturing the semiconductor device inFIG. 36 ; -
FIG. 39 is a sectional view showing a semiconductor device according to a variation of the fourth embodiment; -
FIG. 40 is a plan view showing a semiconductor device according to a fifth embodiment; -
FIG. 41 is a sectional view along line F-F inFIG. 40 ; -
FIG. 42 is a sectional view showing a semiconductor device according to a sixth embodiment; -
FIG. 43 is a sectional view showing a step of a method for manufacturing the semiconductor device inFIG. 42 ; -
FIG. 44 is a plan view showing a semiconductor device according to a variation; -
FIG. 45 is a plan view showing a semiconductor device according to a variation; -
FIG. 46 is a plan view showing a semiconductor device according to a variation; -
FIG. 47 is a plan view showing a semiconductor device according to a variation; and -
FIG. 48 is a sectional view along line G-G inFIG. 47 . - Preferred embodiments of a semiconductor device according to the present disclosure and a method for manufacturing the semiconductor device are described below with reference to the drawings.
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FIGS. 1 to 6 show a semiconductor device according to a first embodiment of the present disclosure. A semiconductor device A1 according to the present embodiment includes asemiconductor element 1, aninternal electrode 2,external electrodes 3, an insulatingfilm 41,conductive bonding members 5, and a sealingresin 6. -
FIG. 1 is a plan view showing the semiconductor device A1.FIG. 1 omits the sealingresin 6.FIG. 2 is a bottom view showing the semiconductor device A1.FIG. 3 is a side view showing the semiconductor device A1.FIG. 3 shows a side surface of the semiconductor device A1 as viewed in x direction which is described below.FIG. 4 is a sectional view along line IV-IV inFIG. 1 .FIG. 5 is a main-part enlarged sectional view showing a part of the cross section inFIG. 4 .FIG. 6 is a main-part enlarged sectional view showing a part of the cross section inFIG. 4 . For convenience of explanation, three directions orthogonal to each other are defined as x direction, y direction, and z direction, respectively. The z direction is the thickness direction of the semiconductor device A1. The x direction is the horizontal direction in the plan view of the semiconductor device A1. The y direction is the vertical direction in the plan view of the semiconductor device A1. The x direction and the z direction correspond to the “first direction” and the “thickness direction” in the claims. - The semiconductor device A1 is a resin package mounted on a surface of a circuit board in any of various electronic devices. As shown in
FIGS. 1 and 2 , the semiconductor device A1 has a rectangular shape as viewed in the z direction (hereinafter, also referred to as “plan view”). The semiconductor device A1 in the present embodiment is of a SON package type. - The
semiconductor element 1 is the functional center of the semiconductor device A1. Thesemiconductor element 1 is an integrated circuit (IC) such as a large scale integration circuit (LSI). Alternatively, thesemiconductor element 1 may be a voltage control element such as a low drop out regulator (LDO), an amplifier element such as an operational amplifier, or a discrete semiconductor element such as a diode. Thesemiconductor element 1 is rectangular in plan view. Thesemiconductor element 1 is mounted on theinternal electrode 2. Thesemiconductor element 1 overlaps with the insulatingfilm 41 in plan view. Thesemiconductor element 1 is mounted by flip-chip bonding. - The
semiconductor element 1 has an elementfront surface 11 and an element backsurface 12. The elementfront surface 11 and the element backsurface 12 are spaced apart and face opposite from each other in the z direction. The elementfront surface 11 and the element backsurface 12 are both flat. - The element back
surface 12 is formed withelectrode pads 13 and apassivation film 14. Each of theelectrode pads 13 is rectangular in plan view. As shown inFIG. 6 , theelectrode pads 13 are bonded to the respectiveconductive bonding members 5. Each of theelectrode pads 13 includes a firstconductive portion 131 and a secondconductive portion 132. - The first
conductive portion 131 is made of aluminum (Al), for example. The secondconductive portion 132 is composed of a nickel (Ni) layer, a palladium (Pd) layer, and a gold (Au) layer that are mutually laminated. The Ni layer of the secondconductive portion 132 is in contact with the firstconductive portion 131. Since theelectrode pads 13 include the secondconductive portions 132, the firstconductive portions 131 which are made of Al are prevented from permeating into theconductive bonding members 5. - The
passivation film 14 covers the element backsurface 12 to protect thesemiconductor element 1. Thepassivation film 14 is formed by mutually laminating a Si3N4 layer formed by a plasma CVD method, for example, and a polyimide resin layer formed by coating. Thepassivation film 14 is open in multiple locations (four locations in the present embodiment), and theelectrode pads 13 are exposed from the respective openings. - The
internal electrode 2 is a conductor disposed inside the semiconductor device A1. Theinternal electrode 2 is electrically connected to thesemiconductor element 1. Theinternal electrode 2 includes wiring layers 21 andcolumnar portions 22. - Each of the wiring layers 21 is composed of a
seed layer 210 a and aplating layer 210 b that are mutually laminated. For example, theseed layer 210 a is composed of a first layer that contains titanium (Ti) as a main component, and a second layer that contains copper (Cu) as a main component. Theseed layer 210 a has a thickness of approximately 200 to 800 nm. Theplating layer 210 b contains Cu as a main component. Theplating layer 210 b has a dimension of approximately 20 to 50 μm in the z direction (hereinafter, the dimension being also referred to as “thickness”). Note that theseed layer 210 a and theplating layer 210 b are not limited to those described above in terms of material and thickness. Theseed layer 210 a and theplating layer 210 b correspond to the “second seed layer” and the “second plating layer” in the claims, respectively. Each of the wiring layers 21 includes a wiring-layer front surface 211, a wiring-layer backsurface 212, and anend surface 213. - The wiring-
layer front surface 211 faces the element backsurface 12 of thesemiconductor element 1 in the z direction. Thesemiconductor element 1 is mounted on the wiring-layer front surface 211 via theconductive bonding member 5. The wiring-layer front surface 211 is partially covered with the sealingresin 6. The wiring-layer backsurface 212 faces opposite from the wiring-layer front surface 211 in the z direction. The wiring-layer backsurface 212 has anelectrode cover region 212 a and an insulating-film cover region 212 b. Theelectrode cover region 212 a is a region of the wiring-layer backsurface 212, and is covered with theexternal electrode 3. The insulating-film cover region 212 b is a region of the wiring-layer backsurface 212, and is covered with the insulatingfilm 41. Theelectrode cover region 212 a is a region of the wiring-layer backsurface 212 other than the insulating-film cover region 212. Furthermore, theelectrode cover region 212 a is located more outward in the z direction than the insulating-film cover region 212 b. Accordingly, the wiring-layer backsurface 212 has a step. - The
end surface 213 intersects with the wiring-layer backsurface 212 and faces outward in the x direction. In the illustrated example, theend surface 213 also intersects with the wiring-layer front surface 211. Theend surface 213 is covered with theexternal electrode 3. Accordingly, theend surface 213 is not visible from outside the semiconductor device A1. - The
columnar portions 22 protrude from the wiring layers 21 (wiring-layer front surfaces 211) in the z direction. Theinternal electrode 2 has fourcolumnar portions 22. Each of thecolumnar portions 22 has a rectangular columnar shape having a rectangular cross section along the x-y plane. Note that each of thecolumnar portions 22 may have another shape such as a cylindrical shape or a polygonal columnar shape. Thecolumnar portions 22 are larger in dimension than the wiring layers 21 in z direction. Each of thecolumnar portions 22 is composed of aseed layer 220 a and aplating layer 220 b that are mutually laminated. For example, theseed layer 220 a is composed of a first layer that contains Ti as a main component, and a second layer that contains Cu as a main component. This means that theseed layer 210 a and theseed layer 220 a are made of the same material. Theseed layer 220 a has a thickness of approximately 200 to 800 nm. Theplating layer 220 b contains Cu as a main component. Accordingly, theplating layer 210 b and theplating layer 220 b are made of the same material. Theplating layer 220 b has a thickness of approximately 50 to 100 μm. Note that theseed layer 220 a and theplating layer 220 b are not limited to those described above in terms of material and thickness. Theseed layer 220 a and theplating layer 220 b correspond to the “first seed layer” and the “first plating layer” in the claims, respectively. - As shown in
FIG. 4 , each of thecolumnar portions 22 has abase end surface 221, atop surface 222, an exposedside surface 223, and a resinabutment side surface 224. Thebase end surface 221 is in contact with thewiring layer 21. Thebase end surface 221 is flat. Thetop surface 222 faces opposite from thebase end surface 221 in the z direction. Thetop surface 222 is flat. Thetop surface 222 is covered with the sealingresin 6. Thetop surface 222 overlaps with thesemiconductor element 1 as viewed in the x direction. In other words, thetop surface 222 is arranged between the elementfront surface 11 and the element backsurface 12 in the z direction. The exposedside surface 223 and resinabutment side surface 224 of eachcolumnar portion 22 face in either one of the x direction and the y direction that are orthogonal to the z direction. In the present embodiment, the exposedside surface 223 faces outward in the x direction. The exposedside surface 223 is exposed from the sealingresin 6. The exposedside surface 223 is flush with theend surface 213. The resinabutment side surface 224 abuts on and is covered with the sealingresin 6. - The
internal electrode 2 has a dimension d1 in the z direction as shown inFIG. 5 , and the dimension d1 may be set to 100 μm or greater. Alternatively, the dimension d1 in the z direction maybe approximately 100 to 150 μm. Regarding theinternal electrode 2, surfaces that abut on the sealing resin 6 (i.e., the wiring-layer front surfaces 211, thetop surfaces 222, and the resin abutment side surfaces 224) are roughened to have a roughness of 2 to 3 μm through a roughening process in the manufacturing method described below. In the present embodiment, the surfaces that abut on the sealingresin 6 are rougher than the wiring-layer back surfaces 212, but smoother than the exposed side surfaces 223. In other words, the exposedside surfaces 223 are rougher than the surfaces that abut on the sealingresin 6. - The
external electrodes 3 are conductors electrically connected to theinternal electrode 2, and are exposed to the outside of the semiconductor device A1. Theexternal electrodes 3 are terminals used when the semiconductor device A1 is mounted on a circuit board. Theexternal electrodes 3 are formed by electroless plating. Each of theexternal electrodes 3 is composed of a Ni layer, a Pd layer, and a Au layer that are mutually laminated. The Ni layer is in contact with theinternal electrode 2, and has a thickness of approximately 5 μm. The Au layer is exposed to the outside, and has a thickness of approximately 0.01 to 0.02 μm. The pd layer is interposed between the Ni layer and the Au layer, and has a thickness of approximately 0.01 to 0.02 μm. Note that theexternal electrodes 3 are not limited in terms of quantity, thickness, material, and forming method. - As shown in
FIGS. 3 and 4 , each of theexternal electrodes 3 includes afirst cover portion 31, asecond cover portion 32, and athird cover portion 33. Thefirst cover portion 31 covers the exposedside surface 223 of thecolumnar portion 22. Thesecond covering portion 32 covers theend surface 213 of thewiring layer 21. Thethird cover portion 33 covers a portion (electrode cover region 212 a) of the wiring-layer backsurface 212 of thewiring layer 21. In the present embodiment, twoexternal electrodes 3 are seen on each of the two side surfaces of the semiconductor device A1 that face in the x direction, and fourexternal electrodes 3 are seen from the bottom surface of the semiconductor device A1. Thefirst cover portion 31, thesecond cover portion 32, and thethird cover portion 33 are formed integrally. Theexternal electrodes 3 are insulated from each other by the insulatingfilm 41. - The insulating
film 41 is made of an insulating material, such as a polyimide resin or a phenol resin. The insulatingfilm 41 is provided at the bottom surface of the semiconductor device A1. The insulatingfilm 41 is arranged lower than the sealingresin 6 in the z direction. As shown inFIG. 1 , the insulatingfilm 41 is rectangular in plan view. Note that the insulatingfilm 41 may have a shape other than a rectangle in plan view. The insulatingfilm 41 corresponds to the “first insulating film” in the claims. The insulatingfilm 41 has an insulating filmfront surface 411 and an insulating film backsurface 412 that face opposite from each other in the z direction. - The insulating film
front surface 411 faces in the same direction as the elementfront surface 11 of thesemiconductor element 1, and faces the element backsurface 12 of thesemiconductor element 1. The insulating film backsurface 412 faces in the same direction as the element backsurface 12. The insulating filmfront surface 411 is in contact with portions (insulating-film cover regions 212 b) of the wiring-layer back surfaces 212 of the wiring layers 21. The insulating film backsurface 412 is flush with portions (electrode cover regions 212 a) of the wiring-layer back surfaces 212 of the wiring layers 21. - As shown in
FIGS. 4 and 6 , theconductive bonding members 5 are conductive members interposed between the wiring layers 21 of theinternal electrode 2 and theelectrode pads 13 of thesemiconductor element 1. Each of theconductive bonding members 5 is made of a Ni layer in contact with thewiring layer 21, and a solder layer in contact with the Ni layer. The solder layer is made of an alloy containing tin (Sn). Examples of such an alloy include lead-free solder such as a Sn—Sb-based alloy or a Sn—Ag-based alloy, and solder containing lead (Pb). Thesemiconductor element 1 is fixed to the wiring layers 21 (internal electrode 2) by theconductive bonding members 5. - The sealing
resin 6 may be a synthetic resin containing black epoxy resin as a main component. As shown inFIG. 4 , the sealingresin 6 covers thesemiconductor element 1, a portion of theinternal electrode 2, and theconductive bonding members 5. The sealingresin 6 has aresin front surface 61, a resin backsurface 62, and a plurality of resin side surfaces 63. - The
resin front surface 61 faces in the same direction as the elementfront surface 11. As shown inFIG. 3 , the resin backsurface 62 faces in the same direction as the element backsurface 12. The resin backsurface 62 is in contact with theinternal electrode 2 and the insulatingfilm 41. The resin side surfaces 63 are orthogonal to theresin front surface 61 and the resin backsurface 62. The sealingresin 6 has two resin side surfaces 63 facing opposite from each other in the x direction, and another two resin side surfaces 63 facing opposite from each other in the y direction. In the present embodiment, twoexternal electrodes 3 are exposed from each of the two resin side surfaces 63 facing in the x direction, as shown inFIG. 3 . In plan view, theexternal electrodes 3 are located more outward of the semiconductor device A1 than the two resin side surfaces 63 facing in the x direction. - Next, an example of a method for manufacturing the semiconductor device A1 will be described with reference to
FIGS. 7 to 32 . AmongFIGS. 7 to 32 ,FIGS. 9, 12, 14, 17, 19, 21 , and 23 are plan views showing steps of the method for manufacturing the semiconductor device A1, andFIGS. 28, 30 , and 32 are bottom views showing steps of the method for manufacturing the semiconductor device A1. The rest of the figures are sectional views showing steps of the method for manufacturing the semiconductor device A1. The cross-sections shown in these figures correspond to the cross-section shown inFIG. 4 . For convenience, the cross-sections inFIGS. 25-27 ,FIG. 29 , andFIG. 31 are shown upside down in the z direction with respect to the other sectional views. - First, as shown in
FIG. 7 , asupport substrate 800 is prepared (support substrate preparation step). Thesupport substrate 800 has afront surface 800 a and aback surface 800 b facing in the z direction. Thesupport substrate 800 may be a glass substrate or a silicon (Si) substrate. In the present embodiment, thesupport substrate 800 is a glass substrate having a light-transmissive property. Thesupport substrate 800 has a thickness of approximately 0.5 μm. Next, as shown inFIG. 7 , atemporary fixing member 801 is formed on the support substrate 800 (temporary fixing member forming step). In this step, thetemporary fixing member 801 is formed to cover the entirety of thefront surface 800 a. Then, as shown inFIG. 7 , asputter film 802 is formed on the temporary fixing member 801 (sputter film formation step). In this step, thesputter film 802 is formed to cover the entirety of thetemporary fixing member 801. Thesputter film 802 is a metal film containing Ti as a main component. - Next, insulating
films 841 are formed, as shown inFIGS. 8 and 9 (insulating film formation step). One of the insulatingfilms 841 correspond to the insulatingfilm 41 of the semiconductor device A1. Each of the insulatingfilms 841 is made of a photosensitive resin material such as a polyimide resin or a phenol resin. In the insulating film formation step, the insulatingfilms 841 are formed on thesputter film 802 with use of a spin coater (rotary coating device), for example, as shown inFIG. 8 . Alternatively, a film-like photosensitive resin material may be attached. Then, patterning may be performed by exposing and developing the photosensitive resin material. As a result, the insulatingfilms 841 are formed as shown inFIGS. 8 and 9 . With the insulatingfilms 841 so formed, thesputter film 802 has portions covered with the insulatingfilms 841 and portions exposed from the insulatingfilms 841. The portions where thesputter film 802 is exposed from the insulatingfilms 841 will ultimately become portions corresponding to theelectrode cover regions 212 a of the wiring layers 21 in the semiconductor device A1. - Next, a
seed layer 820 a is formed as shown inFIG. 10 (preceding seed layer formation step). Portions of theseed layer 820 a will ultimately correspond to portions of the internal electrode 2 (specifically, the seed layers 210 a of the wiring layers 21) in the semiconductor device A1. Theseed layer 820 a is formed by sputtering. Theseed layer 820 a is formed across all surfaces on thefront surface 800 a side of thesupport substrate 800. Theseed layer 820 a is composed of a Ti layer and a Cu layer that are mutually laminated. In the preceding seed layer formation step, the Ti layer is first formed to be in contact with the insulatingfilms 841 and thesputter film 802, and the Cu layer is then formed on the Ti layer. - Next, as shown in
FIGS. 11 and 12 , platinglayers 820 b are formed (preceding plating layer formation step). The plating layers 820 b correspond to portions of the internal electrode 2 (specifically, the plating layers 210 b of the wiring layers 21) of the semiconductor device A1. The plating layers 820 b are formed by pattern formation through photolithography and electrolytic plating. In the preceding plating layer formation step, a resist layer (not shown) for forming the plating layers 820 b is first formed through photolithography. In forming the resist layer, a photosensitive resist is applied to cover the entire surface of theseed layer 820 a, and the photosensitive resist is patterned by exposure and development. The patterning exposes portions of theseed layer 820 a (portions for forming the plating layers 820 b). Then, the plating layers 820 b are formed on the exposed portions of theseed layer 820 a through electrolytic plating using theseed layer 820 a as a conductive path. Subsequently, the resist layer is removed to thereby form the plating layers 820 b as shown inFIGS. 11 and 12 . - Next, as shown in
FIGS. 13 and 14 , unnecessary portions of theseed layer 820 a that are not covered with the plating layers 820 b are all removed (preceding seed layer removal step). The unnecessary portions of theseed layer 820 a are removed by wet etching. The wet etching is performed with use of a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). As a result of the preceding seed layer removal step, the insulatingfilms 841 are exposed from where portions of theseed layer 820 a are removed, as shown inFIGS. 13 and 14 . Also, as a result of the removal of the unnecessary portions of theseed layer 820 a, wiring layers 821, which are composed ofseed layers 820 a and the plating layers 820 b, are formed. The wiring layers 821 correspond to the wiring layers 21 of theinternal electrode 2 of the semiconductor device A1. Accordingly, the wiring layers 821 are formed through a wiring layer formation step that includes the preceding seed layer formation step, the preceding plating layer formation step, and the preceding seed layer removal step. - Next, a
seed layer 820 c is formed as shown inFIG. 15 (succeeding seed layer formation step). Portions of theseed layer 820 c will ultimately correspond to portions of the internal electrode 2 (specifically, the seed layers 220 a of the columnar portions 22) in the semiconductor device A1. Theseed layer 820 c is formed by sputtering. Theseed layer 820 c is formed across all surfaces on thefront surface 800 a side of thesupport substrate 800. Theseed layer 820 c is composed of a Ti layer and a Cu layer that are mutually laminated. In the succeeding seed layer formation step, the Ti layer is formed to be in contact with either the insulatingfilms 841 or the plating layers 820 b, and the Cu layer is then formed to be in contact with the Ti layer. - Next, as shown in
FIGS. 16 and 17 , platinglayers 820 d are formed (succeeding plating layer formation step). The plating layers 820 d correspond to portions of the internal electrode 2 (specifically, the plating layers 220 b of the columnar portions 22) of the semiconductor device A1. The plating layers 820 d are formed by pattern formation through photolithography and electrolytic plating. In the succeeding plating layer formation step, a resist layer (not shown) for forming the plating layers 820 d is first formed through photolithography. In forming the resist layer, a photosensitive resist is applied to cover the entire surface of theseed layer 820 c, and the photosensitive resist is patterned by exposure and development. The patterning exposes portions of theseed layer 820 c (portions for forming the plating layers 820 d). Then, the plating layers 820 d are formed on the exposed portions of theseed layer 820 c through electrolytic plating using theseed layer 820 c as a conductive path. Subsequently, the resist layer is removed to thereby form the plating layers 820 d as shown inFIGS. 16 and 17 . - Next, as shown in
FIGS. 18 and 19 ,conductive bonding members 85 are formed (conductive bonding members formation step). Theconductive bonding members 85 correspond to theconductive bonding members 5 of the semiconductor device A1. Theconductive bonding members 85 are formed by pattern formation through photolithography and electrolytic plating. In the conductive bonding members formation step, a resist layer (not shown) for forming theconductive bonding members 85 is first formed on theseed layer 820 c, and the resist layer is patterned. The patterning exposes portions of theseed layer 820 c (portions for forming the conductive bonding members 85). Then, theconductive bonding members 85 are formed on the exposed portions through electrolytic plating using theseed layer 820 c as a conductive path. In the formation, first conductive layers are formed to be in contact with theseed layer 820 c, and second conductive layers are then formed to be in contact with the first conductive layers. In the present embodiment, each of the first conductive layers contains Ni as a main component, and each of the second conductive layers contains lead-free solder such as a Sn—Ag-based alloy or a Sn—Sb-based alloy. Subsequently, the resist layer is removed. - Next, as shown in
FIGS. 20 and 21 , unnecessary portions of theseed layer 820 c that are not covered with either the plating layers 820 d or theconductive bonding members 85 are all removed (succeeding seed layer removal step). The removal of the unnecessary portions of theseed layer 820 c is performed in the same manner as the preceding seed layer removal step. That is, the removal is performed by wet etching using a mixed solution of sulfuric acid (H2SO4) and hydrogen peroxide (H2O2). As a result of the succeeding seed layer removal step, the wiring layers 821 and the insulatingfilms 841 are exposed from where portions of theseed layer 820 c are removed, as shown inFIGS. 20 and 21 . Also, as a result of the removal of the unnecessary portions of theseed layer 820 c,columnar portions 822 that are composed ofseed layers 820 c and the plating layers 820 d, are formed. Thecolumnar portions 822 correspond to thecolumnar portions 22 of theinternal electrode 2 in the semiconductor device A1. Accordingly, thecolumnar portions 822 are formed through a columnar portion formation step that includes the succeeding seed layer formation step, the succeeding plating layer formation step, and the succeeding seed layer removal step. Since the wiring layers 821 and thecolumnar portions 822 are included in aninternal electrode 82, a step of forming the internal electrode 82 (internal electrode formation step) includes the wiring layer formation step and the columnar portion formation step. - Next, a roughening process is performed. A chemical solution used for the roughening process is not particularly limited as long as the solution reacts with the material (Cu) of the internal electrode 82 (the wiring layers 821 and the columnar portions 822). As a result of the roughening process, the surfaces of the wiring layers 821 and the
columnar portions 822 are roughened. The roughness of the surfaces is approximately 2 to 3 μm, for example. - Next, as shown in
FIGS. 22 and 23 ,semiconductor elements 81 are mounted (semiconductor element mounting step). Note that inFIG. 22 and the subsequent figures, the seed layers 820 a and the plating layers 820 b are collectively shown as the wiring layers 821 with no distinction therebetween. Similarly, the seed layers 820 c and the plating layers 820 d are collectively shown as thecolumnar portions 822 with no distinction therebetween. One of thesemiconductor elements 81 corresponds to thesemiconductor element 1 in the semiconductor device A1. The semiconductor element mounting step is performed through flip chip bonding (FCB). First, flux is applied to electrode pads (not shown) of thesemiconductor elements 81. Then, with thesemiconductor elements 81 positioned opposite from the wiring layers 821, thesemiconductor elements 81 are temporarily attached to theconductive bonding members 85 via a flip chip bonder. At this point, theconductive bonding members 85 are sandwiched between the wiring layers 821 and thesemiconductor elements 81. Next, theconductive bonding members 85 are melted by reflow. Then, theconductive bonding members 85 are cooled and solidified, after which mounting of thesemiconductor elements 81 is completed. - Next, a sealing
resin 86 is formed to cover the semiconductor elements 81 (sealing resin formation step), as shown inFIG. 24 . The sealingresin 86 corresponds to the sealingresin 6 of the semiconductor device A1. The sealingresin 86 is a synthetic resin having an electrically insulating property, such as a synthetic resin containing a black epoxy resin as a main component. In the sealing resin formation step, the sealingresin 86 is formed over thesupport substrate 800 such that thesemiconductor elements 81 are completely covered without exposure. The sealingresin 86 formed in this step has aresin front surface 861. As shown inFIG. 24 , the wiring layers 821 and thecolumnar portions 822 are also covered with the sealingresin 86. After the sealing resin formation step, the sealingresin 86 may be ground from theresin front surface 861 to reduce the thickness of the sealingresin 86. During this process, the sealingresin 86 may be ground until the upper surfaces of thesemiconductor elements 81 are exposed from the sealingresin 86. - Next, as shown in
FIGS. 25 and 26 , thesupport substrate 800 is peeled off (support substrate peeling step). In the support substrate peeling step, a dicingtape 804 is attached to theresin front surface 861, as shown inFIG. 25 . Then, laser irradiation is performed from theback surface 800 b of thesupport substrate 800, for example. In this way, the laser beam passes through thesupport substrate 800 to irradiate thetemporary fixing member 801. This weakens the adhesive strength of thetemporary fixing member 801, allowing thesupport substrate 800 to be peeled off. If thetemporary fixing member 801 partially remains (e.g., as soot) after thesupport substrate 800 is peeled off, the remaining bits of thetemporary fixing member 801 may be removed by plasma. As a result of the above process, thesupport substrate 800 and thetemporary fixing member 801 are removed as shown inFIG. 26 . Note that the support substrate peeling step may be performed through a method other than laser irradiation. For example, an element such as thesupport substrate 800 may be peeled off by blowing air in the x direction (horizontal direction inFIG. 25 ). Alternatively, an element such as thesupport substrate 800 can be peeled off by heating and softening thetemporary fixing member 801. When the peeling is performed by laser irradiation, it is necessary that thesupport substrate 800 be made of a material having an appropriate light-transmissive property, so that the laser beam can pass through thesupport substrate 800. When the peeling is performed by blowing air or heating, thesupport substrate 800 maybe a Si substrate instead of a glass substrate. - Next, the
sputter film 802 is removed (sputter film removal step), as shown inFIGS. 27 and 28 . As a result of the sputter film removal step, insulating film back surfaces 841 b of the insulatingfilms 841 and wiring layer back surfaces 821 b of the wiring layers 821 are exposed. - Next, as shown in
FIGS. 29 and 30 , the sealingresin 86 is cut along the x and y directions so as to be divided into a plurality of pieces that respectively include thesemiconductor elements 81. The step of cutting the sealing resin 86 (cutting step) is performed by blade dicing. In the present embodiment, the cutting is performed along the cut line CL shown inFIGS. 27 and 28 to obtain the plurality of pieces respectively including thesemiconductor elements 81. Regarding the cut line CL shown inFIGS. 27 and 28 , the width in the lateral direction is the thickness of the dicing blade. In the cutting step described above, the dicingtape 804 is not completely cut in the z direction (although it is cut slightly), as shown inFIG. 27 . In this way, after the sealingresin 86 is cut into pieces respectively including thesemiconductor elements 81, these pieces are connected via the dicingtape 804 and thus do not fall apart. As a result of the cutting step, resin side surfaces 863 of the sealingresin 86, end surfaces 821 c of the wiring layers 821, and exposedside surfaces 822 c of thecolumnar portions 822 are formed, as shown inFIG. 29 . These surface are exposed to the outside. - Next, as shown in
FIGS. 31 and 32 ,external electrodes 83 are formed (external electrode formation step). Theexternal electrodes 83 correspond to theexternal electrodes 3 of the semiconductor device A1. The external electrode formation step is performed through electroless plating. In the present embodiment, a Ni layer, a Pd layer, and a Au layer are deposited in the stated order by electroless plating. In this deposition process, the Ni layer is formed to be in contact with and cover the surfaces of the wiring layers 821 and the surfaces of thecolumnar portions 822 that are respectively exposed from the insulatingfilms 841 and the sealingresin 86. Next, the Pd layer is formed on the Ni layer, and then the Au layer is formed on the Pd layer. Note that theexternal electrodes 83 are not deposited on the insulatingfilms 841. As a result, theexternal electrodes 83 are formed as shown inFIGS. 31 and 32 . - Next, the dicing
tape 804 is peeled off. The semiconductor device A1 as shown inFIGS. 1 to 6 is manufactured through the above-described steps. - The following describes the advantages of the semiconductor device A1 and the method for manufacturing the semiconductor device A1 according to the first embodiment.
- According to the present embodiment, the semiconductor device A1 includes the
internal electrode 2 formed by electrolytic plating, and theexternal electrodes 3 formed by electroless plating. As can be understood, the semiconductor device A1 uses wires formed by plating, and do not use any lead frame formed with a metal plate. The wires formed by plating can be reduced in thickness as compared to the lead frame structure. This allows for thinning of the semiconductor device A1. Furthermore, along with high integration of ICs and LSIs, the number of terminals has increased, and this necessitates miniaturization of internal electrodes and the like. In such a case, using a lead frame limits miniaturization because such a frame is created by processing a metal plate. In the case of the semiconductor device A1, however, theinternal electrode 2 is formed by plating to allow miniaturization. This makes it possible to manufacture a semiconductor device having a larger number of terminals. - According to the present embodiment, the
internal electrode 2 includes the wiring layers 21 that each have theend surface 213 exposed from theresin side surface 63, and thecolumnar portion 22 that each have the exposedside surface 223 exposed from theresin side surface 63. Theexternal electrodes 3 each include thefirst cover portion 31 that covers the exposedside surface 223, and thesecond cover portion 32 that covers theend surface 213. With such a structure, portions of theexternal electrodes 3 formed on the side surfaces (side surfaces facing in the x direction in the present embodiment) of the semiconductor device A1 can have a larger dimension in the z direction than in the case where thecolumnar portions 22 are not provided. The semiconductor device A1 is mounted on a circuit board or the like by using solder. If theinternal electrode 2 has nocolumnar portions 22 and is made up of only the wiring layers 21, portions of theexternal electrodes 3 formed on the side surfaces of the semiconductor device A1 will simply be thesecond cover portions 32. In this case, the dimension of thesecond cover portions 32 alone in the z direction is not large enough to easily form soldering fillets when the semiconductor device A1 is mounted on a circuit board. However, the present embodiment makes it possible to increase the dimension of theexternal electrodes 3 in the z direction which are formed on the side surfaces of the semiconductor device A1. In this way, solder fillets can be formed when the semiconductor device A1 is mounted on a circuit board or the like. As a result, the mounting strength of the semiconductor device A1 with respect to the circuit board can be enhanced. Furthermore, the connection state of solder can be visually checked from the side surfaces of the semiconductor device A1. - According to the present embodiment, a roughening process is performed during the manufacturing process of the semiconductor device A1. The roughening process causes the wiring-layer front surfaces 211, the
top surfaces 222, and the resin abutment side surfaces 224 to be roughened. This structure can enhance the adhesion between theinternal electrode 2 and the sealingresin 6. - In the first embodiment, the angle formed between each pair of the wiring-layer back surfaces 212 and the end surfaces 213 is approximately orthogonal. In this case, during the cutting step, a protrusion may be formed at a junction between any pair of the wiring-layer back surfaces 212 and the end surfaces 213.
FIG. 33 shows a main-part enlarged sectional view when such a protrusion is created.FIG. 33 corresponds to the main-part enlarged sectional view inFIG. 5 . InFIG. 33 , aprotrusion 214 protrudes from the wiring-layer backsurface 212 of thewiring layer 21 in the z direction. In this case, theexternal electrode 3 is formed to cover theprotrusion 214. Theprotrusion 214 may have a shape other than the one shown inFIG. 33 . For example, theprotrusion 214 may protrude in a direction other than the z direction, such as the x direction or the y direction. - In the first embodiment, only the
external electrodes 3 are exposed from the insulatingfilm 41 when the semiconductor device A1 is viewed from the bottom surface (seeFIG. 2 ). However, other elements, such as a portion of the resin backsurface 62, may be exposed from the insulatingfilm 41. - The following describes other embodiments relating to the semiconductor device of the present disclosure and the method for manufacturing the semiconductor device. Note that in the following embodiments, elements that are the same as or similar to the elements in the first embodiment are provided with the same reference signs, and the descriptions thereof are omitted.
-
FIG. 34 shows a semiconductor device according to a second embodiment. A semiconductor device A2 according to the present embodiment differs from the semiconductor device A1 (first embodiment) in further including ametal layer 7. -
FIG. 34 is a sectional view showing the semiconductor device A2. The cross-section shown inFIG. 34 corresponds to the cross-section shown inFIG. 4 for the first embodiment. - In the present embodiment the insulating
film 41 has anopening 413. Theopening 413 continues from the insulating filmfront surface 411 to the insulating film backsurface 412 in the z direction. Theopening 413 is rectangular in plan view, but may have any other shape in other embodiments. Theopening 413 is formed by patterning in the insulating film formation step described above. - In the present embodiment, the
internal electrode 2 further includes afiller portion 23. Thefiller portion 23 is a portion of theinternal electrode 2 that fills theopening 413 of the insulatingfilm 41. Thefiller portion 23 is formed in the wiring layer formation step described above. - The
metal layer 7 is made of a conductive metal material. In the present embodiment, themetal layer 7 is formed by electroless plating as in theexternal electrodes 3. Accordingly, themetal layer 7 is composed of a Ni layer, a Pd layer, and a Au layer that are mutually laminated. Note that the material and forming method of themetal layer 7 are not limited to those described above. Themetal layer 7 is in contact with thefiller portion 23 and exposed to the outside of the semiconductor device A2. - The semiconductor device A2 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A2 can be made thinner.
- According to the present embodiment, the semiconductor device A2 includes the
metal layer 7. When the semiconductor device A2 is energized, thesemiconductor element 1 generates heat. The heat generated from thesemiconductor element 1 is transferred to themetal layer 7 and released to the outside. Accordingly, themetal layer 7 functions as a heat dissipator in the semiconductor device A2. Such a structure can improve the heat dissipation of the semiconductor device A2. Themetal layer 7 is made of metal and has conductivity. Accordingly, themetal layer 7 can also be used as a terminal for external connection. - According to the present embodiment, the
metal layer 7 is formed by electroless plating as in theexternal electrodes 3. Accordingly, theexternal electrodes 3 and themetal layer 7 can be formed at the same time. -
FIG. 35 shows a semiconductor device according to a third embodiment. A semiconductor device A3 according to the present embodiment differs from the semiconductor device A1 (first embodiment) in further including an insulatingfilm 42. -
FIG. 35 is a sectional view showing the semiconductor device A3. The cross-section shown inFIG. 35 corresponds to the cross-section shown inFIG. 4 for the first embodiment. - The insulating
film 42 is made of an insulating material, such as a polyimide resin. The insulatingfilm 42 is sandwiched between theinternal electrode 2 and the sealingresin 6. The insulatingfilm 42 may be formed by photolithography. The insulatingfilm 42 is formed after the roughening process and before the semiconductor element mounting step. This means that the insulatingfilm 42 is formed after the conductive bonding members 5 (85) are formed. Accordingly, the insulatingfilm 42 has through-holes 421 filled with theconductive bonding members 5. The insulatingfilm 42 corresponds to the “second insulating film” in the claims. - The semiconductor device A3 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A3 can be made thinner.
- In the present embodiment, the insulating
film 42 has the through-holes 421, and portions of theconductive bonding members 5 fill the through-holes 421. Theconductive bonding members 85 are softened by ref low in the semiconductor element mounting step. In this process, the softenedconductive bonding members 85 may spread along the wiring-layer front surfaces 211. However, in the present embodiment, the wiring-layer front surfaces 211 are covered with the insulatingfilm 42. This prevents the conductive bonding members 5 (85) from spreading along the wiring-layer front surfaces 211. -
FIG. 36 shows a semiconductor device according to a fourth embodiment. A semiconductor device A4 according to the present embodiment differs from the semiconductor device A1 (first embodiment) in that the resin side surfaces 63 of the sealingresin 6 have dents. -
FIG. 36 is a sectional view showing the semiconductor device A4. The cross-section shown inFIG. 36 corresponds to the cross-section shown inFIG. 4 for the first embodiment. - In the present embodiment, each of the resin side surfaces 63 includes a resin side surface
first portion 631 and a resin side surfacesecond portion 632, as shown inFIG. 36 . The resin side surfacefirst portion 631 and the resin side surfacesecond portion 632 are both flat. The resin side surfacefirst portion 631 is arranged more outward than the resin side surfacesecond portion 632 in plan view. The resin side surfacesecond portion 632 is flush with the exposedside surface 223 of thecolumnar portion 22 and theend surface 213 of thewiring layer 21. - The following describes an example of a method for manufacturing the semiconductor device A4, with reference to
FIGS. 37 and 38 . Note that descriptions of steps that are the same as those in the manufacturing method of the semiconductor device A1 according to the first embodiment are omitted.FIGS. 37 and 38 are sectional views showing steps of manufacturing the semiconductor device A4. - In the method for manufacturing the semiconductor device A4, steps from the support substrate preparation step (see
FIG. 7 ) through the sputter film removal step (seeFIGS. 27 and 28 ) are performed in the same manner as in the first embodiment. Note that in the present embodiment, it is not necessary to attach the dicingtape 804 in the support substrate peeling step. Subsequently,grooves 89 are formed as shown inFIG. 37 . The step of forming thegrooves 89 may be performed through half-cut dicing using a dicing blade. In the half-cut dicing, the sealingresin 86 is not completely cut in the z direction so as to form thegrooves 89. The depth of thegrooves 89 is determined by the cut amount during the half-cut dicing, and the width of thegrooves 89 is determined by the thickness of the dicing blade. As shown inFIG. 37 , the end surfaces 821 c of the wiring layers 821 and the exposedside surfaces 822 c of thecolumnar portions 822, which are exposed from the sealingresin 86, are formed by half-cut dicing. - Next, as shown in
FIG. 38 , theexternal electrodes 83 are formed. The external electrode formation step is performed through electroless plating in the same manner as in the first embodiment. As a result, theexternal electrodes 83 are formed to cover the respective surfaces of the wiring layers 821 and thecolumnar portions 822 that are exposed from the sealingresin 86. Thereafter, the sealingresin 86 is cut along the cut line CL2 shown inFIG. 38 so as to be divided into a plurality of pieces that respectively include thesemiconductor elements 81. The dicing blade used when cutting along the cut line CL2 is thinner than the dicing blade used during the half -cut dicing described above. The semiconductor device A4 as shown inFIG. 36 is manufactured through the above-described steps. That is, the semiconductor device A4 is manufactured to include the resin side surfaces 63 of the sealingresin 6 that have dents. - The semiconductor device A4 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A4 can be made thinner.
- According to the present embodiment, the dicing
tape 804 is not attached in the support substrate peeling step. In the cutting step according to the first embodiment, the sealingresin 86 is completely cut along the z direction. Accordingly, it is necessary to use the dicingtape 804 to hold the individual pieces together for the external electrode formation step (electroless plating). In the present embodiment, on the other hand, the pieces of the sealingresin 86 are continuous and do not fall apart even without the dicingtape 804 during the external electrode formation step. Accordingly, the dicingtape 804 is not necessary in the method for manufacturing the semiconductor device A4. - In the fourth embodiment, the resin side surfaces 63 have dents. Alternatively, the exposed
side surfaces 223 of thecolumnar portions 22 may have dents.FIG. 39 shows the case where the exposedside surfaces 223 have dents.FIG. 39 is a sectional view showing a semiconductor device according to such a variation as described above, and corresponds toFIG. 36 . - In the variation, each of the exposed side surfaces 223 includes an exposed side surface
first portion 223 a and an exposed side surfacesecond portion 223 b. The exposed side surfacefirst portion 223 a and the exposed side surfacesecond portion 223 b are both flat. The exposed side surfacefirst portion 223 a is arranged more outward than the exposed side surfacesecond portion 223 b in plan view. The exposed side surfacefirst portion 223 a is flush with theresin side surface 63. The exposed side surfacesecond portion 223 b is flush with theend surface 213 of thewiring layer 21. As shown inFIG. 39 , the exposed side surfacefirst portion 223 a is not covered with theexternal electrode 3, whereas the exposed side surfacesecond portion 223 b is covered with theexternal electrode 3. - According to the present variation, the exposed
side surface 223 is created by forming a shallower groove 89 (seeFIG. 37 ) during the half-cut dicing. In other words, the amount of cut during the half-cut dicing is reduced so as not to completely cut thecolumnar portion 822 in the z direction. In this way, after the sealing resin 6 (86) is cut into pieces respectively including the semiconductor elements 1 (81), the exposedside surfaces 223 that each include the exposed side surfacefirst portion 223 a and the exposed side surfacesecond portion 223 b are formed. -
FIGS. 40 and 41 show a semiconductor device according to a fifth embodiment. A semiconductor device A5 according to the present embodiment differs from the semiconductor device A1 (first embodiment) in that thecolumnar portions 22 includeprotrusions 225. -
FIG. 40 is a plan view showing the semiconductor device A5.FIG. 40 omits the sealingresin 6.FIG. 41 is a sectional view along line F-F inFIG. 40 . - As shown in
FIG. 40 , thecolumnar portions 22 include theprotrusions 225. Theprotrusions 225 protrude from the respective resin abutment side surfaces 224 facing in the y direction in plan view. As shown inFIG. 40 , twoprotrusions 225 protrude from two respective resin abutment side surfaces 224 facing in the y direction. Each of theprotrusions 225 has anengagement surface 225 a. - The
engagement surface 225 a protrudes from the resinabutment side surface 224. Theengagement surface 225 a and the resinabutment side surface 224 form a right angle. In other words, theengagement surface 225 a is orthogonal to the resinabutment side surface 224. Note that theengagement surface 225 a maybe inclined to the resinabutment side surface 224. Theengagement surface 225 a faces outward in the x direction in plan view. Accordingly, theengagement surface 225 a is parallel to a y-z plane. Theengagement surface 225 a is in contact with the sealingresin 6. In the x direction, the sealingresin 6 is interposed between theengagement surface 225 a and theresin side surface 63. - The semiconductor device A5 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A5 can be made thinner.
- According to the present embodiment, the
columnar portions 22 include theprotrusions 225. Theprotrusions 225 have the engagement surfaces 225 a. Each of the engagement surfaces 225 a protrudes from the resinabutment side surface 224 and is in contact with the sealingresin 6. With such a structure, even if a stress is applied to theinternal electrode 2 outward in the x direction, theengagement surface 225 a is caught by the sealingresin 6. Accordingly, the semiconductor device A5 prevents theinternal electrode 2 from slipping out in the x direction. -
FIG. 42 shows a semiconductor device according to a sixth embodiment. A semiconductor device A6 according to the present embodiment differs from the semiconductor device A1 (first embodiment) in that thecolumnar portions 22 includeprotrusions 226. -
FIG. 42 is a sectional view showing a semiconductor device A6. The cross-section shown inFIG. 42 corresponds to the cross-section shown inFIG. 4 for the first embodiment. - In the present embodiment, the
top surfaces 222 of thecolumnar portions 22 are curved as shown inFIG. 42 . Thecolumnar portions 22 includeprotrusions 226 as shown inFIG. 42 . Theprotrusions 226 protrude from the respective resin abutment side surfaces 224 in plan view. Each of theprotrusions 226 has anengagement surface 226 a. - The
engagement surface 226 a protrudes from the resinabutment side surface 224. Theengagement surface 226 a and the resinabutment side surface 224 form a right angle. In other words, theengagement surface 226 a is orthogonal to the resinabutment side surface 224. Note that theengagement surface 226 a maybe inclined to the resinabutment side surface 224. Theengagement surface 226 a faces downward in the z direction (downward inFIG. 42 ). Accordingly, theengagement surface 226 a is parallel to a x-y plane. Theengagement surface 226 a is in contact with the sealingresin 6. -
FIG. 43 is a diagram for explaining a method for forming theprotrusions 226.FIG. 43 shows a succeeding plating layer formation step of the manufacturing method according to the present embodiment. - In the succeeding plating layer formation step, a resist
layer 805 is patterned by photolithography in areas other than the areas on which the plating layers 820 d are to be formed, in the same manner as in the first embodiment. Thereafter, the plating layers 820 d are laminated by electrolytic plating. In this process, the electrolytic plating is continued until thickness of each of the plating layers exceeds the thickness of the patterned resistlayer 805, so that the plating layers 820 d grow along the top surface of the resistlayer 805. Then, the resistlayer 805 is removed to thereby form theprotrusions 226 of thecolumnar portions 22. - The semiconductor device A6 also uses wires formed by plating, and can therefore achieve the same effect as in the first embodiment. That is, the semiconductor device A6 can be made thinner.
- According to the present embodiment, the
columnar portions 22 include theprotrusions 226. Theprotrusions 226 have the engagement surfaces 226 a. Each of the engagement surfaces 226 a protrudes from the resinabutment side surface 224 and is in contact with the sealingresin 6. With such a structure, even if a stress is applied to theinternal electrode 2 outward in the z direction, theengagement surface 226 a is caught by the sealingresin 6. Accordingly, the semiconductor device A6 prevents theinternal electrode 2 from slipping out in the z direction. - In the first to sixth embodiments, two
external electrodes 3 are exposed from each of the two resin side surfaces 63 facing in the x direction. However, the number of theexternal electrodes 3 is not limited. Furthermore, the arrangement and shape of theinternal electrode 2 are not limited to those described above. For example, theinternal electrode 2 may be formed (installed) as shown inFIGS. 44 to 46 .FIGS. 44 to 46 are plan views. InFIGS. 44 to 46 , theconductive bonding members 5 and the sealingresin 6 are omitted, and thesemiconductor element 1 is indicated by an imaginary line (two-dot chain line). Note that inFIGS. 45 and 46 ,regions 19 indicated by imaginary lines (two-dot chain lines) may be provided with elements such as resistors, capacitors, or other semiconductor elements. - Although the first to sixth embodiments have given an example of a SON resin package having terminals on two side surfaces of the semiconductor device (two resin side surfaces 63 facing in the x direction in the above examples), other examples are also possible. For example, it is possible to employ a QFN resin package having terminals on four side surfaces of the semiconductor device.
- In the first to sixth embodiments, one
wiring layer 21 is provided in the z direction. However, a plurality of wiring layers 21 may be provided in the z direction.FIGS. 47 and 48 show a semiconductor device having a multi-layer structure with two wiring layers 21 (afirst wiring layer 21A and asecond wiring layer 21B) in the z direction.FIG. 47 is a plan view showing the semiconductor device.FIG. 47 omits the sealingresin 6.FIG. 48 is a sectional view along line G-G inFIG. 47 . - As shown in
FIG. 48 , theinternal electrode 2 includes first wiring layers 21A, second wiring layers 21B, andcolumnar portions 22. Parts of thefirst wiring layers 21A and the second wiring layers 21B are in contact with each other, whereas the other parts of theselayers film 43. The insulatingfilm 43 is made of a polyimide resin, for example. Thecolumnar portions 22 protrude from the second wiring layers 21B in the z direction. In this way, thecolumnar portions 22 may also be provided for the semiconductor device with a multi-layer structure where the plurality of wiring layers 21 are provided in the z direction. - The semiconductor device according to the present disclosure and the method for manufacturing the semiconductor device are not limited to those described in the above embodiments. Various design changes can be made to the specific structures of the elements of the semiconductor device according to the present disclosure, and to the details of the steps of the method for manufacturing the semiconductor device.
Claims (17)
1-21. (canceled)
22. A semiconductor device, comprising:
a semiconductor element;
a wiring layer portion to which the semiconductor element is mounted by flip chip bonding;
a first conductive portion which is located lower than the wiring layer portion and is located opposite to the semiconductor element with respect to the wiring layer portion; and
a second conductive portion which is located over the first conductive portion and is electrically connected to both of the first conductive portion and the wiring layer portion,
wherein the first conductive portion includes a projecting portion protruding in a thickness direction of the semiconductor device.
23. The semiconductor device according to claim 22 , wherein the semiconductor element includes a projection conductive electrode.
24. The semiconductor device according to claim 23 , wherein the projection conductive electrode contains copper.
25. The semiconductor device according to claim 24 , wherein the first conductive portion includes a surface thin metal covering layer.
26. The semiconductor device according to claim 25 , wherein the surface thin metal covering layer includes a portion formed on the second conductive portion.
27. The semiconductor device according to claim 26 , further comprising a sealing resin covering the semiconductor element, the wiring layer portion, the first conductive portion, and the second conductive portion.
28. The semiconductor device according to claim 27 , wherein one edge of the sealing resin and one edge of the second conductive portion are flush with each other.
29. The semiconductor device of claim 22 , wherein each of the first conductive portion and the second conductive portion contains copper.
30. A semiconductor device, comprising:
a semiconductor element;
a wiring layer including a first wiring portion to which the semiconductor element is mounted, a second wiring portion located lower than the first wiring portion and located opposite to the semiconductor element with respect to the first wiring portion, and a third wiring portion located over the second wiring portion and is electrically connected to the second wiring portion and the first wiring portion; and
a sealing resin covering the first wiring portion, the second wiring portion, and the third wiring portion,
wherein the sealing resin includes an intruding portion that intrudes into a space formed by respective inner surfaces of the first wiring portion, the second wiring portion and the third wiring portion, so that the inner surface of the first wiring portion and a part of the inner surface of the third wiring portion face each other via the intruding portion.
31. The semiconductor device according to claim 30 , wherein the second wiring portion includes a projecting portion protruding in a thickness direction of the semiconductor device.
32. The semiconductor device according to claim 31 , wherein the semiconductor element includes a projection conductive electrode.
33. The semiconductor device according to claim 32 , wherein the projection conductive electrode contains copper.
34. The semiconductor device according to claim 33 , wherein the second wiring portion includes a surface thin metal covering layer.
35. The semiconductor device according to claim 34 , wherein the surface thin metal covering layer includes a portion formed on the third wiring portion.
36. The semiconductor device according to claim 35 , wherein one edge of the sealing resin and one edge of the third wiring portion are flush with each other.
37. The semiconductor device according to claim 36 , wherein each of the second wiring portion and the third wiring portion contains copper.
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US16/354,540 US11004782B2 (en) | 2018-03-16 | 2019-03-15 | Semiconductor device with internal and external electrode and method of manufacturing |
US17/225,840 US11616009B2 (en) | 2018-03-16 | 2021-04-08 | Method of manufacturing semiconductor device with internal and external electrode |
US18/171,156 US20230207444A1 (en) | 2018-03-16 | 2023-02-17 | Semiconductor device and method for manufacturing the same |
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US11404375B2 (en) | 2019-09-26 | 2022-08-02 | Rohm Co., Ltd. | Terminal configuration and semiconductor device |
JP7326115B2 (en) * | 2019-09-26 | 2023-08-15 | ローム株式会社 | Terminal, semiconductor device, and manufacturing method thereof |
US11244881B2 (en) * | 2019-09-30 | 2022-02-08 | Texas Instruments Incorporated | Package terminal cavities |
JP7346221B2 (en) * | 2019-10-09 | 2023-09-19 | ローム株式会社 | Semiconductor device and semiconductor device manufacturing method |
JP7388911B2 (en) * | 2019-12-23 | 2023-11-29 | ローム株式会社 | Semiconductor device and its manufacturing method |
CN113380632A (en) * | 2021-05-07 | 2021-09-10 | 通富微电子股份有限公司 | Semiconductor packaging device and preparation method thereof |
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US6777819B2 (en) | 2000-12-20 | 2004-08-17 | Siliconware Precision Industries Co., Ltd. | Semiconductor package with flash-proof device |
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-
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-
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- 2021-04-08 US US17/225,840 patent/US11616009B2/en active Active
-
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- 2022-03-30 JP JP2022055057A patent/JP7524244B2/en active Active
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- 2023-02-17 US US18/171,156 patent/US20230207444A1/en active Pending
Also Published As
Publication number | Publication date |
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JP2019161149A (en) | 2019-09-19 |
JP7524244B2 (en) | 2024-07-29 |
US11004782B2 (en) | 2021-05-11 |
JP2022091907A (en) | 2022-06-21 |
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US20190287890A1 (en) | 2019-09-19 |
US20210225755A1 (en) | 2021-07-22 |
US11616009B2 (en) | 2023-03-28 |
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