JP2021106177A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device that can be reduced in size.SOLUTION: A semiconductor device A1 comprises: a resin layer 10 having a resin upper surface 101 and a resin lower surface 102 facing opposite to each other in a thickness direction and a through-hole 11 penetrating from the resin upper surface 101 to the resin lower surface 102; a first wiring layer 21 disposed in the through-hole 11 and having an upper surface 211 facing the same side as the resin upper surface 101 and a lower surface 212 facing the same side as the resin lower surface 102; a second wiring layer 22 having an upper surface 221 facing the same side as the resin upper surface 101 and a lower surface 222 facing the same side as the resin lower surface 102 and disposed in contact with part of the resin upper surface 101 and in contact with the upper surface 211; and a semiconductor element 50 bonded to the upper surface 221 of the second wiring layer 22. A thickness of the first wiring layer 21 is equal to or greater than a thickness of the second wiring layer 22.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to semiconductor devices.

With the recent miniaturization of electronic devices, the miniaturization of semiconductor devices used in electronic devices is being promoted. For example, in Patent Document 1, a semiconductor element having a plurality of electrodes, an insulating layer covering the back surface on which the plurality of electrodes of the semiconductor element are formed, and an insulating layer formed on the insulating layer and electrically with the plurality of electrodes. A semiconductor device that is connected and includes a plurality of wires located outside the semiconductor element has been proposed.

Japanese Unexamined Patent Publication No. 2016-89081

By the way, in the above-mentioned semiconductor devices, miniaturization is required due to restrictions such as mounting space in electronic devices.
An object of the present disclosure is to provide a semiconductor device capable of miniaturization.

The semiconductor device according to one aspect of the present disclosure includes a resin upper surface and a resin lower surface facing opposite sides in the thickness direction, a resin layer having a through hole penetrating from the resin upper surface to the resin lower surface, and the through hole. A first wiring layer provided and having a first upper surface facing the same side as the resin upper surface, a first lower surface facing the same side as the resin lower surface, a second upper surface facing the same side as the resin upper surface, and the above. A second wiring layer having a part of the resin upper surface facing the same side as the resin lower surface and a second lower surface in contact with the first upper surface, and a semiconductor element bonded to the second upper surface of the second wiring layer. The thickness of the first wiring layer is equal to or greater than the thickness of the second wiring layer.

According to this configuration, the degree of freedom in arrangement of the semiconductor element and the wiring portion connecting the semiconductor element is increased. Therefore, the first wiring layer included in the wiring portion and the joint portion connecting the semiconductor device can be arranged so as to partially overlap in the thickness direction, and the semiconductor device can be miniaturized.

According to one aspect of the present disclosure, it is possible to provide a semiconductor device capable of miniaturization.

A schematic cross-sectional view showing a semiconductor device of one embodiment. The schematic plan view which shows the semiconductor device of one Embodiment. A partial cross-sectional view of a semiconductor device of a comparative example. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment. FIG. 6 is a schematic cross-sectional view for explaining a manufacturing process of the semiconductor device of one embodiment.

Hereinafter, embodiments and modifications will be described with reference to the drawings. The embodiments and modifications shown below exemplify configurations and methods for embodying the technical idea, and the materials, shapes, structures, arrangements, dimensions, etc. of each component are limited to the following. It's not something to do. Various changes can be made to each of the following embodiments and modifications. In addition, the following embodiments and modifications can be implemented in combination with each other within a technically consistent range.

(Semiconductor device configuration)
Hereinafter, the configuration of the semiconductor device A1 of one embodiment will be described with reference to FIGS. 1 and 2.
FIG. 1 is a schematic cross-sectional view of the semiconductor device A1 of the present embodiment. FIG. 2 is a schematic plan view of the semiconductor device A1 of the present embodiment.

The semiconductor device A1 shown in these figures is a device that is surface-mounted on circuit boards of various electronic devices. Here, for convenience of explanation, the thickness direction of the semiconductor device A1 is referred to as the thickness direction Z. Further, the direction along one side of the semiconductor device A1 orthogonal to the thickness direction Z (vertical direction in the plan view) is referred to as the first direction X. Further, a direction (horizontal direction in the plan view) orthogonal to both the thickness direction Z and the first direction X of the semiconductor device A1 is referred to as a second direction Y.

As shown in FIGS. 1 and 2, the semiconductor device A1 has a rectangular plate shape. The semiconductor device A1 includes a resin layer 10, a wiring portion 20, a bonding portion 40, a semiconductor element 50, a sealing resin layer 60, an external conductive film 71, and an external connection terminal 72.

The resin layer 10 has a resin upper surface 101, a resin lower surface 102, and a plurality of resin side surfaces 103. The resin upper surface 101 and the resin side surface 103 face opposite to each other in the thickness direction Z. The resin lower surface 102 is a flat surface. Each resin side surface 103 intersects the resin upper surface 101 and the resin lower surface 102, and is orthogonal to each other in the present embodiment. The resin side surface 103 faces either the first direction X or the second direction Y. Each resin side surface 103 is a flat surface.

The resin layer 10 is made of, for example, a resin having electrical insulation. As the resin constituting the resin layer 10, for example, a polyimide resin, a phenol resin, a PBO resin, or the like can be used. As the resin constituting the resin layer 10, a resin containing various fillers can also be used. The resin constituting the resin layer 10 is colored, for example, black. The thickness of the resin layer 10 is, for example, 10 μm.

The resin layer 10 has a plurality of through holes 11. Each through hole 11 penetrates the resin layer 10 from the resin upper surface 101 to the resin lower surface 102 in the thickness direction Z. As shown in FIG. 2, the resin layer 10 of the present embodiment has four through holes 11. Each through hole 11 has, for example, a rectangular shape when viewed from the thickness direction Z. The shape of each through hole 11 may be circular or polygonal.

Each through hole 11 is formed so that the opening on the resin upper surface 101 side is larger than the opening on the resin lower surface 102 side of the resin layer 10. That is, in the resin layer 10, the inner wall surface 104 forming the through hole 11 is inclined so that the size of the through hole 11 increases from the resin lower surface 102 toward the resin upper surface 101. The resin layer 10 has a ridge line portion 105 between the inner wall surface 104 and the resin upper surface 101 on the side of the resin upper surface 101. The ridge line portion 105 is curved so as to bulge toward the outside of the resin layer 10. The ridge line portion 105 of the resin layer 10 is formed so as to be gently continuous from the resin upper surface 101 to the inner wall surface 104 via the ridge line portion 105 in the cross section of the resin layer 10 along the thickness direction Z.

The wiring unit 20 has a first wiring layer 21 and a second wiring layer 22. The first wiring layer 21 is arranged in the through hole 11 of the resin layer 10. The thickness of the first wiring layer 21 is equal to the thickness of the resin layer 10. The equal thickness includes, for example, a predetermined ratio to the thickness of the resin layer 10, for example, an error of 5%.

The first wiring layer 21 has an upper surface 211, a lower surface 212, and a plurality of side surfaces 213. The upper surface 211 and the lower surface 212 face each other in the thickness direction Z. The upper surface 211 of the first wiring layer 21 faces the same side as the resin upper surface 101 of the resin layer 10. The side surface 213 of the first wiring layer 21 is in contact with the inner wall surface 104 of the resin layer 10. In the first wiring layer 21, the end portion 211a of the upper surface 211 is inclined toward the side of the lower surface 212 and is curved so as to bulge toward the outside of the first wiring layer 21. As a result, the side surface 213 of the first wiring layer 21 is in contact with the resin layer 10 from the position on the lower surface 212 side of the upper surface 211 to the resin lower surface 102 of the resin layer 10. Therefore, the first wiring layer 21 is formed in a substantially inverted quadrangular frustum shape in which the dimension on the upper surface 211 side is larger than the dimension on the lower surface 212 side. The first wiring layer 21 is made of a material having electrical conductivity. As the material of the first wiring layer 21, for example, Cu (copper), Cu alloy, or the like can be used.

The second wiring layer 22 is formed on the resin upper surface 101 of the resin layer 10 and the upper surface 211 of the first wiring layer 21. The second wiring layer 22 is made of a material having electrical conductivity and is electrically connected to the first wiring layer 21. The second wiring layer 22 has an upper surface 221 and a lower surface 222, and a plurality of side surfaces 223. The upper surface 221 and the lower surface 222 face opposite to each other in the thickness direction Z. The upper surface 221 is a flat surface. Each side surface 223 intersects the upper surface 221 and the lower surface 222. In this embodiment, each side surface 223 is tilted with respect to the first direction X or the second direction Y. The thickness of the second wiring layer 22 is, for example, 10 μm.

The second wiring layer 22 has a metal layer 23 and a conductive layer 24. The metal layer 23 and the conductive layer 24 are in contact with the resin upper surface 101 of the resin layer 10 and the upper surface 211 of the first wiring layer 21 in this order. The metal layer 23 is composed of, for example, a first layer and a second layer laminated on the first layer. The first layer contains, for example, Ti (titanium) as a main component, and is in contact with the resin upper surface 101 of the resin layer 10 and the upper surface 211 of the first wiring layer 21. The second layer contains, for example, Cu as a main component and is laminated on the first layer. The metal layer 23 is formed as a seed layer that forms the conductive layer 24. The conductive layer 24 is formed on the upper surface of the metal layer 23. The conductive layer 24 contains, for example, Cu as a main component. The lower surface of the metal layer 23 constitutes the lower surface 222 of the second wiring layer 22, and the upper surface of the conductive layer 24 constitutes the upper surface 221 of the second wiring layer 22. The side surfaces of the metal layer 23 and the conductive layer 24 form the side surface 223 of the second wiring layer 22.

The joint portion 40 is formed on the upper surface 221 of the second wiring layer 22. The joint portion 40 conducts to the second wiring layer 22. The joint 40 connects the semiconductor element 50 to the second wiring layer 22.
The joint portion 40 includes a conductive layer 41, a plating layer 42, and a solder layer 43. The conductive layer 41, the plating layer 42, and the solder layer 43 are laminated on the second wiring layer 22 in this order.

The conductive layer 41 is made of Cu or an alloy containing Cu. The plating layer 42 is composed of Ni (nickel). The solder layer 43 is composed of Sn (tin) and an alloy containing Sn. This alloy is, for example, a Sn—Ag (silver) alloy, a Sn—Sb (antimony) alloy, or the like.

The semiconductor element 50 has a rectangular shape when viewed from the thickness direction Z. The semiconductor element 50 has an element main surface 501, an element back surface 502, and a plurality of element side surfaces 503. The element main surface 501 and the element back surface 502 face opposite to each other in the thickness direction Z. The element side surface 503 intersects the element main surface 501 and the element back surface 502. The element main surface 501 of the semiconductor element 50 faces the resin upper surface 101 of the resin layer 10. The element back surface 502 faces the same direction as the resin upper surface 101 of the resin layer 10.

The semiconductor element 50 is an integrated circuit (IC) such as an LSI (Large Scale Integration). Further, the semiconductor element 50 may be a voltage control element such as an LDO (Low Drop Out), an amplification element such as an operational amplifier, or a discrete semiconductor element such as a diode or various sensors. For example, in the case of an LSI, the element main surface 501 is a surface on which a constituent member for the function of the semiconductor element 50 is formed. The semiconductor element 50 is not limited to one in which a plurality of constituent members are formed, and the constituent members are formed on an element in which a single constituent member is formed, such as a chip capacitor or a chip inductor, or a base material other than a semiconductor. It can be a formed element. In this embodiment, the semiconductor element 50 is an LSI.

The semiconductor element 50 has a plurality of element electrodes 51. The semiconductor element 50 is electrically connected to the outside via a plurality of element electrodes 51. The element electrode 51 includes, for example, a conductive layer 52 and a barrier layer 53. The conductive layer 52 is made of, for example, an alloy containing CU and Cu. The barrier layer 53 is made of, for example, an alloy containing Ni and Ni.

The sealing resin layer 60 is formed so as to be in contact with the resin upper surface 101 of the resin layer 10 and to cover the semiconductor element 50. The sealing resin layer 60 is filled between the resin layer 10 and the semiconductor element 50. As a result, the sealing resin layer 60 covers the resin upper surface 101 of the resin layer 10, the surface of the second wiring layer 22 formed on the resin upper surface 101, and the joint portion 40 on the second wiring layer 22. Further, the sealing resin layer 60 covers the entire semiconductor element 50, that is, the element main surface 501, the element back surface 502, the element side surface 503, and the element electrode 51.

The sealing resin layer 60 overlaps with the resin layer 10 when viewed from the thickness direction Z. The sealing resin layer 60 has a resin upper surface 601, a resin lower surface 602, and a plurality of resin side surfaces 603. The resin upper surface 601 and the resin lower surface 602 face opposite to each other in the thickness direction Z. Each resin side surface 603 intersects the resin upper surface 601 and the resin lower surface 602, and is orthogonal to each other in the present embodiment. The resin side surface 603 faces either the first direction X or the second direction Y. Each resin side surface 603 is a flat surface.

The resin upper surface 601 of the sealing resin layer 60 faces the same direction as the resin upper surface 101 of the resin layer 10. The resin lower surface 602 of the sealing resin layer 60 faces the resin upper surface 101 of the resin layer 10 and is in contact with the resin upper surface 101. The resin side surface 603 of the sealing resin layer 60 is flush with the resin side surface 103 of the resin layer 10.

The sealing resin layer 60 is made of, for example, a resin having electrical insulation. As this resin, for example, a synthetic resin containing an epoxy resin as a main component can be used. Further, the sealing resin layer 60 is colored black, for example. The material and shape of the sealing resin layer 60 are not limited.

The external conductive film 71 is formed so as to cover the lower surface 212 of the first wiring layer 21 of the wiring portion 20 exposed from the resin lower surface 102 of the resin layer 10. The external conductive film 71 serves as an external connection terminal for the semiconductor device A1. The external conductive film 71 is composed of, for example, a plurality of metal layers laminated with each other. Examples of the metal layer include a Ni layer, a Pd (palladium) layer, and an Au (gold) layer. The material of the external conductive film 71 is not limited, but may be configured by laminating, for example, a Ni layer and an Au layer, or may be Sn.

An external connection terminal 72 is formed on the lower surface of the external conductive film 71. The external connection terminal 72 has a semicircular shape when viewed from a direction orthogonal to the thickness direction Z. The shape of the external connection terminal 72 may be any shape such as an inverted trapezoidal shape when viewed from a direction orthogonal to the thickness direction Z. The external connection terminal 72 is made of, for example, an alloy containing Sn and Sn. This alloy is, for example, a Sn—Ag-based alloy, a Sn—Sb-based alloy, or the like.

(Manufacturing process of semiconductor devices)
Next, an example of the manufacturing process of the semiconductor device A1 of the present embodiment will be described with reference to FIGS. 4 to 15. It should be noted that FIGS. 4 to 15 show a portion related to one semiconductor device A1. In the description of the manufacturing process, some members that will finally become the constituent members of the semiconductor device A1 shown in FIGS. 1 and 2 will be described with reference to the reference numerals given in FIGS. 1 and 2. The two broken lines shown in FIGS. 4 to 15 indicate the range of one semiconductor device A1. The definition of each direction shown in these figures is the same as the definition of the direction shown in FIGS. 1 and 2.

As shown in FIG. 4, the support substrate 800 is prepared. The support substrate 800 has an upper surface 800a and a lower surface 800b facing opposite sides in the thickness direction Z. The support substrate 800 is, for example, a substrate made of a single crystal material of Si (silicon). A glass substrate may be prepared as the support substrate 800.

A seed layer 801 is formed on the upper surface 800a of the support substrate 800. The seed layer 801 is formed so as to cover the entire upper surface 800a of the support substrate 800 by, for example, a sputtering method. The seed layer 801 is, for example, a metal film containing Ti as a main component. The support substrate 800 may have an oxide film formed on the support substrate 800. In this case, the surface of the oxide film is the upper surface 800a, and the seed layer 801 is formed on the surface of the oxide film.

As shown in FIG. 5, a resin layer 810 is formed on the upper surface 801a of the seed layer 801. The resin layer 810 corresponds to the resin layer 10 of the semiconductor device A1 shown in FIG. The resin layer 810 is an insulating film made of a photosensitive resin material such as a polyimide resin, a phenol resin, or a PBO resin. In the step of forming the resin layer 810, the resin layer 810 is formed on the upper surface 801a of the seed layer 801 by using, for example, a spin coater (rotary coating device). A film-like photosensitive resin material may be attached. Then, patterning is performed by exposing and developing the photosensitive resin material. By this patterning, a through hole 11 that exposes a part of the upper surface 801a of the seed layer 801 is formed in the resin layer 810. Then, in the resin layer 810, the inner wall surface 104 forming the through hole 11 is inclined so that the size of opening from the lower surface 810b of the resin layer 810 toward the upper surface 810a of the resin layer 810 is increased. Further, the resin layer 810 has a curved ridge line portion 105 at the end portion of the through hole 11.

As shown in FIG. 6, the first wiring layer 21 in contact with the upper surface 801a of the seed layer 801 is formed.
The first wiring layer 21 can be formed by, for example, an electrolytic plating method. The first wiring layer 21 can be formed by depositing a plated metal on the upper surface 801a of the seed layer 801 by an electrolytic plating method using the seed layer 801 as a conductive path. The first wiring layer 21 formed in this way is in contact with the inner wall surface 104 of the resin layer 810 forming the through hole 11. Further, the thickness of the first wiring layer 21 is equal to the thickness of the resin layer 810 (resin layer 10). Then, the ridge line portion 105 of the resin layer 810 forms a recess 31 at the boundary portion between the upper surface 801a of the resin layer 810 and the upper surface 211 of the first wiring layer 21. The recess 31 is formed in a frame shape when viewed from the thickness direction Z so as to surround the first wiring layer 21.

As shown in FIG. 7, the metal layer 823 is formed. The metal layer 823 is a portion that becomes the metal layer 23 that constitutes the second wiring layer 22 shown in FIG. The metal layer 823 is formed so as to cover the first wiring layer 21 and the resin layer 810 by, for example, a sputtering method. The metal layer 823 includes, for example, a Ti layer and a Cu layer. The metal layer 823 forms a Ti layer on the upper surface 810a of the resin layer 810 and the upper surface 211 of the first wiring layer 21, and forms a Cu layer in contact with the Ti layer. The metal layer 823 is formed so as to enter the recess 31 formed at the boundary between the upper surface 810a of the resin layer 810 and the end portion of the first wiring layer 21 and fill the recess 31.

As shown in FIG. 8, a resist layer 802 having an opening 802c is formed. The resist layer 802 can be formed by, for example, photolithography. For example, the resist layer 802 is formed by applying a photosensitive resist so as to cover the entire surface of the metal layer 823, and then exposing and developing the photosensitive resist. The opening 802c of the resist layer 802 is formed so that the opening width increases from the upper surface 823a of the metal layer 823 toward the upper surface 802a of the resist layer 802.

As shown in FIG. 9, the conductive layer 24 is formed. The conductive layer 24 can be formed by, for example, an electrolytic plating method. The conductive layer 24 can be formed by depositing a plated metal on the upper surface 823a of the metal layer 823 by an electrolytic plating method using the metal layer 823 as a conductive path.

As shown in FIG. 10, the resist layer 802 (see FIG. 9) that serves as a mask when the conductive layer 24 is formed is removed. Then, the metal layer 823 exposed from the conductive layer 24 is removed. The metal layer 823 can be removed by, for example, wet etching. As a result, as shown in FIG. 11, the second wiring layer 22 composed of the metal layer 23 and the conductive layer 24 is formed.

As shown in FIG. 12, a joint portion 40 is formed on the upper surface 221 of the second wiring layer 22, and the semiconductor element 50 is mounted. As shown in FIG. 1, the joint portion 40 includes a conductive layer 41, a plating layer 42, and a solder layer 43. First, the conductive layer 41 is formed on the second wiring layer 22. Next, the plating layer 42 is formed on the conductive layer 41. Then, the solder layer 43 is formed on the plating layer 42.

The joint 40 is formed, for example, in an opening of a resist layer (not shown) that covers the second wiring layer 22. The conductive layer 41 is formed by precipitating Cu or an alloy containing Cu by an electrolytic plating method using the second wiring layer 22 as a conductive path. The plating layer 42 is formed by precipitating an alloy containing Ni or Ni by, for example, an electrolytic plating method using the conductive layer 41 as a conductive path. The solder layer 43 is formed by, for example, precipitating an alloy containing Sn by an electrolytic plating method using the plating layer 42 as a conductive path. After that, the surface of the solder layer 43 having roughness is smoothed by melting the solder layer 43 by a reflow process.

Next, the semiconductor element 50 is mounted. The semiconductor element 50 is mounted by flip chip bonding (FCB: Flip Chip Bonding). Flux is transferred and applied to the solder layer 43 of the joint portion 40, and the semiconductor element 50 is flip-chip mounted using a flip-chip bonder. As a result, the semiconductor element 50 is temporarily attached to the joint portion 40. After that, the solder layer 43 of the joint portion 40 is brought into a liquid phase state by a reflow process, and then the solder layer 43 is solidified by cooling to connect the semiconductor element 50 to the joint portion 40.

As shown in FIG. 13, a resin layer 860 that covers the upper surface 810a of the resin layer 810 and the semiconductor element 50 is formed. The resin layer 860 is a member that becomes the sealing resin layer 60 shown in FIG. The resin layer 860 is, for example, a synthetic resin containing an epoxy resin as a main material. The resin layer 860 is formed by, for example, transfer molding.

As shown in FIG. 14, the support substrate 800 and the seed layer 801 shown in FIG. 13 are removed. Note that FIG. 14 is shown upside down with respect to FIG. For example, the tape 804 is attached to the lower surface 860b of the resin layer 860. As the tape 804, a tape for dicing can also be used. Then, for example, the support substrate 800 is removed by grinding. A method of forming a release film between the support substrate 800 and the resin layer 810 in advance and removing the support substrate 800 by a release method can also be used. The seed layer 801 can be removed by, for example, wet etching.

As shown in FIG. 15, the external conductive film 71 is formed on the surface (lower surface 212 shown in FIG. 1) of the first wiring layer 21 exposed from the resin layer 810. The external conductive film 71 is made of, for example, a plated metal. For example, the external conductive film 71 is formed by depositing plated metals such as Ni, Pd, and Au on the lower surface 212 of the first wiring layer 21 in this order by an electroless plating method. The configuration and forming method of the external conductive film are not limited.

Next, the external connection terminal 72 is formed on the external conductive film 71. The external connection terminal 72 is made of an alloy containing Sn and Sn. The external connection terminal 72 is formed by reflowing a solder paste applied on the external conductive film 71 or a solder ball mounted on the external conductive film 71.

Next, the resin layer 810 and the resin layer 860 are cut to separate the semiconductor element 50 into pieces. In the individualization of the semiconductor element 50, for example, a dicing blade cuts from the side of the resin layer 810 to the tape 804, cuts the resin layer 810 and the resin layer 860, and forms the resin layer 10 and the sealing resin layer 60. The semiconductor device A1 is obtained by peeling the sealing resin layer 60 from the tape 804.

(Comparison example)
FIG. 3 is a cross-sectional view showing a part of the semiconductor device A2 of the comparative example. In the semiconductor device A2 of the comparative example, the same components as the semiconductor device A1 of the present embodiment will be described with the same reference numerals.

The semiconductor device A2 of this comparative example has a different shape of the wiring portion 20 from the semiconductor device A1 of the present embodiment. The semiconductor device A2 of the comparative example does not have the first wiring layer 21, and the second wiring layer 22 is formed from the resin upper surface 101 of the resin layer 10 to the inside of the through hole 11. In the semiconductor device A2, a joint portion 40 for connecting the semiconductor element 50 is formed in a portion of the second wiring layer 22 that overlaps with the resin upper surface 101 of the resin layer 10. In the semiconductor device A2, the through hole 11 and the joint portion 40 are completely displaced from each other when viewed from the thickness direction Z. Therefore, the through hole 11 is arranged outside the semiconductor device A1 with respect to the joint portion 40 connecting the semiconductor element 50, and the semiconductor device A2 becomes larger. If the joint portion 40 is to be provided at a position where it overlaps with the through hole 11 in the thickness direction Z, a step of flattening the upper surface of the second wiring layer 22 is required.

Further, in the semiconductor device A2 of the comparative example, the second wiring layer 22 is formed in the through hole 11 of the resin layer 10. The second wiring layer 22 includes a metal layer 23 and a conductive layer 24 formed on the metal layer 23. The metal layer 23 exposed from the resin lower surface 102 of the resin layer 10 is removed by, for example, etching, and the conductive layer 24 is exposed. At the time of this etching, the metal layer 23 between the resin layer 10 and the conductive layer 24 is excessively removed, and a gap may be formed between the conductive layer 24 and the resin layer 10.

(Action)
The operation of the semiconductor device A1 of the present embodiment will be described.
The wiring portion 20 of the semiconductor device A1 of the present embodiment includes a first wiring layer 21 arranged in the through hole 11 of the resin layer 10 and a second wiring layer 22 in contact with the upper surface 211 of the first wiring layer 21. is doing. Therefore, the upper surface 221 of the second wiring layer 22 can be a flat surface. Then, the joint portion 40 for connecting the semiconductor element 50 can be arranged at a position overlapping the first wiring layer 21 in the thickness direction Z with respect to the upper surface 221 of the second wiring layer 22. Therefore, the semiconductor device A1 can be miniaturized.

Further, in the semiconductor device A1 of the present embodiment, the first wiring layer 21 is arranged in the through hole 11 of the resin layer 10. The lower surface 212 of the first wiring layer 21 is exposed on the resin lower surface 102 of the resin layer 10. The second wiring layer 22 includes a metal layer 23 in contact with the upper surface 211 of the first wiring layer 21, and a conductive layer 24 formed on the metal layer 23. The side surface 213 of the first wiring layer 21 is in contact with the inner wall surface 104 of the through hole 11 of the resin layer 10. That is, the metal layer 23 does not intervene between the first wiring layer 21 and the resin layer 10. Therefore, the etching process from the side of the resin lower surface 102 of the resin layer 10 becomes unnecessary.

The through hole 11 of the resin layer 10 is formed so that the opening on the resin upper surface 101 side is larger than the opening on the resin lower surface 102 side of the resin layer 10. The size of the lower surface 212 of the first wiring layer 21 arranged in the through hole 11 is smaller than the size of the upper surface 211. Therefore, it is possible to prevent the first wiring layer 21 from falling out of the resin layer 10.

As described above, according to the present embodiment, the following effects are obtained.
(1) The wiring portion 20 of the semiconductor device A1 has a first wiring layer 21 arranged in the through hole 11 of the resin layer 10 and a second wiring layer 22 in contact with the upper surface 211 of the first wiring layer 21. ing. Therefore, the upper surface 221 of the second wiring layer 22 can be a flat surface. Then, the joint portion 40 for connecting the semiconductor element 50 can be arranged at a position overlapping the first wiring layer 21 in the thickness direction Z with respect to the upper surface 221 of the second wiring layer 22. Therefore, the semiconductor device A1 can be miniaturized.

(2) The first wiring layer 21 is arranged in the through hole 11 of the resin layer 10. The lower surface 212 of the first wiring layer 21 is exposed on the resin lower surface 102 of the resin layer 10. The second wiring layer 22 includes a metal layer 23 in contact with the upper surface 211 of the first wiring layer 21, and a conductive layer 24 formed on the metal layer 23. The side surface 213 of the first wiring layer 21 is in contact with the inner wall surface 104 of the through hole 11 of the resin layer 10. That is, the metal layer 23 does not intervene between the first wiring layer 21 and the resin layer 10. Therefore, the etching process from the side of the resin lower surface 102 of the resin layer 10 becomes unnecessary.

(3) The through hole 11 of the resin layer 10 is formed so that the opening on the resin upper surface 101 side is larger than the opening on the resin lower surface 102 side of the resin layer 10. The size of the lower surface 212 of the first wiring layer 21 arranged in the through hole 11 is smaller than the size of the upper surface 211. Therefore, it is possible to prevent the first wiring layer 21 from falling out of the resin layer 10.

(Change example)
This embodiment can be modified and implemented as follows.
-At least one of the conductive layer 41 and the plating layer 42 of the joint portion 40 may be omitted.

In the wiring portion 20, the side surface 223 of the second wiring layer 22 may face in a direction orthogonal to the thickness direction Z.
-The external connection terminal 72 may be omitted.

-The shape of the resin layer 10 can be changed as appropriate. For example, in the shape of the through hole 11, the resin layer 10 may be formed so that the opening on the resin upper surface 101 side is smaller than the opening on the resin lower surface 102 side of the resin layer 10. Further, the inner wall surface 104 of the resin layer 10 constituting the through hole 11 may be formed so that the angle formed between the resin layer 10 and the resin lower surface 102 is a right angle or close to a right angle. Further, the ridge line portion 105 may be formed so that the resin upper surface 101 and the inner wall surface 104 intersect.

The technical idea that can be grasped from the above-described embodiment and modified example will be described.
(Appendix 1)
The inner wall surface of the through hole is inclined so that the through hole becomes larger from the lower surface of the resin toward the upper surface of the resin.
The side surface of the first wiring layer is in contact with the inner wall surface of the through hole.
The semiconductor device according to any one of claims 1 to 9.

(Appendix 2)
The semiconductor device according to any one of claims 1 to 9, wherein the resin layer has a curved ridge line portion between the upper surface of the resin and the inner wall surface of the through hole.

A1, A2 Semiconductor device 10 Resin layer 11 Through hole 20 Wiring part 21 First wiring layer 22 Second wiring layer 23 Metal layer 24 Conductive layer 31 Recess 40 Joint 41 Conductive layer 42 Plating layer 43 Solder layer 50 Semiconductor element 51 Element electrode 52 Conductive layer 53 Barrier layer 60 Encapsulating resin layer 71 External conductive film 72 External connection terminal 101 Resin top surface 102 Resin bottom surface 103 Resin side surface 104 Inner wall surface 105 Ridge line part 211 Top surface 211a End part 212 Bottom surface 213 Side surface 221 Top surface 222 Bottom surface 223 Side surface 501 Element main surface 502 Element back surface 503 Element side surface 601 Resin upper surface 602 Resin lower surface 603 Resin side surface 800 Support substrate 800a Upper surface 800b Lower surface 801 Seed layer 801a Upper surface 802 Resist layer 802a Upper surface 802c Opening 804 Tape 810 Resin layer 810 Upper surface 860 Resin layer 860b Lower surface X 1st direction Y 2nd direction Z Thickness direction

Claims (9)

A resin upper surface and a resin lower surface facing opposite sides in the thickness direction, and a resin layer having a through hole penetrating from the resin upper surface to the resin lower surface.
A first wiring layer disposed in the through hole and having a first upper surface facing the same side as the resin upper surface and a first lower surface facing the same side as the resin lower surface.
A second wiring layer having a second upper surface facing the same side as the resin upper surface, and a second lower surface facing the same side as the resin lower surface and in contact with a part of the resin upper surface and the first upper surface.
A semiconductor element bonded to the second upper surface of the second wiring layer, and
With
The thickness of the first wiring layer is equal to or greater than the thickness of the second wiring layer.
Semiconductor device. The semiconductor device according to claim 1, wherein the thickness of the first wiring layer is equal to the thickness of the resin layer. The semiconductor device according to claim 1 or 2, wherein the peripheral edge portion of the first wiring layer has a curved ridge line portion. The semiconductor device according to any one of claims 1 to 3, wherein the resin layer is composed of a polyimide resin or a phenol resin. The semiconductor device according to any one of claims 1 to 4, wherein the first wiring layer is made of Cu or an alloy containing Cu. The second wiring layer is composed of a metal layer in contact with a part of the resin upper surface of the resin layer, the first upper surface of the first wiring layer, and a plating layer in contact with the upper surface of the metal layer. The semiconductor device according to any one of claims 1 to 5. The semiconductor device according to claim 6, wherein the metal layer is composed of a Ti layer and a Cu layer, and the plating layer is composed of Cu or an alloy containing Cu. The semiconductor device according to any one of claims 1 to 7, further comprising a sealing resin layer covering the semiconductor element. The semiconductor device according to any one of claims 1 to 8, further comprising an external conductive film covering the first lower surface of the first wiring layer.

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