KR100742902B1 - 웨이퍼 레벨 csp의 제조방법 - Google Patents

웨이퍼 레벨 csp의 제조방법 Download PDF

Info

Publication number
KR100742902B1
KR100742902B1 KR1020040073293A KR20040073293A KR100742902B1 KR 100742902 B1 KR100742902 B1 KR 100742902B1 KR 1020040073293 A KR1020040073293 A KR 1020040073293A KR 20040073293 A KR20040073293 A KR 20040073293A KR 100742902 B1 KR100742902 B1 KR 100742902B1
Authority
KR
South Korea
Prior art keywords
thermal stress
stress relaxation
post
redistribution circuit
insulating layer
Prior art date
Application number
KR1020040073293A
Other languages
English (en)
Other versions
KR20050028313A (ko
Inventor
다케히코 무라카미
Original Assignee
미나미 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미나미 가부시키가이샤 filed Critical 미나미 가부시키가이샤
Publication of KR20050028313A publication Critical patent/KR20050028313A/ko
Application granted granted Critical
Publication of KR100742902B1 publication Critical patent/KR100742902B1/ko

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/562Protection against mechanical damage
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0236Shape of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/024Material of the insulating layers therebetween
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/033Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0331Manufacturing methods by local deposition of the material of the bonding area in liquid form
    • H01L2224/0332Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05567Disposition the external layer being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05599Material
    • H01L2224/056Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132Screen printing, i.e. using a stencil
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01075Rhenium [Re]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01078Platinum [Pt]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01327Intermediate phases, i.e. intermetallics compounds
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

열응력 완화 포스트, 절연층 및 납땜범프의 형성을 능률 좋게 행할 수 있도록 하여 전체의 제조능률을 큰폭으로 향상시킨다.
웨이퍼(1) 위에 도금에 의한 재배선(再配線)회로(3)를 형성함과 동시에 이 재배선회로(3) 위에 납땜 등의 도전재료에 의한 열응력 완화 포스트(4)를 형성한다. 또한, 이들 재배선회로(3)와 열응력 완화 포스트(4)의 주위에 이 열응력 완화 포스트(4)의 상면을 제외하고 폴리이미드 등으로 이루어지는 절연층(6)을 형성하고, 상기 열응력 완화 포스트(4) 위에 납땜범프(7)를 더 형성한다. 그리고 상기 열응력 완화 포스트(4), 절연층(6) 및 납땜범프(7)는 스크린 인쇄에 의해 형성된다.

Description

웨이퍼 레벨 CSP의 제조방법{METHOD OF MANUFACTURING A WAFER LEVEL CSP}
도 1은 본 발명에 따라 제조된 웨이퍼 레벨 CSP의 단면도이다.
도 2는 종래 방법에 따라 제조된 웨이퍼 레벨 CSP의 단면도이다.
* 주요 부호의 설명 *
1 웨이퍼
2 접합패드
3 재배선회로
4 열응력 완화 포스트
5 절연층
6 절연층
7 납땜범프
8 열응력 서포트층
8a 납땜범프의 하부 바깥 둘레의 수용부
본 발명은 웨이퍼 레벨 CSP의 제조방법에 관한 것이다.
휴대전화, 디지털 비디오, 디지털 카메라 등에 있어 고밀도 실장에 대한 요구에 의해 소형 패키지인 CSP(Chip Size Package)가 급속도로 보급되기 시작하고 있다.
이러한 CSP는 TSOP(Thin Small Outline Package)나 QFP(Quad Flat Package)와 같은 종래 리드 타입 패키지와 비교해서 실장 면적이 작고, 또 배선길이가 짧기 때문에 고주파 디바이스에도 적용하기 쉽다는 특징이 있다. 또한 칩을 직접 기판에 실장하는 플립 칩과 비교하면, 패드피치(pad pitch)를 넓힐 수 있어 기판으로의 실장이 용이하다는 특징도 있다. 환언하면, TSOP 종류의 취급용이성으로 플립 칩 종류의 고속, 고밀도 실장을 실현할 수 있다는 점이 급속하게 보급되기 시작한 요인이 되고 있다.
이에, 이러한 웨이퍼 레벨 CSP의 종래 제조 방법은 도 2에 도시된 바와 같이 웨이퍼(100) 위에 절연재료로 이루어지는 소요(所要) 두께의 열응력 완화층(101)을 형성하고, 이 열응력 완화층(101) 상면에 랜드(land;102)와 이 랜드(102)와 접합 패드(103)를 연결하는 재배선회로(104)를 형성하고, 이 재배선회로(104) 위에 절연층(105)을 더 형성한 후, 랜드(102) 위에 납땜범프(106)를 형성한 것이다. 한편, 열응력 완화층(101)은 웨이퍼를 프린트 기판에 실장한 때 웨이퍼와 프린트 기판의 선팽창계수차에 의해 발생되는 납땜범프의 열 왜곡(변형)을 저감시키고, 접속수명을 향상시키기 위한 것이다. 상기 열응력 완화층(101)은 탄성을 가지는 수지를 주재료로 하여, 납땜범프(106)의 왜곡에 따라 변형되고 이 변형에 의해 왜곡이 저감되는 것이다. 또한 그 외(107)는 웨이퍼(100) 위에 형성된 절연층이다.
그리고, 종래에 있어 열응력 완화층(101)은 인쇄에 의해, 또 재배선회로(104)는 도금에 의해, 또한 절연층(105)은 도포에 의해, 그리고 또 납땜범프(106)는 납땜 볼을 랜드(102) 상에 전재(轉載)하고 리플로우(reflow) 로(爐)에서 가열하여 형성하였다. 그러나 절연층(105)과 납땜범프(106)의 형성에 수고와 시간이 너무 걸리고, 작업능률이 떨어진다는 문제점이 있었다. 또한, 종래는 열응력 완화층(101)이 절연재료이기 때문에 이것의 상면 중앙에 랜드(102)를 형성하지 않으면 안되어, 이것의 형성에 여분의 시간이 걸린다는 문제점도 있었다.
본 발명은 상기의 점을 감안한 것으로 작업능률을 큰 폭으로 향상시킬 수 있도록 이루어진 웨이퍼 레벨 CSP의 제조방법을 제공하고자 하는 것이다.
이에, 본 발명의 요지는, 웨이퍼 위에 도금에 의한 재배선회로를 형성함과 동시에 이 재배선회로 위에 납땜 등의 도전재료에 의한 열응력 완화 포스트를 형성하고, 이들 재배선회로와 열응력 완화 포스트의 주위에 이 열응력 완화 포스트의 상면을 제외하고 폴리이미드 등으로 이루어지는 절연층을 형성하고, 상기 열응력 완화 포스트 위에 납땜범프를 더 형성하는 웨이퍼 레벨 CSP의 제조방법으로서, 상기 열응력 완화 포스트, 절연층 및 납땜범프의 형성을 스크린 인쇄에 의해 이루어지도록 한 것을 특징으로 하는 웨이퍼 레벨 CSP의 제조방법이다.
또한, 상기 제조방법에 있어, 열응력 완화 포스트를 형성하는 도전재료로서 납땜을 이용하는 것이 바람직하다. 이 경우, 열응력 완화 포스트의 재료인 납땜과 납땜범프와의 접합이 금속간 화합물에 의한 융합이 되고, 열응력 완화 포스트의 재료인 납땜과 도금에 의한 재배선회로 간의 상호 확산에 의한 융합보다도 강고(强固)하게 된다.
또한, 상기 제조방법에 있어, 절연층의 상면에 열응력 완화 포스트의 위치에 납땜범프의 하부 바깥 둘레의 수용부를 설치한 절연재료로 이루어지는 열응력 서포트층을 스크린 인쇄에 의해 형성하도록 하여도 무방하다. 이로써 납땜범프의 열 왜곡을 한층 저감할 수 있게 된다.
본 발명을 실시하기 위한 최적의 형태는 열응력 완화 포스트, 절연층 및 납땜범프의 형성을 스크린 인쇄에 의해 행하는 것이다.
이하, 본 발명의 실시예에 대해 도면을 참조하면서 설명한다.
도 1은 본 발명에 따라 제조된 웨이퍼 레벨 CSP의 단면을 도시한 것이다.
도면 중 1은 웨이퍼이다. 2는 상기 웨이퍼(1) 위에 형성된 접합 패드로서, 금(金)의 UBM이다. 3은 상기 웨이퍼(1) 위에 도금에 의해 형성된 재배선회로이다. 4는 상기 재배선회로(3) 위에 형성된 납땜 등의 도전재료에 의한 열응력 완화 포스트이며, 가압식 스크린 인쇄기에 의한 스크린 인쇄에 의해 형성되어 있다. 한편, 본 실시예에서는 도전재료로서 납땜을 이용하고 있다.
5는 웨이퍼(1) 위에 형성된 절연층, 6은 상기 재배선회로(3)와 열응력 완화 포스트(4) 주위에 이 열응력 완화 포스트(4)의 상면을 제외하고 형성된 폴리이미드 등으로 이루어지는 절연층이다. 또한 이 절연층(6)은 가압식 스크린 인쇄기에 의 한 스크린 인쇄에 의해 형성되어 있다.
7은 상기 열응력 완화 포스트(4) 위에 형성된 납땜범프로서, 가압식 스크린 인쇄기에 의한 스크린 인쇄에 의해 형성되어 있다. 8은 상기 절연층(6)의 상면에 형성된 열응력 완화 포스트(4)의 위치에 납땜범프(7)의 하부의 바깥 둘레의 수용부(8a)를 설치한 열응력 서포트층이다. 또한, 이 열응력 서포트층(8)은 폴리이미드 등의 절연재료로 이루어지고, 스크린 인쇄에 의해 형성되어 있다.
본 발명은 상기와 같이 열응력 완화 포스트, 절연층 및 납땜범프의 형성을 스크린 인쇄에 의해 행하는 것이므로, 종래의 제조방법과 비교하여 작업능률을 대폭 향상시킬 수 있다. 또한, 열응력 완화 포스트 위에 직접 납땜범프를 형성하기 때문에, 종래와 같이 랜드를 형성할 필요가 없다. 따라서, 그만큼의 작업공정을 줄일 수 있다.
또한, 열응력 완화 포스트를 형성하는 도전재료로서 납땜을 이용하는 경우에, 납땜범프와의 접합이 금속간 화합물에 의한 융합이 되어 견고한 접합을 가진다.
또한, 절연층의 상면에 열응력 완화 포스트의 위치에 납땜범프의 하부 바깥둘레의 수용부를 설치한 절연재료로 이루어지는 열응력 서포트층을 스크린 인쇄에 의해 형성하도록 한 경우, 납땜범프의 열 왜곡을 한층 저감시킬 수 있다.

Claims (4)

  1. 웨이퍼 위에 도금에 의한 재배선회로를 형성함과 동시에 상기 재배선회로 위에 도전재료에 의한 열응력 완화 포스트를 형성하고, 상기 재배선회로와 열응력 완화 포스트 주위에 절연재료로 이루어지는 절연층을 형성하며, 또한 상기 절연층 상에 절연재료로 이루어지는 열응력 서포트층을 형성하고, 상기 열응력 완화 포스트의 상면 주위에서 상기 열응력 서포트층에 수용부를 형성하며, 상기 열응력 완화 포스트 위에 그리고 상기 수용부에 납땜범프를 형성하는 웨이퍼 레벨 CSP의 제조방법으로서, 상기 열응력 완화 포스트, 절연층, 열응력 서포트층 및 납땜범프의 형성을 스크린 인쇄에 의해 행하는 것을 특징으로 하는 웨이퍼 레벨 CSP의 제조방법.
  2. 삭제
  3. 삭제
  4. 삭제
KR1020040073293A 2003-09-18 2004-09-14 웨이퍼 레벨 csp의 제조방법 KR100742902B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003325938A JP4360873B2 (ja) 2003-09-18 2003-09-18 ウエハレベルcspの製造方法
JPJP-P-2003-00325938 2003-09-18

Publications (2)

Publication Number Publication Date
KR20050028313A KR20050028313A (ko) 2005-03-22
KR100742902B1 true KR100742902B1 (ko) 2007-07-25

Family

ID=34191342

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020040073293A KR100742902B1 (ko) 2003-09-18 2004-09-14 웨이퍼 레벨 csp의 제조방법

Country Status (8)

Country Link
US (2) US20050064624A1 (ko)
EP (1) EP1517369A3 (ko)
JP (1) JP4360873B2 (ko)
KR (1) KR100742902B1 (ko)
CN (1) CN1604295A (ko)
MY (1) MY139562A (ko)
SG (1) SG157220A1 (ko)
TW (1) TWI253128B (ko)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100452377C (zh) * 2005-12-01 2009-01-14 联华电子股份有限公司 芯片与封装结构
KR100713932B1 (ko) * 2006-03-29 2007-05-07 주식회사 하이닉스반도체 플립 칩 본디드 패키지
JP5075611B2 (ja) * 2007-12-21 2012-11-21 ローム株式会社 半導体装置
KR101678054B1 (ko) 2010-06-28 2016-11-22 삼성전자 주식회사 반도체 패키지 및 그 반도체 패키지 제조방법
US10163828B2 (en) * 2013-11-18 2018-12-25 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and fabricating method thereof
US9953954B2 (en) 2015-12-03 2018-04-24 Mediatek Inc. Wafer-level chip-scale package with redistribution layer
CN110767556A (zh) * 2019-10-30 2020-02-07 华虹半导体(无锡)有限公司 智能卡芯片的加工方法及智能卡芯片

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020074400A (ko) * 2001-03-19 2002-09-30 가시오게산키 가부시키가이샤 반도체장치 및 그 제조방법
KR20020081089A (ko) * 2001-04-17 2002-10-26 가시오게산키 가부시키가이샤 반도체 장치

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6114756A (en) * 1998-04-01 2000-09-05 Micron Technology, Inc. Interdigitated capacitor design for integrated circuit leadframes
JP3420703B2 (ja) * 1998-07-16 2003-06-30 株式会社東芝 半導体装置の製造方法
US6103552A (en) * 1998-08-10 2000-08-15 Lin; Mou-Shiung Wafer scale packaging scheme
KR100269540B1 (ko) * 1998-08-28 2000-10-16 윤종용 웨이퍼 상태에서의 칩 스케일 패키지 제조 방법
JP4237325B2 (ja) * 1999-03-11 2009-03-11 株式会社東芝 半導体素子およびその製造方法
JP4024958B2 (ja) * 1999-03-15 2007-12-19 株式会社ルネサステクノロジ 半導体装置および半導体実装構造体
EP1050905B1 (en) * 1999-05-07 2017-06-21 Shinko Electric Industries Co. Ltd. Method of producing a semiconductor device with insulating layer
AU5109900A (en) * 1999-06-15 2001-01-02 Fujikura Ltd. Semiconductor package, semiconductor device, electronic device, and method of manufacturing semiconductor package
JP2001144204A (ja) * 1999-11-16 2001-05-25 Nec Corp 半導体装置及びその製造方法
JP3386029B2 (ja) * 2000-02-09 2003-03-10 日本電気株式会社 フリップチップ型半導体装置及びその製造方法
US6383858B1 (en) * 2000-02-16 2002-05-07 Agere Systems Guardian Corp. Interdigitated capacitor structure for use in an integrated circuit
SG99939A1 (en) * 2000-08-11 2003-11-27 Casio Computer Co Ltd Semiconductor device
JP4394266B2 (ja) * 2000-09-18 2010-01-06 カシオ計算機株式会社 半導体装置および半導体装置の製造方法
JP4183375B2 (ja) * 2000-10-04 2008-11-19 沖電気工業株式会社 半導体装置及びその製造方法
JP3842548B2 (ja) * 2000-12-12 2006-11-08 富士通株式会社 半導体装置の製造方法及び半導体装置
US6756184B2 (en) * 2001-10-12 2004-06-29 Taiwan Semiconductor Manufacturing Co., Ltd Method of making tall flip chip bumps
JP3877150B2 (ja) * 2002-01-28 2007-02-07 日本電気株式会社 ウェーハレベル・チップスケール・パッケージの製造方法
US6803303B1 (en) * 2002-07-11 2004-10-12 Micron Technology, Inc. Method of fabricating semiconductor component having encapsulated, bonded, interconnect contacts
US6656827B1 (en) * 2002-10-17 2003-12-02 Taiwan Semiconductor Manufacturing Co., Ltd. Electrical performance enhanced wafer level chip scale package with ground
US6841883B1 (en) * 2003-03-31 2005-01-11 Micron Technology, Inc. Multi-dice chip scale semiconductor components and wafer level methods of fabrication

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20020074400A (ko) * 2001-03-19 2002-09-30 가시오게산키 가부시키가이샤 반도체장치 및 그 제조방법
KR20020081089A (ko) * 2001-04-17 2002-10-26 가시오게산키 가부시키가이샤 반도체 장치

Also Published As

Publication number Publication date
JP2005093772A (ja) 2005-04-07
CN1604295A (zh) 2005-04-06
TWI253128B (en) 2006-04-11
US20050064624A1 (en) 2005-03-24
EP1517369A2 (en) 2005-03-23
TW200522227A (en) 2005-07-01
MY139562A (en) 2009-10-30
SG157220A1 (en) 2009-12-29
KR20050028313A (ko) 2005-03-22
JP4360873B2 (ja) 2009-11-11
EP1517369A3 (en) 2010-10-13
US20080145973A1 (en) 2008-06-19

Similar Documents

Publication Publication Date Title
US7015069B2 (en) Method of manufacturing a semiconductor device and a semiconductor device
US8269323B2 (en) Integrated circuit package with etched leadframe for package-on-package interconnects
KR100430861B1 (ko) 배선기판, 반도체장치 및 패키지 스택 반도체장치
KR101332861B1 (ko) 아이씨 패키지 및 그 제조방법
US20070254406A1 (en) Method for manufacturing stacked package structure
US7482200B2 (en) Process for fabricating chip package structure
JP2009239256A (ja) 半導体装置及びその製造方法
US11437326B2 (en) Semiconductor package
US20070020812A1 (en) Circuit board structure integrated with semiconductor chip and method of fabricating the same
CN110459521B (zh) 覆晶封装基板和电子封装件
US20080145973A1 (en) Method of manufacturing wafer level chip size package
US7276800B2 (en) Carrying structure of electronic components
US6953709B2 (en) Semiconductor device and its manufacturing method
US7660130B2 (en) Semiconductor device
US20050077080A1 (en) Ball grid array (BGA) package having corner or edge tab supports
KR100475337B1 (ko) 고전력칩스케일패키지및그제조방법
US6348740B1 (en) Bump structure with dopants
KR100192758B1 (ko) 반도체패키지의 제조방법 및 구조
TW410411B (en) Chip scale package and its manufacturing method
KR100612761B1 (ko) 칩 스케일 적층 칩 패키지
US20020043702A1 (en) Semiconductor package comprising substrate with mounting leads and manufacturing method therefor
KR20000002999A (ko) 반도체 칩 패키지와 그 제조 방법
KR19980034131A (ko) 플립 칩 구조 형성 방법

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20120712

Year of fee payment: 6

LAPS Lapse due to unpaid annual fee