KR100698495B1 - 감소된 신호 처리 시간을 갖는 반도체 디바이스 및 그제조 방법 - Google Patents

감소된 신호 처리 시간을 갖는 반도체 디바이스 및 그제조 방법 Download PDF

Info

Publication number
KR100698495B1
KR100698495B1 KR1020027008757A KR20027008757A KR100698495B1 KR 100698495 B1 KR100698495 B1 KR 100698495B1 KR 1020027008757 A KR1020027008757 A KR 1020027008757A KR 20027008757 A KR20027008757 A KR 20027008757A KR 100698495 B1 KR100698495 B1 KR 100698495B1
Authority
KR
South Korea
Prior art keywords
layer
silicon
porous
porous material
conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1020027008757A
Other languages
English (en)
Korean (ko)
Other versions
KR20020065641A (ko
Inventor
호르스트맨맨프레드
위에크조렉카르스텐
버배쉬줘트
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20020065641A publication Critical patent/KR20020065641A/ko
Application granted granted Critical
Publication of KR100698495B1 publication Critical patent/KR100698495B1/ko
Assigned to 글로벌파운드리즈 인크. reassignment 글로벌파운드리즈 인크. 권리의 전부이전등록 Assignors: 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/072—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/097—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by thermally treating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/46—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising air gaps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020027008757A 2000-01-05 2000-07-31 감소된 신호 처리 시간을 갖는 반도체 디바이스 및 그제조 방법 Expired - Fee Related KR100698495B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/475,572 2000-01-05
US09/475,572 US6541863B1 (en) 2000-01-05 2000-01-05 Semiconductor device having a reduced signal processing time and a method of fabricating the same

Publications (2)

Publication Number Publication Date
KR20020065641A KR20020065641A (ko) 2002-08-13
KR100698495B1 true KR100698495B1 (ko) 2007-03-23

Family

ID=23888165

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020027008757A Expired - Fee Related KR100698495B1 (ko) 2000-01-05 2000-07-31 감소된 신호 처리 시간을 갖는 반도체 디바이스 및 그제조 방법

Country Status (6)

Country Link
US (1) US6541863B1 (https=)
EP (1) EP1245045B1 (https=)
JP (1) JP2003519924A (https=)
KR (1) KR100698495B1 (https=)
DE (1) DE60037599T2 (https=)
WO (1) WO2001050527A1 (https=)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100350111B1 (ko) * 2000-02-22 2002-08-23 삼성전자 주식회사 반도체 장치의 배선 및 이의 제조 방법
US6566242B1 (en) * 2001-03-23 2003-05-20 International Business Machines Corporation Dual damascene copper interconnect to a damascene tungsten wiring level
US6756620B2 (en) * 2001-06-29 2004-06-29 Intel Corporation Low-voltage and interface damage-free polymer memory device
US7294567B2 (en) * 2002-03-11 2007-11-13 Micron Technology, Inc. Semiconductor contact device and method
JP2004014815A (ja) * 2002-06-07 2004-01-15 Hitachi Ltd 半導体装置及びその製造方法
KR100416627B1 (ko) * 2002-06-18 2004-01-31 삼성전자주식회사 반도체 장치 및 그의 제조방법
US7382740B2 (en) * 2004-01-13 2008-06-03 Meshnetworks, Inc. System and method to perform smooth handoff of mobile terminals between fixed terminals in a network
US7709903B2 (en) * 2007-05-25 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. Contact barrier structure and manufacturing methods
US7834456B2 (en) * 2009-01-20 2010-11-16 Raytheon Company Electrical contacts for CMOS devices and III-V devices formed on a silicon substrate
US8633520B2 (en) 2010-10-21 2014-01-21 Samsung Electronics Co., Ltd. Semiconductor device
KR102733881B1 (ko) * 2016-09-12 2024-11-27 삼성전자주식회사 배선 구조체를 갖는 반도체 소자
KR102450580B1 (ko) * 2017-12-22 2022-10-07 삼성전자주식회사 금속 배선 하부의 절연층 구조를 갖는 반도체 장치
JP7531981B2 (ja) * 2019-07-18 2024-08-13 東京エレクトロン株式会社 領域選択的堆積における横方向のフィルム成長を緩和するための方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR890015370A (ko) * 1988-03-15 1989-10-30 세끼모또 다다히로 반도체 장치 및 그 제조방법

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4380865A (en) * 1981-11-13 1983-04-26 Bell Telephone Laboratories, Incorporated Method of forming dielectrically isolated silicon semiconductor materials utilizing porous silicon formation
US4628591A (en) * 1984-10-31 1986-12-16 Texas Instruments Incorporated Method for obtaining full oxide isolation of epitaxial islands in silicon utilizing selective oxidation of porous silicon
JPS63127551A (ja) * 1986-11-17 1988-05-31 Toshiba Corp 半導体装置の製造方法
US6017811A (en) * 1993-09-09 2000-01-25 The United States Of America As Represented By The Secretary Of The Navy Method of making improved electrical contact to porous silicon
EP0733269B1 (en) * 1993-12-06 2002-01-16 QinetiQ Limited Porous semiconductor material
US5494858A (en) * 1994-06-07 1996-02-27 Texas Instruments Incorporated Method for forming porous composites as a low dielectric constant layer with varying porosity distribution electronics applications
US5504042A (en) 1994-06-23 1996-04-02 Texas Instruments Incorporated Porous dielectric material with improved pore surface properties for electronics applications
JPH08125016A (ja) * 1994-10-24 1996-05-17 Sony Corp 半導体装置の製造方法
KR0147939B1 (ko) 1994-11-11 1998-09-15 배순훈 투사형 화상표시장치의 화소보정장치
US5691238A (en) 1995-06-07 1997-11-25 Advanced Micro Devices, Inc. Subtractive dual damascene
US5821621A (en) * 1995-10-12 1998-10-13 Texas Instruments Incorporated Low capacitance interconnect structure for integrated circuits
JP3378135B2 (ja) * 1996-02-02 2003-02-17 三菱電機株式会社 半導体装置とその製造方法
WO1998000862A1 (en) 1996-06-28 1998-01-08 Advanced Micro Devices, Inc. Solid porous insulated conductive lines
US5744865A (en) * 1996-10-22 1998-04-28 Texas Instruments Incorporated Highly thermally conductive interconnect structure for intergrated circuits
JP3123449B2 (ja) * 1996-11-01 2001-01-09 ヤマハ株式会社 多層配線形成法
KR100311880B1 (ko) * 1996-11-11 2001-12-20 미다라이 후지오 관통구멍의제작방법,관통구멍을갖는실리콘기판,이기판을이용한디바이스,잉크제트헤드의제조방법및잉크제트헤드
US6008540A (en) * 1997-05-28 1999-12-28 Texas Instruments Incorporated Integrated circuit dielectric and method
US6407441B1 (en) * 1997-12-29 2002-06-18 Texas Instruments Incorporated Integrated circuit and method of using porous silicon to achieve component isolation in radio frequency applications
JPH11312733A (ja) * 1998-04-28 1999-11-09 Nkk Corp 集積回路装置の製造方法
FR2779006B1 (fr) * 1998-05-19 2003-01-24 St Microelectronics Sa Procede de formation de silicium poreux dans un substrat de silicium, en particulier pour l'amelioration des performances d'un circuit inductif
US6376859B1 (en) * 1998-07-29 2002-04-23 Texas Instruments Incorporated Variable porosity porous silicon isolation
US6090724A (en) * 1998-12-15 2000-07-18 Lsi Logic Corporation Method for composing a thermally conductive thin film having a low dielectric property

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR890015370A (ko) * 1988-03-15 1989-10-30 세끼모또 다다히로 반도체 장치 및 그 제조방법

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
1019890015370 *

Also Published As

Publication number Publication date
DE60037599D1 (de) 2008-02-07
EP1245045A1 (en) 2002-10-02
EP1245045B1 (en) 2007-12-26
US6541863B1 (en) 2003-04-01
KR20020065641A (ko) 2002-08-13
DE60037599T2 (de) 2008-04-30
WO2001050527A1 (en) 2001-07-12
JP2003519924A (ja) 2003-06-24

Similar Documents

Publication Publication Date Title
US6268283B1 (en) Method for forming dual damascene structure
US10062645B2 (en) Interconnect structure for semiconductor devices
KR100698495B1 (ko) 감소된 신호 처리 시간을 갖는 반도체 디바이스 및 그제조 방법
US7189615B2 (en) Single mask MIM capacitor and resistor with in trench copper drift barrier
KR20010076367A (ko) 커패시터, 반도체 소자 및 커패시터 제조 방법
US20070040188A1 (en) Contact or via hole structure with enlarged bottom critical dimension
CN103811414A (zh) 铜蚀刻集成方法
US6680542B1 (en) Damascene structure having a metal-oxide-metal capacitor associated therewith
US20080012145A1 (en) Semiconductor Device and Method for Manufacturing the Same
US6593654B2 (en) Semiconductor device and method for manufacturing same
US6277705B1 (en) Method for fabricating an air-gap with a hard mask
CN106373920A (zh) 形成导电特征的方法
TW202029367A (zh) 半導體裝置的製造方法
US6265306B1 (en) Resist flow method for defining openings for conductive interconnections in a dielectric layer
US11158536B2 (en) Patterning line cuts before line patterning using sacrificial fill material
US20230099965A1 (en) Airgap isolation for back-end-of-the-line semiconductor interconnect structure with top via
US7112537B2 (en) Method of fabricating interconnection structure of semiconductor device
TWI878970B (zh) 整合式晶片及其形成的方法
KR0165379B1 (ko) 반도체 장치의 층간접속방법
KR100576513B1 (ko) 반도체 소자의 엠아이엠 캐패시터 제조방법
KR100485180B1 (ko) 반도체 소자의 제조 방법
TW202606024A (zh) 後段製程區域中之電阻及電容調控
KR100450241B1 (ko) 플러그 형성 방법 및 이 플러그를 갖는 반도체 소자
KR100595396B1 (ko) 반도체 소자의 배선 형성 방법
KR20040077042A (ko) 다마신 금속 배선 형성방법

Legal Events

Date Code Title Description
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R11-asn-PN2301

PN2301 Change of applicant

St.27 status event code: A-5-5-R10-R14-asn-PN2301

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 6

FPAY Annual fee payment

Payment date: 20130221

Year of fee payment: 7

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 7

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

FPAY Annual fee payment

Payment date: 20140220

Year of fee payment: 8

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 8

FPAY Annual fee payment

Payment date: 20150226

Year of fee payment: 9

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 9

FPAY Annual fee payment

Payment date: 20160218

Year of fee payment: 10

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 10

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20170316

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20170316

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-4-4-P10-P22-nap-X000