KR100680456B1 - 플래쉬 메모리 소자 및 그의 제조방법 - Google Patents
플래쉬 메모리 소자 및 그의 제조방법 Download PDFInfo
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- KR100680456B1 KR100680456B1 KR1020050057790A KR20050057790A KR100680456B1 KR 100680456 B1 KR100680456 B1 KR 100680456B1 KR 1020050057790 A KR1020050057790 A KR 1020050057790A KR 20050057790 A KR20050057790 A KR 20050057790A KR 100680456 B1 KR100680456 B1 KR 100680456B1
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- film
- polysilicon layer
- semiconductor substrate
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- oxide film
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- 238000000034 method Methods 0.000 title claims abstract description 34
- 239000010410 layer Substances 0.000 claims description 86
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 52
- 229920005591 polysilicon Polymers 0.000 claims description 52
- 238000002955 isolation Methods 0.000 claims description 34
- 239000004065 semiconductor Substances 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 22
- 239000011229 interlayer Substances 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- 238000005229 chemical vapour deposition Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims description 2
- 230000008021 deposition Effects 0.000 claims description 2
- 238000009832 plasma treatment Methods 0.000 claims description 2
- 230000000116 mitigating effect Effects 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 12
- 238000009826 distribution Methods 0.000 abstract description 8
- 230000015556 catabolic process Effects 0.000 abstract 1
- 238000006731 degradation reaction Methods 0.000 abstract 1
- 238000000206 photolithography Methods 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000002040 relaxant effect Effects 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
- H01L29/40114—Multistep manufacturing processes for data storage electrodes the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
Description
Claims (8)
- 필드 영역 및 액티브 영역이 정의된 반도체 기판;상기 필드 영역의 반도체 기판에 얕은 트렌치 분리 구조로 형성되는 소자분리막;상기 액티브 영역의 반도체 기판상의 터널 산화막;상기 터널 산화막상에 형성되며 상부보다 하부의 폭이 넓은 플로팅 게이트;상기 플로팅 게이트를 포함한 반도체 기판의 표면 단차를 따라서 형성된 층간유전막; 및상기 층간유전막상에 형성되는 컨트롤 게이트를 포함하여 구성되는 플래쉬 메모리 소자.
- 제 1항에 있어서,상기 플로팅 게이트는 상기 터널 산화막이 형성된 액티브 영역의 반도체 기판상에 형성되는 제 1 폴리실리콘층과 상기 제 1 폴리실리콘층상에 형성되며 상기 제 1 폴리실리콘층의 폭보다 좁은 폭을 갖는 제 2 폴리실리콘층의 적층막으로 구성됨을 특징으로 하는 플래쉬 메모리 소자.
- (a) 액티브 영역 및 필드 영역이 정의된 반도체 기판상에 터널 산화막과 제 1 폴리실리콘층과 희생 절연막을 형성하는 단계;(b) 상기 필드 영역의 희생 절연막과 제 1 폴리실리콘층과 터널 산화막과 반도체 기판을 식각하여 트렌치를 형성하고 상기 트렌치내에 소자분리막을 형성하는 단계;(c) 상기 희생 절연막을 제거하여 상기 소자분리막 상부 측면을 노출시키는 단계;(d) 상기 노출된 소자분리막 측면에 절연막 측벽을 형성하는 단계;(e) 상기 희생 절연막이 제거된 부분에 제 2 폴리실리콘층을 채우는 단계;(f) 상기 소자분리막과 절연막 측벽을 제거하여 상기 제 2 폴리실리콘층을 노출시키는 단계;(g) 상기 제 2 폴리실리콘층의 모서리 부분을 라운드시키고 제 2 폴리실리콘층이 갖는 네거티브 프로파일을 완화시키는 단계; 및(h) 전면에 층간유전막과 컨트롤 게이트를 차례로 형성하는 단계를 포함하는 플래쉬 메모리 소자의 제조방법.
- 제 3항에 있어서,상기 (g) 단계를 플라즈마 처리된 등방성 식각 공정을 이용하여 실시하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.
- 제 3항에 있어서,상기 희생 절연막을 질화막을 이용하여 형성하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.
- 제 3항에 있어서,상기 절연막 측벽을 실리콘 산화막이나 실리콘 질화막 중 어느 하나를 이용하여 형성하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.
- 제 6항에 있어서,상기 실리콘 산화막은 HTO(High Temperature Oxide), TEOS(Tetra Ethyl Ortho Silicate) 산화막, HLD(High temperature Low pressure Deposition) 산화막 중 어느 하나인 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.
- 제 6항에 있어서,상기 실리콘 산화막 및 실리콘 질화막을 저압 화학증착법, 상압 화학증착법, 플라즈마 응용 화학증착법 중 어느 하나를 사용하는 형성하는 것을 특징으로 하는 플래쉬 메모리 소자의 제조방법.
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050057790A KR100680456B1 (ko) | 2005-06-30 | 2005-06-30 | 플래쉬 메모리 소자 및 그의 제조방법 |
JP2005354650A JP2007013075A (ja) | 2005-06-30 | 2005-12-08 | フラッシュメモリ素子及びその製造方法 |
US11/297,917 US7316955B2 (en) | 2005-06-30 | 2005-12-09 | Method of manufacturing semiconductor device |
US11/942,227 US7696554B2 (en) | 2005-06-30 | 2007-11-19 | Flash memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1020050057790A KR100680456B1 (ko) | 2005-06-30 | 2005-06-30 | 플래쉬 메모리 소자 및 그의 제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR20070002312A KR20070002312A (ko) | 2007-01-05 |
KR100680456B1 true KR100680456B1 (ko) | 2007-02-08 |
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KR1020050057790A KR100680456B1 (ko) | 2005-06-30 | 2005-06-30 | 플래쉬 메모리 소자 및 그의 제조방법 |
Country Status (3)
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US (2) | US7316955B2 (ko) |
JP (1) | JP2007013075A (ko) |
KR (1) | KR100680456B1 (ko) |
Families Citing this family (18)
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JP2007180482A (ja) * | 2005-12-28 | 2007-07-12 | Hynix Semiconductor Inc | フラッシュメモリ素子の製造方法 |
US7667260B2 (en) | 2006-08-09 | 2010-02-23 | Micron Technology, Inc. | Nanoscale floating gate and methods of formation |
JP5091504B2 (ja) * | 2007-02-28 | 2012-12-05 | 株式会社東芝 | 半導体記憶装置 |
KR100897515B1 (ko) | 2007-03-14 | 2009-05-15 | 한국과학기술원 | 비휘발성 메모리 셀 및 그 제조방법. |
TWI343635B (en) * | 2007-10-02 | 2011-06-11 | Nanya Technology Corp | Method for manufacturing a memory |
KR100972862B1 (ko) * | 2008-04-07 | 2010-07-28 | 주식회사 하이닉스반도체 | 불휘발성 메모리 소자의 형성방법 |
US7915124B2 (en) * | 2008-07-09 | 2011-03-29 | Sandisk Corporation | Method of forming dielectric layer above floating gate for reducing leakage current |
US7919809B2 (en) * | 2008-07-09 | 2011-04-05 | Sandisk Corporation | Dielectric layer above floating gate for reducing leakage current |
US8871645B2 (en) | 2008-09-11 | 2014-10-28 | Applied Materials, Inc. | Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof |
US8207036B2 (en) * | 2008-09-30 | 2012-06-26 | Sandisk Technologies Inc. | Method for forming self-aligned dielectric cap above floating gate |
US8288293B2 (en) | 2009-04-20 | 2012-10-16 | Sandisk Technologies Inc. | Integrated circuit fabrication using sidewall nitridation processes |
KR101539404B1 (ko) * | 2010-01-08 | 2015-07-27 | 삼성전자주식회사 | 비휘발성 기억 소자 및 그 제조 방법 |
CN104766825B (zh) * | 2014-01-08 | 2018-01-05 | 中芯国际集成电路制造(上海)有限公司 | 一种增大flash器件栅电容的方法及flash器件 |
US9236389B1 (en) * | 2014-08-12 | 2016-01-12 | International Business Machines Corporation | Embedded flash memory fabricated in standard CMOS process with self-aligned contact |
CN105789133B (zh) * | 2014-12-24 | 2019-09-20 | 上海格易电子有限公司 | 一种闪存存储单元及制作方法 |
US20180173665A1 (en) * | 2016-12-16 | 2018-06-21 | Qualcomm Incorporated | Hard reset over i3c bus |
CN107887390B (zh) * | 2017-11-09 | 2020-06-16 | 上海华力微电子有限公司 | 一种改善闪存单元的工艺集成方法 |
CN111326519B (zh) * | 2020-03-10 | 2024-02-02 | 上海华力微电子有限公司 | 半导体的形成方法 |
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2005
- 2005-06-30 KR KR1020050057790A patent/KR100680456B1/ko active IP Right Grant
- 2005-12-08 JP JP2005354650A patent/JP2007013075A/ja active Pending
- 2005-12-09 US US11/297,917 patent/US7316955B2/en active Active
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2007
- 2007-11-19 US US11/942,227 patent/US7696554B2/en active Active
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Also Published As
Publication number | Publication date |
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JP2007013075A (ja) | 2007-01-18 |
KR20070002312A (ko) | 2007-01-05 |
US20070004137A1 (en) | 2007-01-04 |
US20080061353A1 (en) | 2008-03-13 |
US7696554B2 (en) | 2010-04-13 |
US7316955B2 (en) | 2008-01-08 |
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