KR100647483B1 - 반도체 패키지의 배선 구조물 및 이의 제조 방법, 이를이용한 웨이퍼 레벨 패키지 및 이의 제조 방법 - Google Patents

반도체 패키지의 배선 구조물 및 이의 제조 방법, 이를이용한 웨이퍼 레벨 패키지 및 이의 제조 방법 Download PDF

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KR100647483B1
KR100647483B1 KR1020050076286A KR20050076286A KR100647483B1 KR 100647483 B1 KR100647483 B1 KR 100647483B1 KR 1020050076286 A KR1020050076286 A KR 1020050076286A KR 20050076286 A KR20050076286 A KR 20050076286A KR 100647483 B1 KR100647483 B1 KR 100647483B1
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South Korea
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pattern
conductive
insulating
photoresist
conductive pattern
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Expired - Fee Related
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KR1020050076286A
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English (en)
Korean (ko)
Inventor
이인영
심성민
장동현
정현수
정재식
유승관
박명순
윤종국
최주일
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삼성전자주식회사
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Priority to KR1020050076286A priority Critical patent/KR100647483B1/ko
Priority to JP2006189426A priority patent/JP2007053346A/ja
Priority to US11/486,041 priority patent/US20070069320A1/en
Priority to DE102006037717A priority patent/DE102006037717A1/de
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Publication of KR100647483B1 publication Critical patent/KR100647483B1/ko
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1020050076286A 2005-08-19 2005-08-19 반도체 패키지의 배선 구조물 및 이의 제조 방법, 이를이용한 웨이퍼 레벨 패키지 및 이의 제조 방법 Expired - Fee Related KR100647483B1 (ko)

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KR1020050076286A KR100647483B1 (ko) 2005-08-19 2005-08-19 반도체 패키지의 배선 구조물 및 이의 제조 방법, 이를이용한 웨이퍼 레벨 패키지 및 이의 제조 방법
JP2006189426A JP2007053346A (ja) 2005-08-19 2006-07-10 半導体パッケージの配線構造物及びその製造方法、これを利用したウエハーレベルパッケージ及びその製造方法
US11/486,041 US20070069320A1 (en) 2005-08-19 2006-07-14 Wiring structure of a semiconductor package and method of manufacturing the same, and wafer level package having the wiring structure and method of manufacturing the same
DE102006037717A DE102006037717A1 (de) 2005-08-19 2006-08-07 Verdrahtungsstruktur, Waferebenenpackung und Herstellungsverfahren

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US20080265394A1 (en) * 2007-04-30 2008-10-30 Mtekvision Co., Ltd. Wafer level package and fabricating method thereof
WO2009013826A1 (ja) * 2007-07-25 2009-01-29 Fujitsu Microelectronics Limited 半導体装置
US7851244B2 (en) * 2008-02-11 2010-12-14 Honeywell International Inc. Methods for forming metal layers for a MEMS device integrated circuit
CN101419952B (zh) * 2008-12-03 2010-09-15 晶方半导体科技（苏州）有限公司 晶圆级芯片封装方法及封装结构
KR101060842B1 (ko) * 2010-01-07 2011-08-31 삼성전기주식회사 반도체 패키지의 제조 방법
US11690275B2 (en) * 2020-04-13 2023-06-27 Samsung Display Co., Ltd. Method of fabricating display device
US12362298B2 (en) * 2022-07-13 2025-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

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KR20010075962A (ko) * 2000-01-21 2001-08-11 오길록 재배열 금속배선기술을 적용한 패키징 제조방법

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KR100313706B1 (ko) * 1999-09-29 2001-11-26 윤종용 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
TW449813B (en) * 2000-10-13 2001-08-11 Advanced Semiconductor Eng Semiconductor device with bump electrode
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US6689680B2 (en) * 2001-07-14 2004-02-10 Motorola, Inc. Semiconductor device and method of formation
KR100447968B1 (ko) * 2001-08-07 2004-09-10 주식회사 하이닉스반도체 웨이퍼 레벨 패키지의 제조방법
KR100596452B1 (ko) * 2005-03-22 2006-07-04 삼성전자주식회사 볼 랜드와 솔더 볼 사이에 에어 갭을 갖는 웨이퍼 레벨 칩스케일 패키지와 그 제조 방법

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KR20010075962A (ko) * 2000-01-21 2001-08-11 오길록 재배열 금속배선기술을 적용한 패키징 제조방법

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