JP2007053346A - 半導体パッケージの配線構造物及びその製造方法、これを利用したウエハーレベルパッケージ及びその製造方法 - Google Patents

半導体パッケージの配線構造物及びその製造方法、これを利用したウエハーレベルパッケージ及びその製造方法 Download PDF

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JP2007053346A
JP2007053346A JP2006189426A JP2006189426A JP2007053346A JP 2007053346 A JP2007053346 A JP 2007053346A JP 2006189426 A JP2006189426 A JP 2006189426A JP 2006189426 A JP2006189426 A JP 2006189426A JP 2007053346 A JP2007053346 A JP 2007053346A
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pattern
conductive
insulating film
photoresist
insulating
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JP2007053346A5 (enExample
Inventor
In-Young Lee
仁 榮 李
Sung-Min Sim
成 ▲ビン▼ 沈
Dong-Hyeon Jang
東 鉉 張
Hyun-Soo Chung
顯 秀 鄭
Jae-Sik Chung
載 植 鄭
Seung-Kwan Ryu
承 官 柳
Myeong-Soon Park
明 洵 朴
Jong-Kook Yoon
鐘 國 尹
Ju-Il Choi
朱 逸 崔
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Publication of JP2007053346A publication Critical patent/JP2007053346A/ja
Publication of JP2007053346A5 publication Critical patent/JP2007053346A5/ja
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KR101060842B1 (ko) * 2010-01-07 2011-08-31 삼성전기주식회사 반도체 패키지의 제조 방법
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US12362298B2 (en) * 2022-07-13 2025-07-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture

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KR100313706B1 (ko) * 1999-09-29 2001-11-26 윤종용 재배치 웨이퍼 레벨 칩 사이즈 패키지 및 그 제조방법
KR100343454B1 (ko) * 1999-11-09 2002-07-11 박종섭 웨이퍼 레벨 패키지
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WO2009013826A1 (ja) * 2007-07-25 2009-01-29 Fujitsu Microelectronics Limited 半導体装置
KR101095409B1 (ko) 2007-07-25 2011-12-19 후지쯔 세미컨덕터 가부시키가이샤 반도체 장치
JP5387407B2 (ja) * 2007-07-25 2014-01-15 富士通セミコンダクター株式会社 半導体装置

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