KR100414839B1 - 적층형 반도체 장치 - Google Patents
적층형 반도체 장치 Download PDFInfo
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- KR100414839B1 KR100414839B1 KR10-2000-0062840A KR20000062840A KR100414839B1 KR 100414839 B1 KR100414839 B1 KR 100414839B1 KR 20000062840 A KR20000062840 A KR 20000062840A KR 100414839 B1 KR100414839 B1 KR 100414839B1
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- electrode
- semiconductor chip
- semiconductor
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H01L2224/05671—Chromium [Cr] as principal constituent
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
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- H—ELECTRICITY
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- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
Abstract
Description
Claims (4)
- 적층형 반도체 장치에 있어서,복수의 적층형 반도체 칩을 포함하고, 각각의 반도체 칩은 반도체 칩을 관통하여 형성되는 관통 전극, 상기 반도체 칩의 표면에 형성되는 제1 전극, 상기 반도체 칩의 이면에 형성되는 제2 전극을 포함하고,상기 반도체 칩의 표면과 이면에 형성되고, 상기 관통 전극을 통해 상기 제1 전극과 상기 제2 전극을 접속하는 배선 패턴을 선택적으로 포함하고,상기 복수의 반도체 칩 중 적어도 하나의 반도체 칩은 배선 패턴의 유무가 다른 반도체 칩과 다르게 구성되어 있는것을 특징으로 하는 적층형 반도체 장치.
- 제1항에 있어서, 상기 제1 및 제2 전극의 각각은 소정의 배열 패턴으로 배열된 복수의 전극을 포함하는 것을 특징으로 하는 적층형 반도체 장치.
- 제2항에 있어서, 상기 소정의 배열 패턴은 매트릭스 패턴인 것을 특징으로 하는 적층형 반도체 장치.
- 제1항에 있어서, 상기 제1 전극은 범프 전극이고, 상기 제2 전극은 패드 전극인 것을 특징으로 하는 적층형 반도체 장치.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30404099A JP2001127243A (ja) | 1999-10-26 | 1999-10-26 | 積層半導体装置 |
JP1999-304040 | 1999-10-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20010060208A KR20010060208A (ko) | 2001-07-06 |
KR100414839B1 true KR100414839B1 (ko) | 2004-01-13 |
Family
ID=17928338
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR10-2000-0062840A KR100414839B1 (ko) | 1999-10-26 | 2000-10-25 | 적층형 반도체 장치 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6362529B1 (ko) |
JP (1) | JP2001127243A (ko) |
KR (1) | KR100414839B1 (ko) |
DE (1) | DE10049551A1 (ko) |
TW (1) | TW473982B (ko) |
Families Citing this family (44)
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JP4251421B2 (ja) * | 2000-01-13 | 2009-04-08 | 新光電気工業株式会社 | 半導体装置の製造方法 |
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FR2969374B1 (fr) | 2010-12-16 | 2013-07-19 | St Microelectronics Crolles 2 | Procédé d'assemblage de deux circuits intégrés et structure correspondante |
CN115424980B (zh) * | 2022-11-04 | 2023-02-07 | 成都复锦功率半导体技术发展有限公司 | 一种芯片双面互连的堆叠封装方法 |
Citations (2)
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JPH10223833A (ja) * | 1996-12-02 | 1998-08-21 | Toshiba Corp | マルチチップ半導体装置、ならびにマルチチップ半導体装置用チップおよびその形成方法 |
EP0915516A2 (en) * | 1997-10-30 | 1999-05-12 | Nec Corporation | Substrate for stacked module and stacked module |
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Publication number | Priority date | Publication date | Assignee | Title |
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JPH0563137A (ja) | 1991-08-30 | 1993-03-12 | Fujitsu Ltd | 半導体装置 |
US6002177A (en) * | 1995-12-27 | 1999-12-14 | International Business Machines Corporation | High density integrated circuit packaging with chip stacking and via interconnections |
DE19918671B4 (de) | 1999-04-23 | 2006-03-02 | Giesecke & Devrient Gmbh | Vertikal integrierbare Schaltung und Verfahren zu ihrer Herstellung |
-
1999
- 1999-10-26 JP JP30404099A patent/JP2001127243A/ja active Pending
-
2000
- 2000-09-13 TW TW089118672A patent/TW473982B/zh not_active IP Right Cessation
- 2000-09-22 US US09/667,587 patent/US6362529B1/en not_active Expired - Lifetime
- 2000-10-06 DE DE10049551A patent/DE10049551A1/de not_active Withdrawn
- 2000-10-25 KR KR10-2000-0062840A patent/KR100414839B1/ko active IP Right Grant
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10223833A (ja) * | 1996-12-02 | 1998-08-21 | Toshiba Corp | マルチチップ半導体装置、ならびにマルチチップ半導体装置用チップおよびその形成方法 |
EP0915516A2 (en) * | 1997-10-30 | 1999-05-12 | Nec Corporation | Substrate for stacked module and stacked module |
Also Published As
Publication number | Publication date |
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JP2001127243A (ja) | 2001-05-11 |
US6362529B1 (en) | 2002-03-26 |
DE10049551A1 (de) | 2001-05-03 |
TW473982B (en) | 2002-01-21 |
KR20010060208A (ko) | 2001-07-06 |
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