KR100315977B1 - 반도체기억장치 - Google Patents

반도체기억장치 Download PDF

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Publication number
KR100315977B1
KR100315977B1 KR1019930017940A KR930017940A KR100315977B1 KR 100315977 B1 KR100315977 B1 KR 100315977B1 KR 1019930017940 A KR1019930017940 A KR 1019930017940A KR 930017940 A KR930017940 A KR 930017940A KR 100315977 B1 KR100315977 B1 KR 100315977B1
Authority
KR
South Korea
Prior art keywords
metal layer
word line
memory cell
sheet resistance
mosfet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
KR1019930017940A
Other languages
English (en)
Korean (ko)
Inventor
이시바시코이치로
사사키카츠로
코미야지쿠니히로
아오토도시로
모리타사다유키
Original Assignee
스즈키 진이치로
가부시키가이샤 히타치 쪼오 엘.에스.아이.시스템즈
가나이 쓰도무
가부시끼가이샤 히다치 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by 스즈키 진이치로, 가부시키가이샤 히타치 쪼오 엘.에스.아이.시스템즈, 가나이 쓰도무, 가부시끼가이샤 히다치 세이사꾸쇼 filed Critical 스즈키 진이치로
Application granted granted Critical
Publication of KR100315977B1 publication Critical patent/KR100315977B1/ko
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/418—Address circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/38—Response verification devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/14—Word line organisation; Word line lay-out
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
    • Y10S257/904—FET configuration adapted for use as static memory cell with passive components,, e.g. polysilicon resistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
KR1019930017940A 1992-09-10 1993-09-07 반도체기억장치 Expired - Lifetime KR100315977B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-241719 1992-09-10
JP24171992A JP3533227B2 (ja) 1992-09-10 1992-09-10 半導体記憶装置

Publications (1)

Publication Number Publication Date
KR100315977B1 true KR100315977B1 (ko) 2002-04-06

Family

ID=17078523

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930017940A Expired - Lifetime KR100315977B1 (ko) 1992-09-10 1993-09-07 반도체기억장치

Country Status (4)

Country Link
US (2) US5422839A (enExample)
JP (1) JP3533227B2 (enExample)
KR (1) KR100315977B1 (enExample)
TW (1) TW236024B (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3603229B2 (ja) * 1994-02-09 2004-12-22 富士通株式会社 半導体記憶装置
US5845059A (en) * 1996-01-19 1998-12-01 Stmicroelectronics, Inc. Data-input device for generating test signals on bit and bit-complement lines
US5883838A (en) * 1996-01-19 1999-03-16 Stmicroelectronics, Inc. Device and method for driving a conductive path with a signal
US5691950A (en) * 1996-01-19 1997-11-25 Sgs-Thomson Microelectronics, Inc. Device and method for isolating bit lines from a data line
US5802004A (en) * 1996-01-19 1998-09-01 Sgs-Thomson Microelectronics, Inc. Clocked sense amplifier with wordline tracking
JP3768608B2 (ja) * 1996-01-30 2006-04-19 株式会社日立製作所 半導体装置および半導体記憶装置
US5966388A (en) * 1997-01-06 1999-10-12 Micron Technology, Inc. High-speed test system for a memory device
JP3064967B2 (ja) * 1997-06-25 2000-07-12 日本電気株式会社 半導体集積回路装置
US6136686A (en) * 1997-07-18 2000-10-24 International Business Machines Corporation Fabrication of interconnects with two different thicknesses
JP3914618B2 (ja) * 1997-09-24 2007-05-16 エルピーダメモリ株式会社 半導体集積回路装置
US6016390A (en) * 1998-01-29 2000-01-18 Artisan Components, Inc. Method and apparatus for eliminating bitline voltage offsets in memory devices
JP3852729B2 (ja) * 1998-10-27 2006-12-06 富士通株式会社 半導体記憶装置
US6088287A (en) * 1999-08-23 2000-07-11 Advanced Micro Devices, Inc. Flash memory architecture employing three layer metal interconnect for word line decoding
US7276788B1 (en) 1999-08-25 2007-10-02 Micron Technology, Inc. Hydrophobic foamed insulators for high density circuits
US7335965B2 (en) 1999-08-25 2008-02-26 Micron Technology, Inc. Packaging of electronic chips with air-bridge structures
US6649456B1 (en) * 2002-10-16 2003-11-18 Taiwan Semiconductor Manufacturing Company SRAM cell design for soft error rate immunity
JP4970760B2 (ja) * 2004-09-15 2012-07-11 三星電子株式会社 半導体メモリ装置のライン配置構造
KR100641704B1 (ko) * 2004-10-30 2006-11-03 주식회사 하이닉스반도체 반도체 메모리 소자 및 그 비트라인 센스앰프 옵셋전압측정방법
KR100587692B1 (ko) * 2004-11-05 2006-06-08 삼성전자주식회사 반도체 메모리 장치에서의 회로 배선 배치구조와 그에따른 배치방법
US20250014614A1 (en) * 2023-07-07 2025-01-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor memory devices with flying bit lines and methods of manufacturing thereof

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63225991A (ja) * 1987-03-16 1988-09-20 Hitachi Ltd 半導体記憶装置
JPS63239862A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 半導体記憶装置
US5061980A (en) * 1983-07-27 1991-10-29 Hitachi, Ltd. Semiconductor integrated circuit device

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4402063A (en) * 1981-09-28 1983-08-30 Bell Telephone Laboratories, Incorporated Flip-flop detector array for minimum geometry semiconductor memory apparatus
KR900005667B1 (ko) * 1984-11-20 1990-08-03 후지쓰 가부시끼가이샤 반도체 기억장치
US4791616A (en) * 1985-07-10 1988-12-13 Fujitsu Limited Semiconductor memory device
JPH0642537B2 (ja) * 1985-11-15 1994-06-01 株式会社東芝 半導体装置
US5140550A (en) * 1987-03-16 1992-08-18 Hitachi Ltd. Semiconductor memory device
JP2569538B2 (ja) * 1987-03-17 1997-01-08 ソニー株式会社 メモリ装置
KR970003710B1 (ko) * 1987-09-04 1997-03-21 미다 가쓰시게 저잡음 반도체 메모리
JPH0821638B2 (ja) * 1989-12-15 1996-03-04 株式会社東芝 不揮発性半導体記憶装置およびその製造方法
US5228000A (en) * 1990-08-02 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Test circuit of semiconductor memory device
JP2782948B2 (ja) * 1990-11-16 1998-08-06 日本電気株式会社 半導体メモリ

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5061980A (en) * 1983-07-27 1991-10-29 Hitachi, Ltd. Semiconductor integrated circuit device
JPS63225991A (ja) * 1987-03-16 1988-09-20 Hitachi Ltd 半導体記憶装置
JPS63239862A (ja) * 1987-03-27 1988-10-05 Hitachi Ltd 半導体記憶装置

Also Published As

Publication number Publication date
US5422839A (en) 1995-06-06
US5677887A (en) 1997-10-14
JPH0697391A (ja) 1994-04-08
TW236024B (enExample) 1994-12-11
JP3533227B2 (ja) 2004-05-31

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