KR100306107B1 - Cpu와승산기를갖는반도체집적회로 - Google Patents

Cpu와승산기를갖는반도체집적회로 Download PDF

Info

Publication number
KR100306107B1
KR100306107B1 KR1019930023160A KR930023160A KR100306107B1 KR 100306107 B1 KR100306107 B1 KR 100306107B1 KR 1019930023160 A KR1019930023160 A KR 1019930023160A KR 930023160 A KR930023160 A KR 930023160A KR 100306107 B1 KR100306107 B1 KR 100306107B1
Authority
KR
South Korea
Prior art keywords
data
cpu
bus
command
multiplier
Prior art date
Application number
KR1019930023160A
Other languages
English (en)
Korean (ko)
Other versions
KR940012146A (ko
Inventor
기시가즈마사
마스무라시게끼
나까무라히데오
노구찌고끼
가와사끼순페이
아까오야스시
Original Assignee
스즈키 진이치로
히다치초엘에스아이 엔지니어링가부시키가이샤
가나이 쓰도무
가부시끼가이샤 히다치 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 스즈키 진이치로, 히다치초엘에스아이 엔지니어링가부시키가이샤, 가나이 쓰도무, 가부시끼가이샤 히다치 세이사꾸쇼 filed Critical 스즈키 진이치로
Publication of KR940012146A publication Critical patent/KR940012146A/ko
Application granted granted Critical
Publication of KR100306107B1 publication Critical patent/KR100306107B1/ko

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7864—Architectures of general purpose stored program computers comprising a single central processing unit with memory on more than one IC chip
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/325—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for loops, e.g. loop detection or loop counter
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Microcomputers (AREA)
KR1019930023160A 1992-11-06 1993-11-03 Cpu와승산기를갖는반도체집적회로 KR100306107B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-296778 1992-11-06
JP29677892A JP3231429B2 (ja) 1992-11-06 1992-11-06 中央処理装置と乗算器とを有する半導体集積回路装置

Publications (2)

Publication Number Publication Date
KR940012146A KR940012146A (ko) 1994-06-22
KR100306107B1 true KR100306107B1 (ko) 2001-11-30

Family

ID=17838015

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930023160A KR100306107B1 (ko) 1992-11-06 1993-11-03 Cpu와승산기를갖는반도체집적회로

Country Status (3)

Country Link
US (1) US5832248A (ja)
JP (1) JP3231429B2 (ja)
KR (1) KR100306107B1 (ja)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5867726A (en) * 1995-05-02 1999-02-02 Hitachi, Ltd. Microcomputer
JP3655403B2 (ja) * 1995-10-09 2005-06-02 株式会社ルネサステクノロジ データ処理装置
US6629207B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method for loading instructions or data into a locked way of a cache memory
US6530047B1 (en) 1999-10-01 2003-03-04 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6859891B2 (en) 1999-10-01 2005-02-22 Stmicroelectronics Limited Apparatus and method for shadowing processor information
US6826191B1 (en) 1999-10-01 2004-11-30 Stmicroelectronics Ltd. Packets containing transaction attributes
US6918065B1 (en) 1999-10-01 2005-07-12 Hitachi, Ltd. Method for compressing and decompressing trace information
US6693914B1 (en) 1999-10-01 2004-02-17 Stmicroelectronics, Inc. Arbitration mechanism for packet transmission
US6629115B1 (en) 1999-10-01 2003-09-30 Hitachi, Ltd. Method and apparatus for manipulating vectored data
US6590907B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics Ltd. Integrated circuit with additional ports
US6598177B1 (en) 1999-10-01 2003-07-22 Stmicroelectronics Ltd. Monitoring error conditions in an integrated circuit
US6351803B2 (en) 1999-10-01 2002-02-26 Hitachi Ltd. Mechanism for power efficient processing in a pipeline processor
US6779145B1 (en) 1999-10-01 2004-08-17 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6496905B1 (en) 1999-10-01 2002-12-17 Hitachi, Ltd. Write buffer with burst capability
US7793261B1 (en) 1999-10-01 2010-09-07 Stmicroelectronics Limited Interface for transferring debug information
US7266728B1 (en) 1999-10-01 2007-09-04 Stmicroelectronics Ltd. Circuit for monitoring information on an interconnect
JP2001142692A (ja) * 1999-10-01 2001-05-25 Hitachi Ltd ２つの異なる固定長命令セットを実行するマイクロプロセッサ、マイクロコンピュータおよび命令実行方法
US6684348B1 (en) 1999-10-01 2004-01-27 Hitachi, Ltd. Circuit for processing trace information
US6772325B1 (en) * 1999-10-01 2004-08-03 Hitachi, Ltd. Processor architecture and operation for exploiting improved branch control instruction
US6601189B1 (en) 1999-10-01 2003-07-29 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6349371B1 (en) 1999-10-01 2002-02-19 Stmicroelectronics Ltd. Circuit for storing information
US6633971B2 (en) 1999-10-01 2003-10-14 Hitachi, Ltd. Mechanism for forward data in a processor pipeline using a single pipefile connected to the pipeline
US6546480B1 (en) 1999-10-01 2003-04-08 Hitachi, Ltd. Instructions for arithmetic operations on vectored data
US6665816B1 (en) 1999-10-01 2003-12-16 Stmicroelectronics Limited Data shift register
US6591369B1 (en) 1999-10-01 2003-07-08 Stmicroelectronics, Ltd. System and method for communicating with an integrated circuit
US6701405B1 (en) 1999-10-01 2004-03-02 Hitachi, Ltd. DMA handshake protocol
US6567932B2 (en) 1999-10-01 2003-05-20 Stmicroelectronics Limited System and method for communicating with an integrated circuit
US6553460B1 (en) 1999-10-01 2003-04-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6487683B1 (en) 1999-10-01 2002-11-26 Stmicroelectronics Limited Microcomputer debug architecture and method
US7260745B1 (en) 1999-10-01 2007-08-21 Stmicroelectronics Ltd. Detection of information on an interconnect
US6557119B1 (en) 1999-10-01 2003-04-29 Stmicroelectronics Limited Microcomputer debug architecture and method
US6460174B1 (en) 1999-10-01 2002-10-01 Stmicroelectronics, Ltd. Methods and models for use in designing an integrated circuit
US6820195B1 (en) 1999-10-01 2004-11-16 Hitachi, Ltd. Aligning load/store data with big/little endian determined rotation distance control
US7000078B1 (en) * 1999-10-01 2006-02-14 Stmicroelectronics Ltd. System and method for maintaining cache coherency in a shared memory system
US6463553B1 (en) 1999-10-01 2002-10-08 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6542983B1 (en) 1999-10-01 2003-04-01 Hitachi, Ltd. Microcomputer/floating point processor interface and method
US6615370B1 (en) 1999-10-01 2003-09-02 Hitachi, Ltd. Circuit for storing trace information
US7072817B1 (en) 1999-10-01 2006-07-04 Stmicroelectronics Ltd. Method of designing an initiator in an integrated circuit
US6412047B2 (en) 1999-10-01 2002-06-25 Stmicroelectronics, Inc. Coherency protocol
US6502210B1 (en) 1999-10-01 2002-12-31 Stmicroelectronics, Ltd. Microcomputer debug architecture and method
US6434665B1 (en) 1999-10-01 2002-08-13 Stmicroelectronics, Inc. Cache memory store buffer
US6574651B1 (en) 1999-10-01 2003-06-03 Hitachi, Ltd. Method and apparatus for arithmetic operation on vectored data
US6298394B1 (en) 1999-10-01 2001-10-02 Stmicroelectronics, Ltd. System and method for capturing information on an interconnect in an integrated circuit
US6598128B1 (en) 1999-10-01 2003-07-22 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6449712B1 (en) 1999-10-01 2002-09-10 Hitachi, Ltd. Emulating execution of smaller fixed-length branch/delay slot instructions with a sequence of larger fixed-length instructions
US6412043B1 (en) 1999-10-01 2002-06-25 Hitachi, Ltd. Microprocessor having improved memory management unit and cache memory
US6732307B1 (en) 1999-10-01 2004-05-04 Hitachi, Ltd. Apparatus and method for storing trace information
US6457118B1 (en) 1999-10-01 2002-09-24 Hitachi Ltd Method and system for selecting and using source operands in computer system instructions
US6408381B1 (en) 1999-10-01 2002-06-18 Hitachi, Ltd. Mechanism for fast access to control space in a pipeline processor
US6928073B2 (en) * 1999-10-01 2005-08-09 Stmicroelectronics Ltd. Integrated circuit implementing packet transmission
KR102143339B1 (ko) 2019-07-17 2020-08-11 (유)다시 폐오일캔 압축장치

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63154927A (ja) * 1986-12-19 1988-06-28 Agency Of Ind Science & Technol 圧覚センサ出力信号前処理装置
JPH02186486A (ja) * 1982-02-11 1990-07-20 Texas Instr Inc <Ti> マイクロコンピュータ装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IT1082802B (it) * 1977-05-02 1985-05-21 Cselt Centro Studi Lab Telecom Unita microprogrammata per una apparecchiatura di terminazione di rete in trasmissione dati integrata con dispositivo di mo demodulazione e per la relativa apparecchiatura di centrale
NL8304186A (nl) * 1983-12-06 1985-07-01 Philips Nv Geintegreerde processor voor het verwerken van woordsgewijze ontvangbare informatie.
FI855180A (fi) * 1985-01-18 1986-07-19 Nissan Chemical Ind Ltd Pyrazolsulfonamidderivat, foerfarande foer dess framstaellande och det innehaollande ograesgift.
JPS62214464A (ja) * 1986-03-17 1987-09-21 Hitachi Ltd データ処理システム
US4876644A (en) * 1987-10-30 1989-10-24 International Business Machines Corp. Parallel pipelined processor
AU616213B2 (en) * 1987-11-09 1991-10-24 Tandem Computers Incorporated Method and apparatus for synchronizing a plurality of processors
US5056015A (en) * 1988-03-23 1991-10-08 Du Pont Pixel Systems Limited Architectures for serial or parallel loading of writable control store
US5086407A (en) * 1989-06-05 1992-02-04 Mcgarity Ralph C Data processor integrated circuit with selectable multiplexed/non-multiplexed address and data modes of operation
JPH03167649A (ja) * 1989-11-28 1991-07-19 Nec Corp ウエイト・サイクル制御装置

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02186486A (ja) * 1982-02-11 1990-07-20 Texas Instr Inc <Ti> マイクロコンピュータ装置
JPS63154927A (ja) * 1986-12-19 1988-06-28 Agency Of Ind Science & Technol 圧覚センサ出力信号前処理装置

Also Published As

Publication number Publication date
JP3231429B2 (ja) 2001-11-19
US5832248A (en) 1998-11-03
KR940012146A (ko) 1994-06-22
JPH06149545A (ja) 1994-05-27

Similar Documents

Publication Publication Date Title
KR100306107B1 (ko) Cpu와승산기를갖는반도체집적회로
US5604915A (en) Data processing system having load dependent bus timing
KR100276475B1 (ko) 마이크로 컴퓨터 시스템
US4228498A (en) Multibus processor for increasing execution speed using a pipeline effect
WO1994003860A1 (en) Massively parallel computer including auxiliary vector processor
EP0858039A2 (en) Microprocessor
US6154828A (en) Method and apparatus for employing a cycle bit parallel executing instructions
WO2004114128A2 (en) Instruction controlled data processing device
KR100288170B1 (ko) 레지스터 화일군을 공유하는 연산 유닛을 갖춘 데이타 처리기
JP2816624B2 (ja) ２乗演算を実行する速度改良型データ処理システム及びその方法
KR100210205B1 (ko) 스톨캐쉬를 제공하기 위한 장치 및 방법
US5838934A (en) Host port interface
US5909588A (en) Processor architecture with divisional signal in instruction decode for parallel storing of variable bit-width results in separate memory locations
US6327648B1 (en) Multiprocessor system for digital signal processing
US6948049B2 (en) Data processing system and control method
US4980821A (en) Stock-memory-based writable instruction set computer having a single data bus
US4975837A (en) Programmable unit having plural levels of subinstruction sets where a portion of the lower level is embedded in the code stream of the upper level of the subinstruction sets
JP3851008B2 (ja) プロセッサおよびそれを有する半導体集積回路、処理装置ならびに命令処理方法
JPH03129425A (ja) ビットフィールド論理演算処理装置およびそれを具備するモノリシックマイクロプロセッサ
JP3461887B2 (ja) 可変長パイプライン制御装置
JPH08194658A (ja) マイクロコンピュータシステム
Freeman Emulating peripheral chips using a RISC core
Farrell The CPU to System Connection
POWER et al. HIGH VOLUME HIGH PERFORMANCE
JPH0944472A (ja) 演算処理装置

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20080721

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee