KR100225189B1 - 반도체 메모리 - Google Patents

반도체 메모리

Info

Publication number
KR100225189B1
KR100225189B1 KR1019960061457A KR19960061457A KR100225189B1 KR 100225189 B1 KR100225189 B1 KR 100225189B1 KR 1019960061457 A KR1019960061457 A KR 1019960061457A KR 19960061457 A KR19960061457 A KR 19960061457A KR 100225189 B1 KR100225189 B1 KR 100225189B1
Authority
KR
South Korea
Prior art keywords
data
output
signal
input
reference clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019960061457A
Other languages
English (en)
Korean (ko)
Other versions
KR970029843A (ko
Inventor
마모루 후지따
Original Assignee
가네꼬 히사시
닛본 덴기 가부시끼가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=18014761&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=KR100225189(B1) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by 가네꼬 히사시, 닛본 덴기 가부시끼가이샤 filed Critical 가네꼬 히사시
Publication of KR970029843A publication Critical patent/KR970029843A/ko
Application granted granted Critical
Publication of KR100225189B1 publication Critical patent/KR100225189B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
KR1019960061457A 1995-11-29 1996-11-29 반도체 메모리 Expired - Fee Related KR100225189B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP95-311238 1995-11-29
JP7311238A JP2817685B2 (ja) 1995-11-29 1995-11-29 半導体メモリ

Publications (2)

Publication Number Publication Date
KR970029843A KR970029843A (ko) 1997-06-26
KR100225189B1 true KR100225189B1 (ko) 1999-10-15

Family

ID=18014761

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960061457A Expired - Fee Related KR100225189B1 (ko) 1995-11-29 1996-11-29 반도체 메모리

Country Status (4)

Country Link
US (1) US5805504A (enExample)
JP (1) JP2817685B2 (enExample)
KR (1) KR100225189B1 (enExample)
TW (1) TW314626B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE39579E1 (en) * 1997-04-04 2007-04-17 Renesas Technology Corp. Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system
JP3001475B2 (ja) * 1997-08-28 2000-01-24 日本電気アイシーマイコンシステム株式会社 半導体記憶装置
US6078987A (en) * 1997-09-30 2000-06-20 Sun Microsystems, Inc. Translation look aside buffer having separate RAM arrays which are accessable with separate enable signals
JPH11203860A (ja) 1998-01-07 1999-07-30 Nec Corp 半導体記憶装置
DE19964449B4 (de) * 1998-06-30 2013-01-31 Fujitsu Semiconductor Ltd. Integrierte Halbleiterschaltung
JP4756724B2 (ja) 2000-02-24 2011-08-24 エルピーダメモリ株式会社 半導体記憶装置
KR100496857B1 (ko) * 2002-05-17 2005-06-22 삼성전자주식회사 외부적으로 데이터 로드 신호를 갖는 반도체 메모리 장치및 이 반도체 메모리 장치의 직렬 데이터의 병렬데이터로의 프리패치 방법
KR100582411B1 (ko) * 2003-10-31 2006-05-22 주식회사 하이닉스반도체 출력되는 데이터의 스큐 및 타이밍 에러를 방지할 수 있는반도체 메모리 장치
US7558933B2 (en) * 2003-12-24 2009-07-07 Ati Technologies Inc. Synchronous dynamic random access memory interface and method
KR101510452B1 (ko) * 2008-06-11 2015-04-10 삼성전자주식회사 그래픽 메모리의 데이터 라이트 제어 방법 및 그 장치
US10395753B2 (en) * 2014-08-28 2019-08-27 Winbond Electronics Corp. Semiconductor memory device and programming method thereof

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4683555A (en) * 1985-01-22 1987-07-28 Texas Instruments Incorporated Serial accessed semiconductor memory with reconfigureable shift registers
JPS63250149A (ja) * 1987-04-07 1988-10-18 Mitsubishi Electric Corp 半導体装置
US5222047A (en) * 1987-05-15 1993-06-22 Mitsubishi Denki Kabushiki Kaisha Method and apparatus for driving word line in block access memory
JPH04176089A (ja) * 1990-11-08 1992-06-23 Nec Corp メモリ装置
JPH04326138A (ja) * 1991-04-25 1992-11-16 Fujitsu Ltd 高速メモリｉｃ
US5384745A (en) * 1992-04-27 1995-01-24 Mitsubishi Denki Kabushiki Kaisha Synchronous semiconductor memory device
JPH0636560A (ja) * 1992-07-21 1994-02-10 Mitsubishi Electric Corp 半導体記憶装置
US5617555A (en) * 1995-11-30 1997-04-01 Alliance Semiconductor Corporation Burst random access memory employing sequenced banks of local tri-state drivers

Also Published As

Publication number Publication date
TW314626B (enExample) 1997-09-01
JPH09153278A (ja) 1997-06-10
KR970029843A (ko) 1997-06-26
US5805504A (en) 1998-09-08
JP2817685B2 (ja) 1998-10-30

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