KR100207967B1 - 출력버퍼회로 - Google Patents

출력버퍼회로 Download PDF

Info

Publication number
KR100207967B1
KR100207967B1 KR1019960034309A KR19960034309A KR100207967B1 KR 100207967 B1 KR100207967 B1 KR 100207967B1 KR 1019960034309 A KR1019960034309 A KR 1019960034309A KR 19960034309 A KR19960034309 A KR 19960034309A KR 100207967 B1 KR100207967 B1 KR 100207967B1
Authority
KR
South Korea
Prior art keywords
mos transistor
gate
type
signal
channel mos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019960034309A
Other languages
English (en)
Korean (ko)
Other versions
KR970013653A (ko
Inventor
마코토 다카하시
가즈타카 노가미
Original Assignee
니시무로 타이죠
가부시끼가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 니시무로 타이죠, 가부시끼가이샤 도시바 filed Critical 니시무로 타이죠
Publication of KR970013653A publication Critical patent/KR970013653A/ko
Application granted granted Critical
Publication of KR100207967B1 publication Critical patent/KR100207967B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
KR1019960034309A 1995-08-22 1996-08-20 출력버퍼회로 Expired - Fee Related KR100207967B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP95-213464 1995-08-22
JP21346495A JP3190233B2 (ja) 1995-08-22 1995-08-22 出力バッファ回路

Publications (2)

Publication Number Publication Date
KR970013653A KR970013653A (ko) 1997-03-29
KR100207967B1 true KR100207967B1 (ko) 1999-07-15

Family

ID=16639646

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019960034309A Expired - Fee Related KR100207967B1 (ko) 1995-08-22 1996-08-20 출력버퍼회로

Country Status (4)

Country Link
US (1) US5748011A (enExample)
JP (1) JP3190233B2 (enExample)
KR (1) KR100207967B1 (enExample)
TW (1) TW321804B (enExample)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118302A (en) * 1996-05-28 2000-09-12 Altera Corporation Interface for low-voltage semiconductor devices
US5864243A (en) * 1996-09-18 1999-01-26 Vlsi Technology, Inc. Buffer and method for transferring data therein
KR100242987B1 (ko) * 1996-11-27 2000-02-01 김영환 5v 톨러런트 입출력 회로
JPH10285013A (ja) * 1997-04-08 1998-10-23 Mitsubishi Electric Corp 出力バッファ回路
US5969541A (en) * 1997-05-19 1999-10-19 Stmicroelectronics, Inc. Current inhibiting I/O buffer having a 5 volt tolerant input and method of inhibiting current
US6150843A (en) * 1998-01-29 2000-11-21 Vlsi Technology, Inc. Five volt tolerant I/O buffer
TW386321B (en) * 1998-04-14 2000-04-01 Via Tech Inc I/O buffer capable of withstanding input voltage higher than power voltage
TW511335B (en) 1998-06-09 2002-11-21 Mitsubishi Electric Corp Integrated circuit
US6144221A (en) * 1998-07-02 2000-11-07 Seiko Epson Corporation Voltage tolerant interface circuit
US6545506B1 (en) * 1999-03-12 2003-04-08 Silable, Inc. CMOS output driver that can tolerant a high input voltage
KR100306877B1 (ko) * 1999-06-30 2001-11-01 박종섭 전압 특성을 개선한 반도체집적회로의 입출력버퍼
JP4303387B2 (ja) * 2000-02-09 2009-07-29 株式会社ルネサステクノロジ 半導体集積回路
US6384632B2 (en) * 2000-02-22 2002-05-07 Yamaha Corporation Buffer circuit
US6208178B1 (en) 2000-02-23 2001-03-27 Pericom Semiconductor Corp. CMOS over voltage-tolerant output buffer without transmission gate
US6329835B1 (en) 2000-02-23 2001-12-11 Pericom Semiconductor Corp. Quiet output buffers with neighbor sensing of wide bus and control signals
US7199612B2 (en) * 2002-08-12 2007-04-03 Broadcom Corporation Method and circuit for reducing HCI stress
JP3759121B2 (ja) 2003-04-25 2006-03-22 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4054727B2 (ja) * 2003-07-14 2008-03-05 株式会社リコー 出力バッファ回路及び出力バッファ回路を使用したインタフェース回路
JP2006311201A (ja) * 2005-04-28 2006-11-09 Nec Electronics Corp バッファ回路
US7859305B2 (en) 2006-08-07 2010-12-28 Fujitsu Semiconductor Limited Input/output circuit
JP5266974B2 (ja) * 2008-02-06 2013-08-21 富士通セミコンダクター株式会社 入出力回路
JP4882584B2 (ja) * 2006-08-07 2012-02-22 富士通セミコンダクター株式会社 入出力回路
JP4726881B2 (ja) * 2007-11-12 2011-07-20 株式会社リコー 出力バッファ回路及び出力バッファ回路を使用したインタフェース回路
CN104660248B (zh) * 2013-11-19 2018-06-01 中芯国际集成电路制造(上海)有限公司 上拉电阻电路

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1375958A (en) * 1972-06-29 1974-12-04 Ibm Pulse circuit
US4709162A (en) * 1986-09-18 1987-11-24 International Business Machines Corporation Off-chip driver circuits
US4782250A (en) * 1987-08-31 1988-11-01 International Business Machines Corporation CMOS off-chip driver circuits
US4963766A (en) * 1989-06-28 1990-10-16 Digital Equipment Corporation Low-voltage CMOS output buffer
US5151619A (en) * 1990-10-11 1992-09-29 International Business Machines Corporation Cmos off chip driver circuit
US5144165A (en) * 1990-12-14 1992-09-01 International Business Machines Corporation CMOS off-chip driver circuits
US5206544A (en) * 1991-04-08 1993-04-27 International Business Machines Corporation CMOS off-chip driver with reduced signal swing and reduced power supply disturbance
US5387826A (en) * 1993-02-10 1995-02-07 National Semiconductor Corporation Overvoltage protection against charge leakage in an output driver
US5406140A (en) * 1993-06-07 1995-04-11 National Semiconductor Corporation Voltage translation and overvoltage protection
US5418476A (en) * 1994-07-28 1995-05-23 At&T Corp. Low voltage output buffer with improved speed
US5576635A (en) * 1995-02-14 1996-11-19 Advanced Micro Devices, Inc. Output buffer with improved tolerance to overvoltage
US5629634A (en) * 1995-08-21 1997-05-13 International Business Machines Corporation Low-power, tristate, off-chip driver circuit

Also Published As

Publication number Publication date
JP3190233B2 (ja) 2001-07-23
US5748011A (en) 1998-05-05
TW321804B (enExample) 1997-12-01
KR970013653A (ko) 1997-03-29
JPH0964718A (ja) 1997-03-07

Similar Documents

Publication Publication Date Title
KR100207967B1 (ko) 출력버퍼회로
US5880602A (en) Input and output buffer circuit
US6130556A (en) Integrated circuit I/O buffer with 5V well and passive gate voltage
US5900741A (en) CMOS buffer having stable threshold voltage
JP2002135107A (ja) レベル変換回路および半導体集積回路
US6285209B1 (en) Interface circuit and input buffer integrated circuit including the same
US20030001629A1 (en) Signal transmission circuit capable of tolerating high-voltage input signal
US11979155B2 (en) Semiconductor integrated circuit device and level shifter circuit
US6118303A (en) Integrated circuit I/O buffer having pass gate protection with RC delay
KR100211758B1 (ko) 멀티 파워를 사용하는 데이터 출력버퍼
EP0848498B1 (en) Output driver circuit in semiconductor device
JP4089704B2 (ja) 半導体集積回路
US12341498B2 (en) Bidirectional signal conversion circuit
US7477075B2 (en) CMOS output driver using floating wells to prevent leakage current
US6838908B2 (en) Mixed-voltage I/O design with novel floating N-well and gate-tracking circuits
US7038504B2 (en) Output buffer circuit eliminating high voltage insulated transistor and level shift circuit, and an interface circuit using the output buffer circuit
KR0145851B1 (ko) 반도체 메모리 장치의 전압 변환회로
JPH04329024A (ja) 入出力バッファ回路
CN117833906A (zh) 电平转换电路
JP7396774B2 (ja) 論理回路
KR100845106B1 (ko) 전압레벨 변경회로
Chen et al. A new output buffer for 3.3-V PCI-X application in a 0.13-/spl mu/m 1/2.5-V CMOS process
US6580290B1 (en) Open collector/drain and SSTL compliant output driver circuit and method for operating the circuit
CN118554939A (zh) 具有高压保护电路的输出驱动器
KR0137603B1 (ko) 3v/5v 데이타 입력 가능한 입.출력 버퍼

Legal Events

Date Code Title Description
A201 Request for examination
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

PN2301 Change of applicant

St.27 status event code: A-3-3-R10-R13-asn-PN2301

St.27 status event code: A-3-3-R10-R11-asn-PN2301

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

R18-X000 Changes to party contact information recorded

St.27 status event code: A-3-3-R10-R18-oth-X000

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U11-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

FPAY Annual fee payment

Payment date: 20030401

Year of fee payment: 5

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 5

LAPS Lapse due to unpaid annual fee
PC1903 Unpaid annual fee

St.27 status event code: A-4-4-U10-U13-oth-PC1903

Not in force date: 20040415

Payment event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

PC1903 Unpaid annual fee

St.27 status event code: N-4-6-H10-H13-oth-PC1903

Ip right cessation event data comment text: Termination Category : DEFAULT_OF_REGISTRATION_FEE

Not in force date: 20040415

R18-X000 Changes to party contact information recorded

St.27 status event code: A-5-5-R10-R18-oth-X000