JPWO2024247025A5 - - Google Patents
Download PDFInfo
- Publication number
- JPWO2024247025A5 JPWO2024247025A5 JP2023556766A JP2023556766A JPWO2024247025A5 JP WO2024247025 A5 JPWO2024247025 A5 JP WO2024247025A5 JP 2023556766 A JP2023556766 A JP 2023556766A JP 2023556766 A JP2023556766 A JP 2023556766A JP WO2024247025 A5 JPWO2024247025 A5 JP WO2024247025A5
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- plating layer
- recess
- semiconductor device
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2023/019866 WO2024247025A1 (ja) | 2023-05-29 | 2023-05-29 | 半導体装置および半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP7378693B1 JP7378693B1 (ja) | 2023-11-13 |
| JPWO2024247025A1 JPWO2024247025A1 (https=) | 2024-12-05 |
| JPWO2024247025A5 true JPWO2024247025A5 (https=) | 2025-05-13 |
Family
ID=88729163
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023556766A Active JP7378693B1 (ja) | 2023-05-29 | 2023-05-29 | 半導体装置および半導体装置の製造方法 |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP7378693B1 (https=) |
| CN (1) | CN121219834A (https=) |
| WO (1) | WO2024247025A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2025109755A1 (ja) * | 2023-11-24 | 2025-05-30 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
| CN121076034B (zh) * | 2025-11-04 | 2026-03-10 | 深圳市联合蓝海应用材料科技股份有限公司 | 一种化合物半导体背孔器件及其制备方法和晶体管 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02214127A (ja) * | 1989-02-15 | 1990-08-27 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
| JP2803408B2 (ja) * | 1991-10-03 | 1998-09-24 | 三菱電機株式会社 | 半導体装置 |
| TWI504780B (zh) * | 2009-09-04 | 2015-10-21 | 穩懋半導體股份有限公司 | 一種利用無電解電鍍法將金屬種子層鍍在半導體晶片的背面及導孔的製程方法 |
| JP5725073B2 (ja) * | 2012-10-30 | 2015-05-27 | 三菱電機株式会社 | 半導体素子の製造方法、半導体素子 |
| JP2022070436A (ja) * | 2020-10-27 | 2022-05-13 | 富士通株式会社 | 半導体装置及びその製造方法 |
-
2023
- 2023-05-29 JP JP2023556766A patent/JP7378693B1/ja active Active
- 2023-05-29 WO PCT/JP2023/019866 patent/WO2024247025A1/ja not_active Ceased
- 2023-05-29 CN CN202380098296.2A patent/CN121219834A/zh active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPWO2024247025A5 (https=) | ||
| KR102335506B1 (ko) | 쓰루 실리콘 비아 금속화 | |
| US20220238451A1 (en) | Cobalt based interconnects and methods of fabrication thereof | |
| US6787468B2 (en) | Method of fabricating metal lines in a semiconductor device | |
| US7750487B2 (en) | Metal-metal bonding of compliant interconnect | |
| CN105393345B (zh) | 金属无pvd传导结构 | |
| CN100350604C (zh) | 具有双覆盖层的半导体器件的互连及其制造方法 | |
| US20080020230A1 (en) | Copper Alloy Via Bottom Liner | |
| TW200707640A (en) | Contact metallization scheme using a barrier layer over a silicide layer | |
| US6998342B2 (en) | Electronic device manufacturing method | |
| US20130256876A1 (en) | Semiconductor package | |
| JP2009231497A (ja) | 半導体装置及び半導体装置の製造方法 | |
| US7951714B2 (en) | High aspect ratio electroplated metal feature and method | |
| JPH03220751A (ja) | インターレベル・コンタクトを製造する方法、および半導体構造 | |
| US9865812B2 (en) | Methods of forming conductive elements of semiconductor devices and of forming memory cells | |
| TW201642364A (zh) | 半導體裝置及半導體裝置之製造方法 | |
| TWI552339B (zh) | 半導體裝置、半導體裝置的製造方法 | |
| JP2025503627A5 (https=) | ||
| CN111105990B (zh) | 一种适用于铜金属化半导体器件的薄膜结构及其制备方法 | |
| CN100530565C (zh) | 半导体器件及其制造方法 | |
| US6674171B2 (en) | Semiconductor device with a low resistance wiring | |
| JP2001274160A (ja) | 半導体装置およびその製造方法 | |
| JP3518470B2 (ja) | 半導体装置の製造方法 | |
| CN113823613A (zh) | 半导体器件和半导体器件的制备方法 | |
| KR100267104B1 (ko) | 다층확산방지막을이용한반도체장치의콘택형성방법 |