JP2025503627A5 - - Google Patents
Info
- Publication number
- JP2025503627A5 JP2025503627A5 JP2024541057A JP2024541057A JP2025503627A5 JP 2025503627 A5 JP2025503627 A5 JP 2025503627A5 JP 2024541057 A JP2024541057 A JP 2024541057A JP 2024541057 A JP2024541057 A JP 2024541057A JP 2025503627 A5 JP2025503627 A5 JP 2025503627A5
- Authority
- JP
- Japan
- Prior art keywords
- metal layer
- layer
- interconnection structure
- structure according
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/573,461 US20230223341A1 (en) | 2022-01-11 | 2022-01-11 | Low via resistance interconnect structure |
| US17/573,461 | 2022-01-11 | ||
| PCT/US2022/053521 WO2023136914A1 (en) | 2022-01-11 | 2022-12-20 | Low via resistance interconnect structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2025503627A JP2025503627A (ja) | 2025-02-04 |
| JP2025503627A5 true JP2025503627A5 (https=) | 2025-12-16 |
Family
ID=85199417
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2024541057A Pending JP2025503627A (ja) | 2022-01-11 | 2022-12-20 | 低ビア抵抗相互接続構造体 |
Country Status (7)
| Country | Link |
|---|---|
| US (1) | US20230223341A1 (https=) |
| EP (1) | EP4463887A1 (https=) |
| JP (1) | JP2025503627A (https=) |
| KR (1) | KR20240134304A (https=) |
| CN (1) | CN118369757A (https=) |
| TW (1) | TW202335230A (https=) |
| WO (1) | WO2023136914A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12308291B2 (en) | 2022-06-03 | 2025-05-20 | Nanya Technology Corporation | Method for preparing semiconductor device structure with barrier portion |
| US12308318B2 (en) * | 2022-06-03 | 2025-05-20 | Nanya Technology Corporation | Semiconductor device structure with barrier portion |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1020543A1 (en) * | 1999-01-15 | 2000-07-19 | Interuniversitair Micro-Elektronica Centrum Vzw | Deposition of copper on an activated surface of a substrate |
| US20030148618A1 (en) * | 2002-02-07 | 2003-08-07 | Applied Materials, Inc. | Selective metal passivated copper interconnect with zero etch stops |
| JP4647184B2 (ja) * | 2002-12-27 | 2011-03-09 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
| US20070057305A1 (en) * | 2005-09-13 | 2007-03-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | MIM capacitor integrated into the damascene structure and method of making thereof |
| US20070249156A1 (en) * | 2006-04-20 | 2007-10-25 | Griselda Bonilla | Method for enabling hard mask free integration of ultra low-k materials and structures produced thereby |
| US7651943B2 (en) * | 2008-02-18 | 2010-01-26 | Taiwan Semicondcutor Manufacturing Company, Ltd. | Forming diffusion barriers by annealing copper alloy layers |
| US9514983B2 (en) * | 2012-12-28 | 2016-12-06 | Intel Corporation | Cobalt based interconnects and methods of fabrication thereof |
| US9059217B2 (en) * | 2013-03-28 | 2015-06-16 | International Business Machines Corporation | FET semiconductor device with low resistance and enhanced metal fill |
| EP3503168A1 (en) * | 2014-12-23 | 2019-06-26 | INTEL Corporation | Decoupled via fill |
| US9842805B2 (en) * | 2015-09-24 | 2017-12-12 | International Business Machines Corporation | Drive-in Mn before copper plating |
| US10002789B2 (en) * | 2016-03-24 | 2018-06-19 | International Business Machines Corporation | High performance middle of line interconnects |
| US10361364B2 (en) * | 2017-06-14 | 2019-07-23 | International Business Machines Corporation | Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size |
| TW202524711A (zh) * | 2017-11-30 | 2025-06-16 | 美商英特爾股份有限公司 | 用於先進積體電路結構製造之異質金屬線組成 |
| KR20250070116A (ko) * | 2017-11-30 | 2025-05-20 | 인텔 코포레이션 | 진보된 집적 회로 구조체 제조를 위한 핀 패터닝 |
| US10395986B1 (en) * | 2018-05-30 | 2019-08-27 | International Business Machines Corporation | Fully aligned via employing selective metal deposition |
| US10629484B1 (en) * | 2018-11-01 | 2020-04-21 | Applied Materials, Inc. | Method of forming self-aligned via |
| US10957579B2 (en) * | 2018-11-06 | 2021-03-23 | Samsung Electronics Co., Ltd. | Integrated circuit devices including a via and methods of forming the same |
| US11164778B2 (en) * | 2019-11-25 | 2021-11-02 | International Business Machines Corporation | Barrier-free vertical interconnect structure |
| US11515203B2 (en) * | 2020-02-05 | 2022-11-29 | Tokyo Electron Limited | Selective deposition of conductive cap for fully-aligned-via (FAV) |
| US11362035B2 (en) * | 2020-03-10 | 2022-06-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Diffusion barrier layer for conductive via to decrease contact resistance |
| US11289375B2 (en) * | 2020-03-23 | 2022-03-29 | International Business Machines Corporation | Fully aligned interconnects with selective area deposition |
-
2022
- 2022-01-11 US US17/573,461 patent/US20230223341A1/en active Pending
- 2022-12-20 WO PCT/US2022/053521 patent/WO2023136914A1/en not_active Ceased
- 2022-12-20 JP JP2024541057A patent/JP2025503627A/ja active Pending
- 2022-12-20 EP EP22854546.3A patent/EP4463887A1/en active Pending
- 2022-12-20 CN CN202280081933.0A patent/CN118369757A/zh active Pending
- 2022-12-20 TW TW111149010A patent/TW202335230A/zh unknown
- 2022-12-20 KR KR1020247021909A patent/KR20240134304A/ko active Pending
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