Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/425—Barrier, adhesion or liner layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
  • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
  • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
  • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
  • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
  • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
  • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
  • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/42—Vias, e.g. via plugs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
  • H10W20/435—Cross-sectional shapes or dispositions of interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
  • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
  • H10W20/48—Insulating materials thereof
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
  • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
  • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
  • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
  • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
  • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
  • H10P14/44—Physical vapour deposition [PVD]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/071—Manufacture or treatment of dielectric parts thereof
  • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
  • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures

Definitions

• Certain aspects of the present disclosure generally relate to interconnects, and more particularly, to an interconnect structure comprising a low via resistance via structure.
• IC may include an active semiconductor layer fabricated in a front-end-of-line process.
• the active semiconductor layer may contain various semiconductor devices.
• IC may also include an interconnect structure formed adjacent to the active semiconductor layer through a back-end-of-line process.
• the interconnect structure may contain multiple metallization layers each with metal lines disposed in a respective metallization layer to provide connections between different semiconductor devices and external interconnects.
• Vertical interconnect accesses vias may be disposed between metallization layers to provide connections for the different metallization layers.
• the interconnect structure may include a via structure, the via structure comprising a barrier layer on sidewalls and at bottom of the via structure.
• the interconnect structure may also include a first metal layer.
• the interconnect structure may further include a second metal layer between the barrier layer at the bottom of the via structure and the first metal layer, wherein the first metal layer and the second metal layer comprise different materials.
• Certain aspects of the present disclosure provide a method for fabricating an interconnect structure of a semiconductor device.
• the method may include forming a via opening on a first metal layer.
• the method may also include forming a second metal layer at bottom of the via opening.
• the first metal layer and the second metal layer comprise different materials.
• the method may also include forming a barrier layer on sidewalls and at the bottom of the via opening, wherein the second metal layer is between the barrier layer at the bottom of the via opening and the first metal layer.
• the method may further include depositing metal in the via opening.
• Figure 1 illustrates an exemplary interconnect structure of a semiconductor device comprising a first metal layer and a second metal layer connected by a via structure with low via resistance in accordance with certain aspects of the present disclosure
• Figures 2A-2B illustrate an exemplary fabrication process for the interconnect structure 100 in Figure 1 in accordance with certain aspects of the present disclosure
• Figure 3 shows a flow chart illustrating an exemplary fabrication process for the interconnect structure 100 in Figure 1;
• Figure 4 is a block diagram showing an exemplary wireless communication system in which an aspect of the present disclosure may be employed.
• FIG 1 illustrates an exemplary interconnect structure of a semiconductor device comprising a first metal layer and a second metal layer connected by a via structure with low via resistance in accordance with certain aspects of the present disclosure.
• An interconnect structure 100 is shown in Figure 1.
• the interconnect structure 100 comprises a first etch stop layer 102.
• the first etch stop layer 102 may comprise at least one of Silicon Carbon Nitride (SiCN) and Aluminum Nitride (AIN) with Oxygen Doped Carbon (ODC).
• the interconnect structure 100 also comprises a first dielectric layer 104 on the first etch stop layer 102.
• the first dielectric layer 104 may comprise Carbon Doped Silicon Oxide (SiCOH).
• the interconnect structure 100 also comprises a first metal layer 106 in the first dielectric layer 104.
• the first metal layer 106 may comprise Copper (Cu).
• the interconnect structure 100 also comprises a first barrier layer 108 between the first dielectric layer 104 and the first metal layer 106.
• the first barrier layer 108 may comprise a first Tantalum Nitride (TaN) layer between the first dielectric layer 104 and the first metal layer 106 and a first Cobalt (Co) liner between the first TaN layer and the first metal layer 106.
• the interconnect structure 100 also comprises a first cap layer 110 on the first metal layer 106.
• the first cap layer 110 may comprises Co.
• the interconnect structure 100 also comprises a second etch stop layer 112 on the first dielectric layer 104 and on the first cap layer 110.
• the second etch stop layer 112 may comprise at least one of SiCN and AIN with ODC.
• the interconnect structure 100 also comprises a second dielectric layer 114 on the second etch stop layer 112.
• the second dielectric layer 114 may comprise SiCOH.
• the interconnect structure 100 also comprises a second metal layer 116 and a via structure 118 in the second dielectric layer 114.
• the second metal layer 116 may comprise Cu.
• the via structure 118 is between the first metal layer 106 and the second metal layer 116.
• the via structure 118 comprises a second barrier layer 120 on sidewalls and at bottom of the via structure 118 and a via metal in the via structure 118.
• the via metal may comprise Cu.
• the second barrier layer 120 is also on sidewalls and at bottom of the second metal layer 116.
• the second barrier layer 120 may comprise a second TaN layer between the second dielectric layer 114 and the via metal and between the second dielectric layer 114 and the second metal layer 116 and a second Co liner between the second TaN layer and the via metal and between the second TaN layer and the second metal layer 116 on the sidewalls of the via structure 118 and on the sidewalls and at the bottom of the second metal layer 116.
• the second TaN layer may be between the first metal layer 106 and the via metal and the second Co liner may be between the second TaN layer and the via metal.
• TaN layers may be formed by Physical Vapor Deposition (PVD) at room temperature. PVD is anon-conformal deposition process. A thickness of PVD TaN layer at the bottom of the via structure 118 would be around twice a thickness of PVD TaN layer on the sidewalls of the via structure 118. Alternatively, TaN layers may be formed by Atomic Layer Deposition (ALD) at around 275°C. ALD is a conformal deposition process. A thickness of ALD TaN layer at the bottom of the via structure 118 would be around the same as a thickness of ALD TaN layer on the sidewalls of the via structure 118. A thickness of TaN layer at the bottom of the via structure 118 would affect via resistance of the via structure 118.
• PVD Physical Vapor Deposition
• ALD Atomic Layer Deposition
• a thinner TaN layer at the bottom of the via structure 118 would reduce the via resistance of the via structure 118 and improve performance of the interconnect structure 100.
• PVD TaN layer has better adhesion to Co liners compared to ALD TaN layer.
• ALD TaN layer could be combined with PVD TaN layer to form the second TaN layer in the second barrier layer 120.
• the second TaN layer may comprise ALD TaN layer with a thickness of 16 Angstrom (A) and PVD TaN layer with a thickness of 10 A on the sidewalls of the via structure 118.
• the second TaN layer may comprise ALD TaN Layer with a thickness of 16 A and PVD TaN layer with a thickness of 20 A.
• the second TaN layer may be around 36 A thick.
• the second TaN layer comprises PVD TaN layer only, with the same TaN layer thickness (26A) on the sidewalls of the via structure 118, a thickness of the second TaN layer at the bottom of the via structure 118 would be around 52 A, which is thicker compared to 36 A. Therefore, a combination of ALD TaN layer and PVD TaN layer to form the second TaN layer would realize both low via resistance and good adhesion to Co liners.
• the second TaN layer may comprise an ALD TaN layer with a thickness between 11 A and 21 A between the second dielectric layer 114 and the second Co liner and a PVD TaN layer with a thickness between 5 A and 15 A between the ALD TaN layer and the second Co liner on the sidewalls of the via structure 118.
• the ALD TaN layer may be between the first metal layer 106 and the second Co liner and the PVD TaN layer may be between the ALD TaN layer and the second Co liner.
• the second Co liner may have a thickness between 20 A and 30 A. Because the first TaN layer does not contribute to the via resistance of the via structure 118, the first TaN layer may comprise ALD TaN layer only, PVD TaN layer only, or a combination of ALD TaN layer and PVD TaN layer.
• ALD may be performed around 275°C. This temperature would generate stress at interface between the ALD TaN layer at the bottom of the vias structure 118 and Cu in the first metal layer 106 due to different coefficients of thermal expansion between TaN (3.6xlO' 6 /K) and Cu (16.5xlO' 6 /K). The stress generated may lead to voids formed at the interface and increase the via resistance of the via structure 118.
• the interconnect structure 100 also comprises a third metal layer 122 between the ALD TaN layer at the bottom of the via structure 118 and the first metal layer 106.
• the third metal layer 122 may comprise a metallic material having a coefficient of thermal expansion less than 7xlO' 6 /K, such as Tungsten (W), Molybdenum (Mo), Chromium (Cr), Osmium (Os), Zirconium (Zr), Hafnium (Hf), Rhenium (Re), Cerium (Ce), Tantalum (Ta), Ruthenium (Ru), Iridium (Ir), and Praseodymium (Pr).
• the third metal layer 122 may have a thickness less than 5 nanometer (nm).
• a top surface of the third metal layer 122 may be coplanar with or below a top surface of the second etch stop layer 112.
• the metallic materials mentioned above could grow at room temperature and achieve good adhesion with Cu through metallic bonding. Because the metallic materials mentioned above have similar coefficients of thermal expansion to TaN, ALD TaN layer adhesion on these metallic materials is better than ALD TaN layer adhesion on Cu. Thus, with the third metal layer 122, less stress would be generated at the interface between the ALD TaN layer at the bottom of the via structure 118 and Cu in the first metal layer 106. The third metal layer 122 would help to eliminate voids at the interface and reduce the via resistance of the via structure 118.
• the interconnect structure 100 further comprises a second cap layer 124 on the second metal layer 116. As an example, the second cap layer 124 may comprise Co.
• the combination of ALD TaN layer and PVD TaN layer at the bottom of the via structure 118 together with the third metal layer 122 would reduce the via resistance of the via structure 118 and improve the performance of the interconnect structure 100.
• FIGS 2A-2B illustrate an exemplary fabrication process for the interconnect structure 100 in Figure 1 in accordance with certain aspects of the present disclosure.
• stage 200(1) includes forming trench and via opening 202 in an interconnect structure of a semiconductor device.
• the interconnect structure may comprise a first etch stop layer 204.
• the first etch stop layer 204 may comprise at least one of SiCN and AIN with ODC.
• the interconnect structure may also comprise a first dielectric layer 206 on the first etch stop layer 204.
• the first dielectric layer 206 may comprise SiCOH.
• the interconnect structure may also comprise a first metal layer 208 in the first dielectric layer 206.
• the first metal layer 208 may comprise Cu.
• the interconnect structure may also comprise a first barrier layer 210 between the first dielectric layer 206 and the first metal layer 208.
• the first barrier layer 210 may comprise a first TaN layer between the first dielectric layer 206 and the first metal layer 208 and a first Co liner between the first TaN layer and the first metal layer 208.
• the interconnect structure may also comprise a first cap layer 212 on the first metal layer 208.
• the first cap layer 212 may comprises Co.
• the interconnect structure may also comprise a second etch stop layer 214 on the first dielectric layer 206 and on the first cap layer 212.
• the second etch stop layer 214 may comprise at least one of SiCN and AIN with ODC.
• the interconnect structure may further comprise a second dielectric layer 216 on the second etch stop layer 214.
• the second dielectric layer 216 may comprise SiCOH.
• the trench and via opening 202 is formed in the second dielectric layer 216 and through the second etch stop layer 214 and the first cap layer 212.
• the trench and via opening 202 extends into the first metal layer 208 to form a recess in the first metal layer 208.
• the trench and via opening 202 may be formed by a dual damascene process.
• stage 200(2) includes forming a second metal layer 218 on the first metal layer 208 at bottom of the trench and via opening 202.
• the second metal layer 218 may comprise a metallic material having a coefficient of thermal expansion less than 7xlO' 6 /K, such as W, Mo, Cr, Os, Zr, Hf, Re, Ce, Ta, Ru, Ir, and Pr.
• the second metal layer 218 may have a thickness less than 5 nm.
• a top surface of the second metal layer 218 may be coplanar with or below a top surface of the second etch stop layer 214.
• the second metal layer 218 may be formed by selective deposition, such as electroless deposition at room temperature, and may achieve good adhesion with Cu in the first metal layer 208 through metallic bonding.
• stage 200(3) includes forming a second barrier layer 220 on sidewalls of the trench and via opening 202 and on the second metal layer 218.
• the second barrier layer 220 may comprise a second TaN layer on the sidewalls of the trench and via opening 202 and on the second metal layer 218 and a second Co liner on the second TaN layer.
• the second TaN layer may be formed by ALD TaN with a thickness between 11 A and 21 A followed by PVD TaN with a thickness between 5 A and 15 A on the sidewalls of the trench and via opening 202.
• the second Co liner may be formed by Chemical Vapor Deposition (CVD) on the PVD TaN.
• the second Co liner may have a thickness between 20 A and 30 A.
• PVD is a non-conformal deposition process.
• a thickness of PVD TaN layer on the second metal layer 218 would be around twice a thickness of PVD TaN layer on the sidewalls of the trench and via opening 202.
• ALD is a conformal deposition process.
• a thickness of ALD TaN layer on the second metal layer 218 would be around the same as a thickness of ALD TaN layer on the sidewalls of the trench and via opening 202.
• a thickness of the second TaN layer on the second metal layer 218 would affect via resistance.
• a thinner second TaN layer on the second metal layer 218 would reduce the via resistance and improve performance of the interconnect structure.
• PVD TaN layer has better adhesion to Co liners compared to ALD TaN layer.
• ALD TaN and PVD TaN could be used to form the second TaN layer.
• ALD may be performed around 275°C, less stress would be generated at interface between the second TaN layer and the second metal layer 218, because the second metal layer 218 has similar coefficients of thermal expansion to TaN.
• the introduction of the second metal layer 218 between the second TaN layer and the first metal layer 208 would help to eliminate voids at the bottom of the trench and via opening 202 and reduce the via resistance. Thus, the performance of the interconnect structure would be improved.
• stage 200(4) includes depositing a third metal in the trench and via opening 202.
• the third metal may comprise Cu.
• Stage 200(4) also includes Chemical Mechanical Polishing (CMP) of the third metal and the second dielectric layer 216.
• Stage 200(4) further includes forming a second cap layer 222 on the third metal.
• the second cap layer 222 may comprise Co.
• Figure 3 shows a flow chart 300 illustrating an exemplary fabrication process for the interconnect structure 100 in Figure 1.
• Block 302 includes forming a via opening on a first metal layer.
• Block 304 includes forming a second metal layer at bottom of the via opening.
• Block 306 includes forming a barrier layer on sidewalls and at the bottom of the via opening, wherein the second metal layer is between the barrier layer at the bottom of the via opening and the first metal layer.
• Block 308 includes depositing metal in the via opening to form the interconnect structure 100.
• the interconnect structure comprising the low via resistance via structure may be provided in or integrated into any electronic device.
• Examples include a set top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a phablet, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, eyewear, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player,
• GPS global positioning system
• PDA personal digital assistant
• Figure 4 is a block diagram showing an exemplary wireless communication system 400 in which an aspect of the present disclosure may be employed.
• Figure 4 shows three remote units 420, 430, and 450 and two base stations 440.
• Remote units 420, 430, and 450 include integrated circuit (IC) devices 425A, 425C, and 425B that may include the disclosed interconnect structure.
• IC integrated circuit
• Figure 4 shows forward link signals 480 from the base stations 440 to the remote units 420, 430, and 450 and reverse link signals 490 from the remote units 420, 430, and 450 to the base stations 440.
• remote unit 420 is shown as a mobile telephone
• remote unit 430 is shown as a portable computer
• remote unit 450 is shown as a fixed location remote unit in a wireless local loop system.
• a remote unit may be a mobile phone, a hand-held personal communication systems (PCS) unit, a portable data unit such as a PDA, a GPS enabled device, a navigation device, a set top box, a music player, a video player, an entertainment unit, a fixed location data unit, such as a meter reading equipment, or other communication device that stores or retrieves data or computer instructions, or combinations thereof.
• PCS personal communication systems
• Figure 4 illustrates remote units according to certain aspects of the present disclosure, the present disclosure is not limited to these exemplary illustrated units. Certain aspects of the present disclosure may be suitably employed in many devices, which include the disclosed interconnect structure.
• An interconnect structure of a semiconductor device comprising: a via structure, the via structure comprising a barrier layer on sidewalls and at bottom of the via structure; a first metal layer; and a second metal layer between the barrier layer at the bottom of the via structure and the first metal layer, wherein the first metal layer and the second metal layer comprise different materials.
• Clause 2 The interconnect structure of clause 1, wherein the barrier layer comprises Tantalum Nitride (TaN) and Cobalt (Co).
• Clause 3 The interconnect structure of clause 1 or clause 2, wherein the first metal layer comprises Copper (Cu).
• Clause 4 The interconnect structure of any of clauses 1 to 3, wherein the second metal layer comprises a metallic material having a coefficient of thermal expansion less than 7X10' 6 /K.
• Clause 5 The interconnect structure of clause 4, wherein the metallic material comprises at least one of Tungsten (W), Molybdenum (Mo), Chromium (Cr), and Ruthenium (Ru).
• W Tungsten
• Mo Molybdenum
• Cr Chromium
• Ru Ruthenium
• Clause 6 The interconnect structure of any of clauses 1 to 5, wherein the second metal layer has a thickness less than 5 nanometer.
• Clause 7 The interconnect structure of any of clauses 1 to 6, further comprising a cap layer on the first metal layer.
• Clause 8 The interconnect structure of clause 7, wherein the cap layer comprises Co.
• Clause 9 The interconnect structure of clause 7 or clause 8, further comprising an etch stop layer on the cap layer.
• Clause 10 The interconnect structure of clause 9, wherein a top surface of the second metal layer is coplanar with or below a top surface of the etch stop layer.
• Clause 11 The interconnect structure of clause 9 or clause 10, wherein the etch stop layer comprises at least one of Silicon Carbon Nitride (SiCN) and Aluminum Nitride (AIN) with Oxygen Doped Carbon (ODC).
• SiCN Silicon Carbon Nitride
• AIN Aluminum Nitride
• ODC Oxygen Doped Carbon
• Clause 12 A method for fabricating an interconnect structure of a semiconductor device, the method comprising: forming a via opening on a first metal layer; forming a second metal layer at bottom of the via opening, wherein the first metal layer and the second metal layer comprise different materials; forming a barrier layer on sidewalls and at the bottom of the via opening, wherein the second metal layer is between the barrier layer at the bottom of the via opening and the first metal layer; and depositing metal in the via opening.
• Clause 13 The method of clause 12, wherein the barrier layer comprises Tantalum Nitride (TaN) and Cobalt (Co).
• Clause 14 The method of clause 13, wherein the TaN in the barrier layer comprises TaN formed by Atomic Layer Deposition (ALD) and Physical Vapor Deposition (PVD).
• ALD Atomic Layer Deposition
• PVD Physical Vapor Deposition
• Clause 15 The method of any of clauses 12 to 14, wherein the first metal layer comprises Copper (Cu).
• Clause 16 The method of any of clauses 12 to 15, wherein the second metal layer comprises a metallic material having a coefficient of thermal expansion less than 7x10" 6 /K.
• Clause 17 The method of clause 16, wherein the metallic material comprises at least one of Tungsten (W), Molybdenum (Mo), Chromium (Cr), and Ruthenium (Ru).
• W Tungsten
• Mo Molybdenum
• Cr Chromium
• Ru Ruthenium
• Clause 18 The method of any of clauses 12 to 17, wherein the second metal layer is formed by electroless deposition.
• Clause 19 The method of any of clauses 12 to 18, further comprising forming a cap layer on the metal in the via opening.
• Clause 20 The method of clause 19, wherein the cap layer comprises Co.

Landscapes

• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=85199417

Family Applications (1)

Country Status (7)

Families Citing this family (2)

Citations (4)

Family Cites Families (17)

• 2022
  • 2022-01-11 US US17/573,461 patent/US20230223341A1/en active Pending
  • 2022-12-20 WO PCT/US2022/053521 patent/WO2023136914A1/en not_active Ceased
  • 2022-12-20 JP JP2024541057A patent/JP2025503627A/ja active Pending
  • 2022-12-20 EP EP22854546.3A patent/EP4463887A1/en active Pending
  • 2022-12-20 CN CN202280081933.0A patent/CN118369757A/zh active Pending
  • 2022-12-20 TW TW111149010A patent/TW202335230A/zh unknown
  • 2022-12-20 KR KR1020247021909A patent/KR20240134304A/ko active Pending

Patent Citations (4)

Also Published As

Similar Documents

Legal Events