TW202335230A - 低過孔電阻互連結構 - Google Patents

低過孔電阻互連結構 Download PDF

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Publication number
TW202335230A
TW202335230A TW111149010A TW111149010A TW202335230A TW 202335230 A TW202335230 A TW 202335230A TW 111149010 A TW111149010 A TW 111149010A TW 111149010 A TW111149010 A TW 111149010A TW 202335230 A TW202335230 A TW 202335230A
Authority
TW
Taiwan
Prior art keywords
layer
metal layer
metal
interconnect structure
tan
Prior art date
Application number
TW111149010A
Other languages
English (en)
Chinese (zh)
Inventor
鈞勁 包
約翰 建宏 朱
吉里達 納拉帕蒂
Original Assignee
美商高通公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商高通公司 filed Critical 美商高通公司
Publication of TW202335230A publication Critical patent/TW202335230A/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H10W20/057—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches by selectively depositing, e.g. by using selective CVD or plating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/43—Chemical deposition, e.g. chemical vapour deposition [CVD]
    • H10P14/432—Chemical deposition, e.g. chemical vapour deposition [CVD] using selective deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H10P14/42—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials using a gas or vapour
    • H10P14/44—Physical vapour deposition [PVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW111149010A 2022-01-11 2022-12-20 低過孔電阻互連結構 TW202335230A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US17/573,461 US20230223341A1 (en) 2022-01-11 2022-01-11 Low via resistance interconnect structure
US17/573,461 2022-01-11

Publications (1)

Publication Number Publication Date
TW202335230A true TW202335230A (zh) 2023-09-01

Family

ID=85199417

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111149010A TW202335230A (zh) 2022-01-11 2022-12-20 低過孔電阻互連結構

Country Status (7)

Country Link
US (1) US20230223341A1 (https=)
EP (1) EP4463887A1 (https=)
JP (1) JP2025503627A (https=)
KR (1) KR20240134304A (https=)
CN (1) CN118369757A (https=)
TW (1) TW202335230A (https=)
WO (1) WO2023136914A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12308291B2 (en) 2022-06-03 2025-05-20 Nanya Technology Corporation Method for preparing semiconductor device structure with barrier portion
US12308318B2 (en) * 2022-06-03 2025-05-20 Nanya Technology Corporation Semiconductor device structure with barrier portion

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1020543A1 (en) * 1999-01-15 2000-07-19 Interuniversitair Micro-Elektronica Centrum Vzw Deposition of copper on an activated surface of a substrate
US20030148618A1 (en) * 2002-02-07 2003-08-07 Applied Materials, Inc. Selective metal passivated copper interconnect with zero etch stops
JP4647184B2 (ja) * 2002-12-27 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US20070057305A1 (en) * 2005-09-13 2007-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. MIM capacitor integrated into the damascene structure and method of making thereof
US20070249156A1 (en) * 2006-04-20 2007-10-25 Griselda Bonilla Method for enabling hard mask free integration of ultra low-k materials and structures produced thereby
US7651943B2 (en) * 2008-02-18 2010-01-26 Taiwan Semicondcutor Manufacturing Company, Ltd. Forming diffusion barriers by annealing copper alloy layers
US9514983B2 (en) * 2012-12-28 2016-12-06 Intel Corporation Cobalt based interconnects and methods of fabrication thereof
US9059217B2 (en) * 2013-03-28 2015-06-16 International Business Machines Corporation FET semiconductor device with low resistance and enhanced metal fill
EP3503168A1 (en) * 2014-12-23 2019-06-26 INTEL Corporation Decoupled via fill
US9842805B2 (en) * 2015-09-24 2017-12-12 International Business Machines Corporation Drive-in Mn before copper plating
US10002789B2 (en) * 2016-03-24 2018-06-19 International Business Machines Corporation High performance middle of line interconnects
US10361364B2 (en) * 2017-06-14 2019-07-23 International Business Machines Corporation Co-fabrication of magnetic device structures with electrical interconnects having reduced resistance through increased conductor grain size
TW202524711A (zh) * 2017-11-30 2025-06-16 美商英特爾股份有限公司 用於先進積體電路結構製造之異質金屬線組成
KR20250070116A (ko) * 2017-11-30 2025-05-20 인텔 코포레이션 진보된 집적 회로 구조체 제조를 위한 핀 패터닝
US10395986B1 (en) * 2018-05-30 2019-08-27 International Business Machines Corporation Fully aligned via employing selective metal deposition
US10629484B1 (en) * 2018-11-01 2020-04-21 Applied Materials, Inc. Method of forming self-aligned via
US10957579B2 (en) * 2018-11-06 2021-03-23 Samsung Electronics Co., Ltd. Integrated circuit devices including a via and methods of forming the same
US11164778B2 (en) * 2019-11-25 2021-11-02 International Business Machines Corporation Barrier-free vertical interconnect structure
US11515203B2 (en) * 2020-02-05 2022-11-29 Tokyo Electron Limited Selective deposition of conductive cap for fully-aligned-via (FAV)
US11362035B2 (en) * 2020-03-10 2022-06-14 Taiwan Semiconductor Manufacturing Company, Ltd. Diffusion barrier layer for conductive via to decrease contact resistance
US11289375B2 (en) * 2020-03-23 2022-03-29 International Business Machines Corporation Fully aligned interconnects with selective area deposition

Also Published As

Publication number Publication date
EP4463887A1 (en) 2024-11-20
WO2023136914A1 (en) 2023-07-20
CN118369757A (zh) 2024-07-19
US20230223341A1 (en) 2023-07-13
JP2025503627A (ja) 2025-02-04
KR20240134304A (ko) 2024-09-09

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