JP2011530835A - 金属相互接続のための共形接着促進材ライナ - Google Patents
金属相互接続のための共形接着促進材ライナ Download PDFInfo
- Publication number
- JP2011530835A JP2011530835A JP2011523063A JP2011523063A JP2011530835A JP 2011530835 A JP2011530835 A JP 2011530835A JP 2011523063 A JP2011523063 A JP 2011523063A JP 2011523063 A JP2011523063 A JP 2011523063A JP 2011530835 A JP2011530835 A JP 2011530835A
- Authority
- JP
- Japan
- Prior art keywords
- liner
- metal
- conformal
- layer
- adhesion promoter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 251
- 239000002184 metal Substances 0.000 title claims abstract description 250
- 239000002318 adhesion promoter Substances 0.000 title claims abstract description 73
- 239000010949 copper Substances 0.000 claims abstract description 266
- 150000004767 nitrides Chemical class 0.000 claims abstract description 75
- 239000000463 material Substances 0.000 claims abstract description 71
- 229910052802 copper Inorganic materials 0.000 claims abstract description 63
- -1 copper nitride Chemical class 0.000 claims abstract description 42
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 29
- 238000009713 electroplating Methods 0.000 claims abstract description 28
- 238000000231 atomic layer deposition Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 63
- 238000000137 annealing Methods 0.000 claims description 24
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 22
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 21
- 238000005240 physical vapour deposition Methods 0.000 claims description 18
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 14
- 229910052757 nitrogen Inorganic materials 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 11
- 229910021529 ammonia Inorganic materials 0.000 claims description 10
- 239000004065 semiconductor Substances 0.000 claims description 10
- 239000001995 intermetallic alloy Substances 0.000 claims description 8
- 239000000203 mixture Substances 0.000 claims description 7
- 229910052799 carbon Inorganic materials 0.000 claims description 3
- 229910052801 chlorine Inorganic materials 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 229910052717 sulfur Inorganic materials 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 153
- 230000008569 process Effects 0.000 description 25
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000000151 deposition Methods 0.000 description 11
- 230000008021 deposition Effects 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 6
- 239000005368 silicate glass Substances 0.000 description 6
- 230000009977 dual effect Effects 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 4
- 125000004433 nitrogen atom Chemical group N* 0.000 description 4
- 239000011800 void material Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 125000004429 atom Chemical group 0.000 description 2
- 239000005388 borosilicate glass Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 230000004927 fusion Effects 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000010899 nucleation Methods 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 238000000992 sputter etching Methods 0.000 description 2
- 238000005477 sputtering target Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910019142 PO4 Inorganic materials 0.000 description 1
- 229910004200 TaSiN Inorganic materials 0.000 description 1
- 229910008482 TiSiN Inorganic materials 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 229910008807 WSiN Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000001723 curing Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 229910001873 dinitrogen Inorganic materials 0.000 description 1
- 238000009429 electrical wiring Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229940104869 fluorosilicate Drugs 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 229910052741 iridium Inorganic materials 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- NBIIXXVUZAFLBC-UHFFFAOYSA-K phosphate Chemical compound [O-]P([O-])([O-])=O NBIIXXVUZAFLBC-UHFFFAOYSA-K 0.000 description 1
- 239000010452 phosphate Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052702 rhenium Inorganic materials 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76864—Thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76868—Forming or treating discontinuous thin films, e.g. repair, enhancement or reinforcement of discontinuous thin films
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1068—Formation and after-treatment of conductors
- H01L2221/1073—Barrier, adhesion or liner layers
- H01L2221/1084—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L2221/1089—Stacks of seed layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- General Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
【解決手段】 誘電体層を少なくとも1つのライン・トラフ及び/又は少なくとも1つのビア・キャビティを有するようにパターン化する。金属窒化物ライナをパターン化誘電体層の表面上に形成する。金属ライナを金属窒化物ライナの表面上に形成する。共形銅窒化物層を、原子層堆積(ALD)又は化学気相堆積(CVD)によって、金属ライナの直接上に形成する。Cuシード層を共形銅窒化物層の直接上に形成する。少なくとも1つのライン・トラフ及び/又は少なくとも1つのビア・キャビティは、電気めっき材料で充填される。共形銅窒化物層とCuシード層との間の直接接触は、強化された接着強度を与える。共形銅窒化物層をアニールして、露出した外側部分を連続的なCu層に変換することができ、このことはCuシード層の厚さを減すのに用いることができる。
【選択図】 図3
Description
金属窒化物ライナ120は、典型的には、物理気相堆積(PVD)によって形成される。PVDは、堆積される材料が、スパッタリング・ターゲットの方向から堆積が起る基板に向かって動く方向性堆積法であるので、金属窒化物ライナ120の段差被覆率は、常に1.0より小さく、すなわち、平面表面上よりも構造体の側壁上により少ない材料が堆積される。したがって、ビア・キャビティの側壁上よりもライン・トレンチの底表面上により多くの材料が堆積される。側壁の被覆率を増加させるための1つの方法は、堆積と方向性スパッタ・エッチングの組み合わせである。この場合、窪んだ底表面上に堆積された金属材料を、底表面から再スパッタで除去し、方向性スパッタ・エッチングによって窪んだ底表面を囲む側壁に再堆積させることができる。さらに、ビア・キャビティの下部分よりもビア・キャビティの側壁の上部分上により多くの材料が堆積される。化学気相堆積(CVD)及び原子層堆積(ALD)法はPVDよりも改善された段差被覆率を与えることが知られているが、これらの膜内には不純物が見られることが多く、これが接着層及び拡散障壁層としての膜の質を劣化させる。
基板上にパターン化誘電体層を形成することと、
パターン化誘電体層のパターン化表面の直接上に金属窒化物ライナを形成することと、
金属窒化物ライナの直接上に元素金属又は金属間合金を含む金属ライナを形成することと、
金属ライナの直接上に、化学気相堆積(CVD)又は原子層堆積(ALD)によって銅窒化物を含む共形接着促進材ライナを形成することと
を含む。
基板上に配置され、ライン・トラフ及びビア・キャビティのうちの少なくとも1つを含むパターン化誘電体層と、
パターン化誘電体層のパターン化表面に隣接する金属窒化物ライナと、
元素金属又は金属間合金を含み、金属窒化物ライナに隣接する金属ライナと、
銅窒化物を含み、金属ライナに隣接する共形接着促進材ライナと
を含む。
共形Cuリッチ導電層に隣接するCuシード層と、
電気めっき導電性構造体と
をさらに含み、ここで、金属窒化物ライナ、金属ライナ、共形接着促進材ライナ、共形Cuリッチ導電層、Cuシード層、及び電気めっき導電性構造体は、ライン・トラフ又はビア・キャビティを完全に充填する。
典型的には、金属窒化物ライナ20は、真空中で行われるスパッタリング・プロセスである物理気相堆積(PVD)によって堆積される。金属の粒子は、真空プロセスチャンバ内において窒素雰囲気下でスパッタリング・ターゲットから追い出され、真空プロセスチャンバ内に配置されたパターン化誘電体層10の表面上に堆積される。PVDプロセスは方向性である。したがって、垂直表面上よりも窪んでいない又は突き出た水平表面上により多くの材料が堆積される。また、垂直表面の底部分上よりも垂直表面の上部分上により多くの材料が堆積される。したがって、金属窒化物ライナ20の厚さは、測定の位置によって変わる。金属窒化物ライナ20内の変動を含めて、金属窒化物ライナ20の厚さは、約2nmから約20nmまでとすることができるが、より薄い厚さ及びより厚い厚さもまた本明細書で考慮される。いくつかの実施形態において、金属窒化物ライナ20は、化学気相堆積(CVD)又は原子層堆積(ALD)によって形成することができる。
15:キャビティ
20、120:金属窒化物ライナ
30、130:金属ライナ
33、133:薄い金属ライナ領域
40:共形接着促進材ライナ
45:共形Cuリッチ導電層
50、150:Cuシード層
60:電気めっき導電性構造体
80:導電性Cu構造体
137:キャビティ(ボイド)
160:電気めっきCu構造体
Claims (25)
- 半導体構造体を形成する方法であって、
基板上にパターン化誘電体層を形成するステップと、
前記パターン化誘電体層のパターン化表面の直接上に、金属窒化物ライナを形成するステップと、
前記金属窒化物ライナの直接上に、元素金属又は金属間合金を含む金属ライナを形成するステップと、
前記金属ライナの直接上に、化学気相堆積(CVD)又は原子層堆積(ALD)によって、銅窒化物を含む共形接着促進材ライナを形成するステップと
を含む方法。 - 前記共形接着促進材ライナの直接上に、Cuシード層を形成するステップをさらに含む、請求項1に記載の方法。
- 前記Cuシード層の直接上に、Cu材料を電気めっきするステップをさらに含む、請求項2に記載の方法。
- 前記パターン化誘電体層は、ライン・トラフ及びビア・キャビティのうちの少なくとも1つを含む、請求項3に記載の方法。
- 前記ライン・トラフ又は前記ビア・キャビティは、前記Cu材料の前記電気めっきによって完全に充填される、請求項4に記載の方法。
- 前記電気めっきCu材料を平坦化するステップをさらに含み、前記金属窒化物ライナの表面、前記金属ライナの表面、前記共形接着促進材ライナの表面、及び前記電気めっきCu材料の表面は、実質的に水平で同一平面上にある、請求項3に記載の方法。
- 前記電気めっきCu材料及び前記Cuシード層をアニールするステップをさらに含み、前記電気めっきCu材料及び前記Cuシード層は構造的に融合して、その全体積内に界面のない一体構造の導電性Cu構造体を形成する、請求項6に記載の方法。
- 前記共形接着促進材ライナは、銅アミジナートとアンモニアに対する一連の交互露出による原子層堆積(ALD)によって形成される、請求項1に記載の方法。
- 前記ALDは150℃から300℃までの温度で実行され、銅アミジナートの分圧は、銅アミジナートに対する露出の各サイクルの間、1mトルから1トルまでである、請求項8に記載の方法。
- 前記共形接着促進材ライナは、銅アミジナート及びアンモニアの同時の流れを使用する化学気相堆積(CVD)によって形成される、請求項1に記載の方法。
- 前記CVDは150℃から350℃までの温度で実行され、銅アミジナートの分圧は、前記CVDの間、1mトルから100トルまでである、請求項10に記載の方法。
- 前記銅窒化物はCuxNの組成を有し、xは1から5までである、請求項1に記載の方法。
- 前記共形接着促進材ライナを150℃から400℃までの高温でアニールするステップをさらに含み、前記共形接着促進材ライナの露出した外側部分は、銅及び窒素を含む共形Cuリッチ導電層に変換される、請求項1に記載の方法。
- 前記共形Cuリッチ導電層の直接上に、物理気相堆積(PVD)によってCuシード層を形成するステップと、
前記Cuシード層の直接上に、Cu材料を電気めっきするステップと
をさらに含む、請求項13に記載の方法。 - 前記電気めっきCu材料、前記Cuシード層、及び前記共形Cuリッチ導電層をアニールするステップをさらに含み、前記共形Cuリッチ導電層は共形元素Cu層を含み、前記電気めっきCu材料、前記Cuシード層、及び前記共形元素Cu層は構造的に融合して、その全体積内に界面のない一体構造の導電性Cu構造体を形成する、請求項14に記載の方法。
- 基板上に配置され、ライン・トラフ及びビア・キャビティのうちの少なくとも1つを含むパターン化誘電体層と、
前記パターン化誘電体層のパターン化表面に隣接する金属窒化物ライナと、
元素金属又は金属間合金を含み、前記金属窒化物ライナに隣接する金属ライナと、
銅窒化物を含み、前記金属ライナに隣接する共形接着促進材ライナと
を含む、金属相互接続構造体。 - 前記共形接着促進材ライナに隣接するCuシード層をさらに含む、請求項16に記載の金属相互接続構造体。
- 電気めっき導電性構造体をさらに含み、前記金属窒化物ライナ、前記金属ライナ、前記共形接着促進材ライナ、前記Cuシード層、及び前記電気めっき導電性構造体は、前記ライン・トラフ又は前記ビア・キャビティを完全に充填する、請求項17に記載の金属相互接続構造体。
- 前記金属窒化物ライナの表面、前記金属ライナの表面、前記共形接着促進材ライナの表面、及び前記電気めっき導電性構造体の表面は、実質的に水平で同一平面上にある、請求項18に記載の金属相互接続構造体。
- 前記電気めっき導電性構造体はCu及び不純物からなり、前記不純物はO、N、C、Cl及びSを含み、前記不純物の全濃度は1ppmから200ppmまでである、請求項18に記載の金属相互接続構造体。
- 前記銅窒化物は、CuxNの組成を有し、xは1から5までである、請求項16に記載の金属相互接続構造体。
- 前記共形接着促進材ライナは、0.5nmから20nmまでの厚さを有する、請求項16に記載の金属相互接続構造体。
- 前記共形接着促進材ライナ上に隣接する共形Cuリッチ導電層をさらに含む、請求項16に記載の金属相互接続構造体。
- 前記共形Cuリッチ導電層に隣接するCuシード層と、
電気メッキ導電性構造体と
をさらに含み、
前記金属窒化物ライナ、前記金属ライナ、前記共形接着促進材ライナ、前記共形Cuリッチ導電層、前記Cuシード層、及び前記電気めっき導電性構造体は、前記ライン・トラフ又は前記ビア・キャビティを完全に充填する、
請求項16に記載の金属相互接続構造体。 - その全体積内に界面がなく、前記共形接着促進材ライナに隣接する、一体構造の導電性Cu構造体をさらに含む、請求項16に記載の金属相互接続構造体。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/190,906 | 2008-08-13 | ||
US12/190,906 US8105937B2 (en) | 2008-08-13 | 2008-08-13 | Conformal adhesion promoter liner for metal interconnects |
PCT/US2009/053256 WO2010019490A1 (en) | 2008-08-13 | 2009-08-10 | Conformal adhesion promoter liner for metal interconnects |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014094906A Division JP5856647B2 (ja) | 2008-08-13 | 2014-05-02 | 金属相互接続構造体及び金属相互接続構造体の形成方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2011530835A true JP2011530835A (ja) | 2011-12-22 |
Family
ID=41669219
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011523063A Pending JP2011530835A (ja) | 2008-08-13 | 2009-08-10 | 金属相互接続のための共形接着促進材ライナ |
JP2014094906A Expired - Fee Related JP5856647B2 (ja) | 2008-08-13 | 2014-05-02 | 金属相互接続構造体及び金属相互接続構造体の形成方法 |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2014094906A Expired - Fee Related JP5856647B2 (ja) | 2008-08-13 | 2014-05-02 | 金属相互接続構造体及び金属相互接続構造体の形成方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US8105937B2 (ja) |
JP (2) | JP2011530835A (ja) |
KR (1) | KR20110052668A (ja) |
CN (1) | CN102124559B (ja) |
WO (1) | WO2010019490A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160048665A (ko) * | 2014-10-25 | 2016-05-04 | 램 리써치 코포레이션 | 선택적인 배리어 증착을 활용하는 인터레벨 도전체 사전-충진 |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2010010753A1 (ja) * | 2008-07-22 | 2010-01-28 | 国立大学法人東北大学 | 配線基板及びその製造方法 |
US8048761B2 (en) * | 2009-02-17 | 2011-11-01 | Globalfoundries Singapore Pte. Ltd. | Fabricating method for crack stop structure enhancement of integrated circuit seal ring |
CN102082119B (zh) * | 2010-11-16 | 2013-04-10 | 复旦大学 | 一种选择性淀积钨接触孔或通孔的方法 |
WO2012121677A1 (en) * | 2011-03-09 | 2012-09-13 | Nanyang Technological University | Method for depositing gradient films on a substrate surface by atomic layer deposition |
TWI502716B (zh) * | 2011-05-12 | 2015-10-01 | United Microelectronics Corp | 一種製作矽貫通電極的方法 |
US8481425B2 (en) * | 2011-05-16 | 2013-07-09 | United Microelectronics Corp. | Method for fabricating through-silicon via structure |
US9177826B2 (en) * | 2012-02-02 | 2015-11-03 | Globalfoundries Inc. | Methods of forming metal nitride materials |
US8753975B1 (en) | 2013-02-01 | 2014-06-17 | Globalfoundries Inc. | Methods of forming conductive copper-based structures using a copper-based nitride seed layer without a barrier layer and the resulting device |
US8859419B2 (en) | 2013-02-01 | 2014-10-14 | Globalfoundries Inc. | Methods of forming copper-based nitride liner/passivation layers for conductive copper structures and the resulting device |
CN103255368B (zh) * | 2013-05-10 | 2015-01-07 | 杭州电子科技大学 | 一种改变Cu3N薄膜择优取向的方法 |
US20150001720A1 (en) * | 2013-06-27 | 2015-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interconnect Structure and Method for Forming Interconnect Structure |
US9553059B2 (en) | 2013-12-20 | 2017-01-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Backside redistribution layer (RDL) structure |
US9219033B2 (en) * | 2014-03-21 | 2015-12-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Via pre-fill on back-end-of-the-line interconnect layer |
US10079174B2 (en) | 2014-04-30 | 2018-09-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Composite contact plug structure and method of making same |
US9379057B2 (en) * | 2014-09-02 | 2016-06-28 | International Business Machines Corporation | Method and structure to reduce the electric field in semiconductor wiring interconnects |
US9431603B1 (en) * | 2015-05-15 | 2016-08-30 | Taiwan Semiconductor Manufacturing Co., Ltd. | RRAM device |
TWI700799B (zh) * | 2016-10-04 | 2020-08-01 | 聯華電子股份有限公司 | 導電結構、包含導電結構之佈局結構以及導電結構之製作方法 |
US10892186B2 (en) | 2017-10-14 | 2021-01-12 | Applied Materials, Inc. | Integration of ALD copper with high temperature PVD copper deposition for BEOL interconnect |
US11004794B2 (en) | 2018-06-27 | 2021-05-11 | Taiwan Semiconductor Manufacturing Co., Ltd. | Partial barrier free vias for cobalt-based interconnects and methods of fabrication thereof |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06310512A (ja) * | 1993-04-27 | 1994-11-04 | Nec Corp | Cu配線およびその形成方法 |
JP2004281481A (ja) * | 2003-03-13 | 2004-10-07 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JP2004532519A (ja) * | 2001-03-23 | 2004-10-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電子構造の製造方法 |
JP2005136433A (ja) * | 2004-12-15 | 2005-05-26 | Internatl Business Mach Corp <Ibm> | 集積回路チップ上の電気めっき相互接続構造 |
JP2006511716A (ja) * | 2002-11-15 | 2006-04-06 | プレジデント・アンド・フェロウズ・オブ・ハーバード・カレッジ | 金属アミジナートを用いる原子層の析出 |
JP2007051124A (ja) * | 2005-07-22 | 2007-03-01 | Ube Ind Ltd | 新規な銅錯体及び当該銅錯体を用いた銅含有薄膜の製造方法 |
JP2008066680A (ja) * | 2006-09-11 | 2008-03-21 | Samsung Electronics Co Ltd | 配線構造と配線形成方法及び薄膜トランジスタ基板とその製造方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06318592A (ja) * | 1993-05-10 | 1994-11-15 | Kawasaki Steel Corp | 半導体集積回路のCu配線構造体の製造方法 |
JPH0888224A (ja) * | 1994-09-16 | 1996-04-02 | Toshiba Corp | 半導体装置およびその製造方法 |
US6037248A (en) | 1997-06-13 | 2000-03-14 | Micron Technology, Inc. | Method of fabricating integrated circuit wiring with low RC time delay |
KR100385042B1 (ko) * | 1998-12-03 | 2003-06-18 | 인터내셔널 비지네스 머신즈 코포레이션 | 내 일렉트로 마이그레이션의 구조물을 도핑으로 형성하는 방법 |
US6171949B1 (en) | 1999-06-09 | 2001-01-09 | Advanced Micro Devices, Inc. | Low energy passivation of conductive material in damascene process for semiconductors |
JP4554011B2 (ja) | 1999-08-10 | 2010-09-29 | ルネサスエレクトロニクス株式会社 | 半導体集積回路装置の製造方法 |
US6727169B1 (en) * | 1999-10-15 | 2004-04-27 | Asm International, N.V. | Method of making conformal lining layers for damascene metallization |
JP3518470B2 (ja) * | 2000-03-01 | 2004-04-12 | 日本電気株式会社 | 半導体装置の製造方法 |
US6365927B1 (en) | 2000-04-03 | 2002-04-02 | Symetrix Corporation | Ferroelectric integrated circuit having hydrogen barrier layer |
CN100334709C (zh) * | 2000-11-02 | 2007-08-29 | 富士通株式会社 | 半导体器件及其制造方法 |
JP4535629B2 (ja) | 2001-02-21 | 2010-09-01 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
US6900119B2 (en) | 2001-06-28 | 2005-05-31 | Micron Technology, Inc. | Agglomeration control using early transition metal alloys |
US6645853B1 (en) * | 2001-12-05 | 2003-11-11 | Advanced Micro Devices, Inc. | Interconnects with improved barrier layer adhesion |
US7067424B2 (en) * | 2001-12-19 | 2006-06-27 | Koninklijke Philips Electronics N.V. | Method of manufacturing an electronic device |
US6518184B1 (en) | 2002-01-18 | 2003-02-11 | Intel Corporation | Enhancement of an interconnect |
US7109070B2 (en) | 2002-08-07 | 2006-09-19 | Schot Glas | Production of a composite material having a biodegradable plastic substrate and at least one coating |
JP4173393B2 (ja) * | 2003-03-24 | 2008-10-29 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
TW200501289A (en) | 2003-04-09 | 2005-01-01 | Kulicke & Soffa Investments | Interconnect apparatus and methods |
US7094705B2 (en) | 2004-01-20 | 2006-08-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Multi-step plasma treatment method to improve CU interconnect electrical performance |
US7105445B2 (en) | 2005-01-14 | 2006-09-12 | International Business Machines Corporation | Interconnect structures with encasing cap and methods of making thereof |
TWI354350B (en) | 2005-05-25 | 2011-12-11 | Au Optronics Corp | Copper gate electrode and fabricating method there |
US7405153B2 (en) * | 2006-01-17 | 2008-07-29 | International Business Machines Corporation | Method for direct electroplating of copper onto a non-copper plateable layer |
US7749906B2 (en) * | 2006-02-22 | 2010-07-06 | Intel Corporation | Using unstable nitrides to form semiconductor structures |
US20090162550A1 (en) | 2006-06-02 | 2009-06-25 | Advanced Technology Materials, Inc. | Copper (i) amidinates and guanidinates, mixed ligand copper complexes, and compositions for chemical vapor deposition, atomic layer deposition, and rapid vapor deposition of copper |
JP4783261B2 (ja) | 2006-10-30 | 2011-09-28 | 株式会社東芝 | 半導体装置の製造方法 |
US7973189B2 (en) * | 2007-04-09 | 2011-07-05 | President And Fellows Of Harvard College | Cobalt nitride layers for copper interconnects and methods for forming them |
-
2008
- 2008-08-13 US US12/190,906 patent/US8105937B2/en not_active Expired - Fee Related
-
2009
- 2009-08-10 JP JP2011523063A patent/JP2011530835A/ja active Pending
- 2009-08-10 CN CN200980131364.0A patent/CN102124559B/zh not_active Expired - Fee Related
- 2009-08-10 WO PCT/US2009/053256 patent/WO2010019490A1/en active Application Filing
- 2009-08-10 KR KR1020117004716A patent/KR20110052668A/ko not_active Application Discontinuation
-
2014
- 2014-05-02 JP JP2014094906A patent/JP5856647B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06310512A (ja) * | 1993-04-27 | 1994-11-04 | Nec Corp | Cu配線およびその形成方法 |
JP2004532519A (ja) * | 2001-03-23 | 2004-10-21 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 電子構造の製造方法 |
JP2006511716A (ja) * | 2002-11-15 | 2006-04-06 | プレジデント・アンド・フェロウズ・オブ・ハーバード・カレッジ | 金属アミジナートを用いる原子層の析出 |
JP2004281481A (ja) * | 2003-03-13 | 2004-10-07 | Seiko Epson Corp | 半導体装置の製造方法及び半導体装置 |
JP2005136433A (ja) * | 2004-12-15 | 2005-05-26 | Internatl Business Mach Corp <Ibm> | 集積回路チップ上の電気めっき相互接続構造 |
JP2007051124A (ja) * | 2005-07-22 | 2007-03-01 | Ube Ind Ltd | 新規な銅錯体及び当該銅錯体を用いた銅含有薄膜の製造方法 |
JP2008066680A (ja) * | 2006-09-11 | 2008-03-21 | Samsung Electronics Co Ltd | 配線構造と配線形成方法及び薄膜トランジスタ基板とその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160048665A (ko) * | 2014-10-25 | 2016-05-04 | 램 리써치 코포레이션 | 선택적인 배리어 증착을 활용하는 인터레벨 도전체 사전-충진 |
KR102523689B1 (ko) * | 2014-10-25 | 2023-04-19 | 램 리써치 코포레이션 | 선택적인 배리어 증착을 활용하는 인터레벨 도전체 사전-충진 |
Also Published As
Publication number | Publication date |
---|---|
JP2014140078A (ja) | 2014-07-31 |
JP5856647B2 (ja) | 2016-02-10 |
WO2010019490A1 (en) | 2010-02-18 |
US8105937B2 (en) | 2012-01-31 |
KR20110052668A (ko) | 2011-05-18 |
CN102124559B (zh) | 2014-05-28 |
CN102124559A (zh) | 2011-07-13 |
US20100038789A1 (en) | 2010-02-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5856647B2 (ja) | 金属相互接続構造体及び金属相互接続構造体の形成方法 | |
US20220336271A1 (en) | Doped selective metal caps to improve copper electromigration with ruthenium liner | |
US8039966B2 (en) | Structures of and methods and tools for forming in-situ metallic/dielectric caps for interconnects | |
JP4236201B2 (ja) | 半導体装置の製造方法 | |
US7417321B2 (en) | Via structure and process for forming the same | |
US8124524B2 (en) | Methods of forming metal interconnection structures | |
US7524755B2 (en) | Entire encapsulation of Cu interconnects using self-aligned CuSiN film | |
US7960832B2 (en) | Integrated circuit arrangement with layer stack | |
TWI397149B (zh) | 形成包括有具伸張應力之介電質蓋罩之介連接線的方法與結構 | |
KR101502691B1 (ko) | 하이브리드 확산 장벽층의 형성 방법 및 그 반도체 디바이스 | |
US20050023686A1 (en) | Multilayer diffusion barrier for copper interconnections | |
US20070059919A1 (en) | Method of manufacturing semiconductor device | |
US20070093060A1 (en) | Semiconductor device having a cu interconnection | |
US20080173547A1 (en) | Method of manufacturing semiconductor device | |
JP2023515920A (ja) | コバルト注入ルテニウム・ライナとコバルト・キャップとの相互接続構造 | |
US7358180B2 (en) | Method of forming wiring structure and semiconductor device | |
US20060154465A1 (en) | Method for fabricating interconnection line in semiconductor device | |
JP2005005383A (ja) | 半導体装置および半導体装置の製造方法 | |
US7538024B2 (en) | Method of fabricating a dual-damascene copper structure | |
US20070152333A1 (en) | Metal Interconnection of Semiconductor Device and Method of Fabricating the Same | |
US20090001579A1 (en) | Multi-layered metal line having an improved diffusion barrier of a semiconductor device and method for forming the same | |
US20070052098A1 (en) | Metal line for a semiconductor device and fabrication method thereof | |
JP2012039019A (ja) | 半導体装置およびその製造方法 | |
US7981781B2 (en) | Metal line of semiconductor device having a diffusion barrier and method for forming the same | |
KR100891524B1 (ko) | 반도체 소자의 제조방법 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20120329 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20131031 |
|
RD12 | Notification of acceptance of power of sub attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7432 Effective date: 20140220 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A821 Effective date: 20140220 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20140402 |