WO2024247025A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

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Publication number
WO2024247025A1
WO2024247025A1 PCT/JP2023/019866 JP2023019866W WO2024247025A1 WO 2024247025 A1 WO2024247025 A1 WO 2024247025A1 JP 2023019866 W JP2023019866 W JP 2023019866W WO 2024247025 A1 WO2024247025 A1 WO 2024247025A1
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Prior art keywords
semiconductor device
layer
gold
plating
substrate
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English (en)
French (fr)
Japanese (ja)
Inventor
亮 奥畑
弘一郎 西澤
智之 森田
智明 徳久
寿和 清水
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2023556766A priority Critical patent/JP7378693B1/ja
Priority to PCT/JP2023/019866 priority patent/WO2024247025A1/ja
Priority to CN202380098296.2A priority patent/CN121219834A/zh
Publication of WO2024247025A1 publication Critical patent/WO2024247025A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/80—FETs having rectifying junction gate electrodes
    • H10D30/87—FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes

Definitions

  • This application relates to a semiconductor device and a method for manufacturing the semiconductor device.
  • Cu copper
  • Via filling with copper plating is performed by electrolytic plating, which requires precise control of the plating solution composition, applied voltage waveform, solution agitation, etc. (see, for example, Patent Document 1).
  • a diffusion barrier layer must be formed on the inner wall of the via (see, for example, Patent Document 2).
  • JP 2014-095104 A (paragraphs 0042 to 0050, Table 1)
  • JP2013-532903A (paragraph 0039, FIG. 13)
  • Cu via filling by electrolytic plating requires precise control of the plating process (composition of plating solution, applied voltage waveform, agitation of solution), which poses problems of excessive equipment investment and increased costs for process management.
  • the diffusion barrier layer requires materials such as conductive metal nitrides, which have a complex formation process and are difficult to handle, which again poses problems of excessive equipment investment and increased costs for process management.
  • This application discloses technology to solve the problems described above, and aims to provide a semiconductor device with good electrical connection and heat dissipation in the thickness direction at low cost.
  • the semiconductor device disclosed in this application is characterized by comprising a substrate of a semiconductor material, a solid via having an opening on the other side of the substrate, a first plating layer of gold covering the inner wall of a cylindrical hole having the wiring member as its bottom surface and having a recess recessed from the opening side toward the bottom surface, and a second plating layer of copper, silver, nickel, tin, or gold having a larger crystal grain size than the first plating layer, filling the recess.
  • the method of manufacturing a semiconductor device disclosed in this application is characterized by including the steps of forming a wiring member on one side of a substrate made of a semiconductor material, forming a cylindrical hole that opens on the other side of the substrate and has the wiring member as its bottom, forming a first plating layer of gold by electroless plating so as to cover the inner wall of the cylindrical hole and form a recess that is recessed from the opening side toward the bottom, and forming a second plating layer of copper, silver, nickel, tin, or gold by electrolytic plating so as to fill the recess.
  • the semiconductor device or semiconductor device manufacturing method disclosed in this application does not require excessively large equipment and forms a gold coating layer on the inner wall of the via in a simple process, making it possible to obtain a semiconductor device with good electrical connection and heat dissipation in the thickness direction at low cost.
  • FIG. 4 is an end view for explaining a configuration of a via of the semiconductor device according to the first embodiment
  • FIG. 1 is an end view for explaining a configuration of a semiconductor device according to a first embodiment
  • 1 is a flowchart for explaining a method of manufacturing a semiconductor device according to a first embodiment.
  • 1 is an end view during a via filling process for explaining the configuration of a covering layer of a via in the semiconductor device according to the first embodiment
  • FIG. 1A to 1C are diagrams showing cross-sectional SEM images during a via filling process in the semiconductor device according to the first embodiment
  • 5A to 5C are schematic end views showing stages during formation of a covering layer in via filling of the semiconductor device according to the first embodiment.
  • FIG. 13 is an end view for explaining a configuration of a via of a semiconductor device according to a modified example of the first embodiment
  • FIG. 11 is an end view for explaining a configuration of a via of a semiconductor device according to a comparative example.
  • FIG. 11A and 11B are diagrams showing cross-sectional SEM images during a via filling process in a semiconductor device according to a comparative example.
  • 13 is an end view for explaining a configuration before a filling layer is formed in via filling of a semiconductor device according to a second embodiment.
  • FIG. 10 is a flowchart for explaining a method of manufacturing a semiconductor device according to a second embodiment.
  • FIG. 11 is an end view for explaining a configuration of a via of a semiconductor device according to a second embodiment.
  • FIG. 13 is an end view for explaining a configuration of a via of a semiconductor device according to a third embodiment.
  • FIG. 13 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the third embodiment.
  • FIG. 13 is an end view for explaining a configuration of a via of a semiconductor device according to a fourth embodiment.
  • FIG. 13 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the fourth embodiment.
  • FIG. 13 is an end view for explaining a configuration of a via of a semiconductor device according to a fifth embodiment.
  • FIG. 13 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the fifth embodiment.
  • FIG. 13 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the fifth embodiment.
  • FIG. 23 is an end view for explaining the configuration of a via of a semiconductor device according to a sixth embodiment.
  • FIG. 23 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the sixth embodiment.
  • FIG. 23 is an end view for explaining a configuration of a via of a semiconductor device according to a seventh embodiment.
  • FIG. 23 is an end view for explaining a configuration of a via in a semiconductor device according to a modified example of the seventh embodiment.
  • Embodiment 1. 1 to 9 are for explaining the semiconductor device according to the first embodiment and the manufacturing method of the semiconductor device, and FIG. 1 is an end view corresponding to the line A-A in FIG. 2 described later for explaining the configuration of the via of the semiconductor device, and FIG. 2 is an end view for explaining the configuration of the semiconductor device.
  • FIG. 3 is a flow chart for explaining the manufacturing method of the semiconductor device, and FIG. 4 is an end view corresponding to FIG. 1 before forming the filling layer and forming the coating layer during the via filling process for explaining the configuration of the coating layer of the via of the semiconductor device, and FIG. 5 is a cross-sectional SEM image at the stage of forming the coating layer similar to FIG. 4 in the via filling process.
  • FIG. 6 is an end view schematic diagram showing the state at each stage during the formation of the coating layer in the via filling of the semiconductor device according to the first embodiment.
  • FIG. 7 is an end view corresponding to FIG. 4 at the stage where a coating layer has been formed to explain the configuration of the via of the semiconductor device according to the modified example.
  • FIG. 8 is an end view at the stage where a coating layer has been formed to explain the configuration of the via of the semiconductor device according to the comparative example
  • FIG. 9 is a cross-sectional SEM image at the stage where a coating layer similar to that of FIG. 8 has been formed in the via filling process.
  • the semiconductor device 10 is assumed to be, for example, a semiconductor device called a high electron mobility transistor (HEMT).
  • HEMT high electron mobility transistor
  • Figures 1 and 2 a case will be described in which a via 10v is formed from the back surface directly below the source electrode 3s on the front surface (the upper surface in the figure).
  • the via 10v shown in Figure 1 is a detailed view of the via 10v formed directly below the source electrode 3s in Figure 2, but the via 10v does not necessarily have to be directly below the source electrode 3s, and may be located directly below a conductor layer (wiring member) formed on the front surface, including the wiring pattern.
  • a conductor layer wiring member
  • the semiconductor device 10 there is an epitaxial growth layer 2 on a silicon carbide (SiC) substrate 1, and there are a source electrode 3s, a drain electrode 3d, and a gate electrode 3g (collectively, surface electrodes 3) on top of that.
  • the via 10v is formed directly below the source electrode 3s, with the source electrode 3s serving as an etching stop layer.
  • a gallium nitride (GaN) HEMT on a silicon carbide substrate 1 is described as an example, but the present invention is not limited to this.
  • the same effect can be obtained with other semiconductor substrates, such as compound semiconductors such as indium phosphide (InP), gallium nitride, and germanium silicide (SiGe), and silicon (Si)-based semiconductors.
  • compound semiconductors such as indium phosphide (InP), gallium nitride, and germanium silicide (SiGe), and silicon (Si)-based semiconductors.
  • Au gold
  • the coating layer 42 of the via 10v is formed on the seed layer 41, and is therefore not dependent on the element type of the substrate 1.
  • step S100 epitaxial growth, metal film and insulating film formation, and transfer patterning are repeatedly performed in a wafer process on the surface (upper surface in Figs. 1 and 2) of a substrate 1 made of SiC single crystal, to form an electric circuit on the surface (step S100).
  • the wafer process is performed on a disk-shaped substrate having a diameter of 4 to 8 inches and a thickness of 0.35 mm or 0.5 mm.
  • an epitaxial growth layer 2 is formed on a substrate 1.
  • a laminated structure is generally formed in which an aluminum gallium nitride (AlGaN) layer is laminated on a gallium nitride layer.
  • AlGaN aluminum gallium nitride
  • a source electrode 3s, a drain electrode 3d, and a gate electrode 3g are formed.
  • a laminated structure such as titanium/aluminum/gold (Ti/Al/Au) or titanium/aluminum/nickel/gold (Ti/Al/Ni/Au) is used.
  • a laminated structure such as titanium/platinum/gold (Ti/Pt/Au) is used.
  • the source electrode 3s, the drain electrode 3d, and the gate electrode 3g are protected with an insulating film 9 made of, for example, silicon nitride (SiN).
  • an insulating film 9 made of, for example, silicon nitride (SiN).
  • the gate electrode 3g portion may be opened by dry etching to form the gate electrode 3g, and the whole may be protected again with the insulating film 9.
  • electrodes for wiring may be further attached.
  • electrolytic gold plating or the like is used for the electrodes for wiring.
  • a wax material is used to attach the front side of the wafer to a support substrate for processing the back side (the lower surface in Figures 1 and 2).
  • a tape material may be used instead of the wax material.
  • the thickness of the wax material is, for example, 20 ⁇ m.
  • the back side of the wafer is ground and polished while still attached to the support substrate.
  • the substrate thickness is thinned to 50 ⁇ m. By thinning the substrate, the heat dissipation and high frequency characteristics of the device are improved.
  • the via processing process (steps S200 to S230) is performed.
  • a resist material is applied using a spin coater, and then the resist is removed only from the processed area using transfer and development patterning.
  • the substrate is etched using ICP (Inductively Coupled Plasma) dry etching to form a through hole for the via 10v (step S200).
  • ICP Inductively Coupled Plasma
  • the applied resist material is removed by immersion in a stripping solution.
  • a semiconductor back surface can be obtained with the inner surface of the through hole, which becomes the via 10v in the substrate 1, exposed.
  • Smaller vias 10v are advantageous because they provide greater freedom in layout, but if they are too small, the etching process for forming the through holes will not proceed and they will not be able to penetrate the substrate 1.
  • they can be formed in a cylindrical shape with a diameter of 50 ⁇ m.
  • the aspect ratio (via depth/via diameter) of the via 10v (through hole) is 1, but this can vary depending on the substrate thickness and via shape, and can range from 1 to 5.
  • a seed layer 41 is formed to cover the inner wall of the formed through hole (step S210).
  • the seed layer 41 is formed, for example, by stacking a 200 nm thick gold layer on a 50 nm thick titanium layer in contact with the substrate 1.
  • the titanium layer is a film inserted to improve adhesion between the gold layer, which is the main component of the seed layer 41, and the substrate 1.
  • Titanium nitride, tantalum (Ta), tungsten (W), chromium (Cr), etc. may be used instead of titanium.
  • a platinum layer may also be inserted between the titanium layer and the gold layer. In that case, for example, the titanium layer may be 50 nm thick, the platinum layer may be 50 nm thick, and the gold layer may be 200 nm thick.
  • An insulating film layer may also be inserted between the substrate 1 and the seed layer 41.
  • the electroless plating reaction begins when the surface of the seed layer 41 is made into a gold layer.
  • gold silver (Ag), copper (Cu), palladium (Pd), platinum, nickel, ruthenium (Ru), tin (Sn), etc. may also be used.
  • the electroless plating reaction can be initiated by adding a step of immersing the surface in a pretreatment solution containing catalytic metal ions as a pretreatment for electroless plating, thereby adding a catalyst.
  • a pretreatment solution containing catalytic metal ions as a pretreatment for electroless plating
  • the gold which is the deposited metal, itself acts as a catalyst, so the reaction continues and a gold plating film can be obtained (autocatalytic electroless plating).
  • the seed layer 41 is interposed between the substrate 1 and the gold coating layer 42, and therefore does not need to function as a barrier layer to prevent copper diffusion as was feared in Patent Document 2. Therefore, there is no need to use materials that are difficult to handle and require complex formation processes, such as conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).
  • conductive metal nitrides such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).
  • the seed layer 41 is covered by electroless gold plating to form a gold coating layer 42 having a recess 42d that opens to the back side (step S220).
  • the figure shows an example of forming a conical recess 42d whose cross section passing through the axial center of the through hole is V-shaped.
  • the formation of the conical recess 42d can be achieved by adjusting the additive in the electroless gold plating solution within an appropriate range. Note that this additive has the effect of suppressing plating deposition on the opening side (lower side in the figure) and preferentially depositing gold from the bottom surface (upper side in the figure) and inner peripheral surface of the seed layer 41.
  • the above-mentioned method allows the formation of a coating layer 42 having a conical recess 42d.
  • the thickness t42 (see Figure 4) from the bottom of the via to the apex of the cone (bottom 42b of recess 42d) is at least 1/4 of the via height Hv.
  • the depth Dd of recess 42d is less than 4/3 of the via height Hv.
  • the via height Hv is drawn as the dimension obtained by subtracting the thickness of the seed layer 41 from the thickness of the substrate 1 including the epitaxial growth layer 2, but the thickness of the seed layer 41 is negligibly thin compared to the thickness of the substrate 1. Thinner than the substrate 1. Therefore, the sum of the thickness of the substrate 1 and the thickness of the epitaxial growth layer 2 is defined as the above-mentioned via height Hv.
  • the thickness t42 is 1/2 or less of the via height Hv. If the thickness t42 is made thicker than 1/2 of the via height Hv, the amount of additive in the plating solution will be reduced, increasing the risk of the via opening being blocked as shown in FIG. 9. Also, because the amount of additive is small, the thickness of the coating layer 42 on the back surface of the wafer will be too thick.
  • the vertical growth of the plating can be suppressed by the additive. Therefore, as shown in FIG. 6, once the plating has grown through stages 1, 2, and 3 to a thickness t42 determined by the amount of additive added, the gold plating will not grow even if the wafer is subsequently immersed in an electroless plating solution for, for example, two hours (from stage 3 to stage 4). Therefore, a coating layer 42 having recesses 42d with the same uniform thickness t42 can be formed in each of the multiple through holes in the substrate surface.
  • the recesses 42d shown in FIG. 1 are filled by electrolytic plating to form a gold filling layer 43 with a larger crystal grain size than the coating layer 42 formed by electroless plating (step S230).
  • This forms a solid via 10v whose through hole is filled completely with gold.
  • it is advisable to apply a pulse voltage.
  • a depression will occur in the opening end of the via 10v (the lower surface in the figure), i.e., the filling layer 43, reflecting the recesses 42d in the coating layer 42, but the presence or absence of this depression and its shape are not important.
  • the via 10v is completely filled with the filling layer 43 formed by electrolytic plating, improving high frequency characteristics and heat dissipation. If the gold film thickness on the back surface (lower part in the figure) of the wafer becomes too thick due to the complete filling of the via 10v, etching can be carried out until the desired film thickness is reached.
  • argon (Ar) ion milling is used for dry etching
  • iodine (I)-based wet etching is used for wet etching.
  • the support substrate is peeled off from the wafer.
  • the support substrate and wafer are heated to 100°C on a hot plate for at least one minute to melt the wax material, and then slid parallel to the wafer surface to peel them off.
  • the wafer is then immersed in acetone heated to 50°C for 10 minutes to remove the wax material from the surface (step S300). At this time, the higher the temperature and the longer the immersion time, the better the removability.
  • the recess 42d of the coating layer 42 does not necessarily have to have a V-shaped (conical) cross-sectional shape as shown in Fig. 4, but may have a curved recessed shape as shown in the modified example of Fig. 7. It is sufficient that the opening width Wd of the recess 42d of the coating layer 42 is formed so as to decrease toward the bottom 42b, and the bottom 42b does not have to be pointed.
  • the opening width Wd of the recess 42dC of the coating layer 42C must not be an overhang shape having a portion that becomes larger toward the bottom 42bC. If electrolytic plating is performed to form the filling layer 43C in this state, the opening of the recess 42dC will be blocked, and a gap will be generated inside the via. If no additive is used, the recess 42dC will have an overhang shape as shown in FIG. 9, the via opening will be blocked first, and a void 4v will be generated.
  • the parts corresponding to the embodiment are distinguished by adding "C" to the end of the reference numeral.
  • the inside of the via 10v can be completely filled without any voids with a gold filling layer 43 formed by electrolytic plating and having a larger crystal grain size than the coating layer 42.
  • the inductor component of the via 10v is reduced, improving high frequency characteristics. Furthermore, an improvement of about 10% in heat dissipation is expected compared to hollow via structures, for example (R. Baskaran, Allen W. Hanson, CS MANTECH Conference (USA), May 18th-21st, 2015 "Simulation of the Impact of Through-Substrate Vias on the Thermal Resistance of Compound Semiconductor Devices”). Furthermore, because the coating layer 42 is made of gold, there is no concern about reduced electrical reliability due to copper contamination.
  • Embodiment 2 In the above-mentioned first embodiment, an example in which a portion covered with a coating layer remains on the rear surface of the wafer has been described. In the second embodiment, an example in which the coating layer is removed from the rear surface of the wafer will be described.
  • FIGS. 10 to 12 are used to explain the semiconductor device and the manufacturing method of the semiconductor device according to the second embodiment
  • FIG. 10 is a flow chart for explaining the manufacturing method of the semiconductor device.
  • FIG. 11 is an end view corresponding to FIG. 3 used to explain the configuration after the formation of the covering layer and before the formation of the filling layer in via filling of the semiconductor device
  • FIG. 12 is an end view corresponding to FIG. 1 used to explain the configuration of the via. Note that the same reference numerals are used for the same parts as in the first embodiment, and the description of the same parts is omitted, and FIG. 2 and FIG. 4 used in the first embodiment are used.
  • step S220V the formation of the coating layer 42
  • step S220V the formation of the gold coating layer 42 having the recess 42d opening on the back side as described in Fig. 4 of the first embodiment, so as to cover the back surface of the wafer.
  • step S220V a process of adjusting the coverage by removing the layer of the coating layer 42 and the seed layer 41 precipitated on the front surface (back surface of the wafer) by etching is added.
  • Dry etching or wet etching is used for the etching.
  • dry etching for example, argon ion milling is used.
  • dry etching titanium, gold, and platinum can be etched at the same time.
  • wet etching the chemical used is changed depending on the target layer to be removed. For example, an iodine-based chemical is used for gold, and for titanium, buffered hydrofluoric acid (BHF) or a mixture of ammonia (NH 3 ) and hydrogen peroxide (H 2 O 2 ) is used.
  • BHF buffered hydrofluoric acid
  • NH 3 ammonia
  • H 2 O 2 hydrogen peroxide
  • the seed layer 41 does not necessarily have to be etched.
  • the flat area on the backside of the wafer can have the surface of the gold base of the seed layer 41 (titanium and platinum in this example). Because a thicker layer of gold is deposited inside the through-holes than on the flat area, the surface is mainly gold.
  • a metal film 44 is formed on the coating layer 42 and the back surface of the wafer by sputtering as shown in FIG. 12 (step S225).
  • a titanium layer with a thickness of 50 nm and a gold layer with a thickness of 200 nm are used.
  • a filling layer 43 is formed by electrolytic gold plating to fill the recess 42d (step S230). Again, if the thickness of the filling layer 43 becomes too thick, etching may be performed until the desired thickness is reached. For dry etching, for example, argon ion milling or the like is used, and for wet etching, for example, iodine-based wet etching or the like is used.
  • the film thickness on the flat part of the back surface of the wafer becomes as thick as, for example, about 5 ⁇ m
  • the internal stress of the plating film becomes high, causing wafer warping and chip warping.
  • the plating film on the flat portion on the back surface of the wafer is etched back to reduce the gold thickness on the flat portion, thereby improving the above-mentioned problem.
  • the gold on the flat portion is removed, and if left as is, the electrical resistance of the flat portion increases, which interferes with the power supply in the next electrolytic plating process. Therefore, by forming the metal film 44 by sputtering or vapor deposition, it is possible to ensure the uniformity of the film and the filling characteristics in the via 10v in the electrolytic plating in the process of forming the filling layer 43 (step S230), in the same way as reconstructing the seed layer 41.
  • Embodiment 3 In the above-mentioned first and second embodiments, the manufacturing method and the crystal grain size are different, but the filling layer is made of the same gold as the covering layer. In the present embodiment 3, an example in which the filling layer is made of copper will be described.
  • FIG. 13 and 14 are intended to explain a semiconductor device according to the third embodiment and a method for manufacturing the semiconductor device, with FIG. 13 being an end view corresponding to FIG. 1 used to explain the configuration of the vias in the semiconductor device, and FIG. 14 being an end view corresponding to FIG. 13 to explain the configuration of the vias in the semiconductor device according to a modified example. Note that parts similar to those in the first embodiment are given the same reference numerals, and explanations of similar parts are omitted, with reference to FIGS. 2 to 4 used in the first embodiment.
  • the configuration of the coating layer 42 and the manufacturing method thereof are the same as those in the first embodiment.
  • the step of forming the filling layer 53 is performed by electrolytic plating, but the copper filling layer 53 is formed by electrolytic plating of copper (electrolytic copper plating) as shown in FIG. 13.
  • the inside of the via 10v can be completely filled without gaps together with the copper filling layer 53 formed by electrolytic plating.
  • the filling layer 53 is made of copper, CMP polishing can be performed without using special chemicals, making it easier to flatten the surface.
  • electrolytic plating additives that are more effective for filling vias have been developed for copper plating than for gold plating, making it easier to fill the recess 42d.
  • the inductor component of the via 10v is reduced, improving the high frequency characteristics.
  • the gold coating layer 42 acts as a copper diffusion barrier in addition to the conductive nitride film shown in Patent Document 2, improving the reliability of the device.
  • copper has better electrical and thermal conductivity than gold, so the device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved compared to when the filler 4 is made of gold alone.
  • the back surface of the wafer can be easily planarized, allowing three-dimensional device design in which the next layer is stacked on top of the planarized layer.
  • Embodiment 4 In the above-described third embodiment, an example was described in which the filling layer in the semiconductor device of the first embodiment is made of copper. In the fourth embodiment, an example is described in which the filling layer in the semiconductor device of the second embodiment is made of copper.
  • FIG. 15 and 16 are intended to explain the semiconductor device and the method of manufacturing the semiconductor device according to the fourth embodiment, with FIG. 15 being an end view corresponding to FIG. 12 used to explain the second embodiment and intended to explain the via configuration of the semiconductor device, and FIG. 16 being an end view corresponding to FIG. 15 and intended to explain the via configuration of the semiconductor device according to the modified example. Note that parts similar to those in the first and second embodiments are given the same reference numerals, and explanations of similar parts are omitted, with reference to FIGS. 2 and 4 used in the first embodiment and FIGS. 10 and 11 used in the second embodiment.
  • the configuration of the coating layer 42 and the manufacturing method thereof are the same as those in the second embodiment.
  • the step of forming the filling layer 53 is performed by electrolytic plating, but the copper filling layer 53 is formed by electrolytic plating of copper (electrolytic copper plating) as shown in FIG. 15.
  • the inside of the via 10v can be completely filled without gaps together with the copper filling layer 53 formed by electrolytic plating.
  • the filling layer 53 is made of copper, CMP polishing can be performed without using special chemicals, making it easier to flatten the surface.
  • electrolytic plating additives that are more effective for filling vias have been developed for copper plating than for gold plating, making it easier to fill the recess 42d.
  • the inductor component of the via 10v is reduced, improving the high frequency characteristics.
  • the gold coating layer 42 acts as a copper diffusion barrier in addition to the conductive nitride film, improving the reliability of the device.
  • copper has better electrical and thermal conductivity than gold, so the device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved compared to when the filler 4 is made of gold alone.
  • the back surface of the wafer can be easily planarized, allowing three-dimensional device design in which the next layer is stacked on top of the planarized layer.
  • Embodiment 5 In the above-described third and fourth embodiments, examples were described in which the composition of the filling layer was changed from gold to copper in comparison with the first and second embodiments. In the present fifth embodiment, an example will be described in which the composition of the filling layer is changed from gold to silver.
  • FIG. 17 and 18 are intended to explain the semiconductor device and the manufacturing method of the semiconductor device according to the fifth embodiment, with FIG. 17 being an end view corresponding to FIG. 1 used in the description of the first embodiment and illustrating the via configuration of the semiconductor device, and FIG. 18 being an end view corresponding to FIG. 12 used in the description of the second embodiment and illustrating the via configuration of the semiconductor device according to the modified example. Note that parts similar to those in the first and second embodiments are given the same reference numerals, and descriptions of similar parts are omitted, and FIG. 2 to FIG. 4 used in the first embodiment and FIG. 10 and FIG. 11 used in the second embodiment are used.
  • the configuration of the coating layer 42 and the manufacturing method thereof are the same as those in the first embodiment.
  • the step of forming the filling layer 63 involves electrolytic plating, but the filling layer 63 is formed of silver by electrolytic plating (electrolytic silver plating) as shown in FIG. 17.
  • the configuration of coating layer 42 and the manufacturing method thereof are the same as those in embodiment 2.
  • the step of forming filling layer 63 is performed by electrolytic plating, but by electrolytic plating of silver (electrolytic silver plating), to form filling layer 63 of silver, as shown in FIG.
  • a coating layer 42 having a recess 42d that tapers toward the bottom 42b is formed by electroless plating, and together with the silver filling layer 63 formed by electrolytic plating, the inside of the via 10v can be completely filled without gaps. Furthermore, in the fifth embodiment, since the filling layer 63 is made of silver, there is no need to worry about copper contamination as in the first and second embodiments, and there is no concern about a decrease in electrical reliability.
  • silver has better electrical and thermal conductivity than gold or copper, so the inductor component of via 10v is lower and the device characteristics (electrical characteristics, high frequency characteristics, thermal characteristics) are improved compared to when the filler 4 is made of gold alone or when the filler layer is made of copper.
  • Embodiment 6 In the above-mentioned embodiment 5, an example was described in which the composition of the filling layer was changed from gold to silver in comparison with embodiments 1 and 2. In the present embodiment 6, an example will be described in which the composition of the filling layer is changed from gold to nickel.
  • FIG. 19 and 20 are intended to explain the semiconductor device and the method of manufacturing the semiconductor device according to the sixth embodiment, with FIG. 19 being an end view corresponding to FIG. 1 used in the explanation of the first embodiment and illustrating the via configuration of the semiconductor device, and FIG. 20 being an end view corresponding to FIG. 12 used in the explanation of the second embodiment and illustrating the via configuration of the semiconductor device according to the modified example.
  • FIG. 2 to FIG. 4 used in the first embodiment and FIG. 10 and FIG. 11 used in the second embodiment are used.
  • the configuration of the coating layer 42 and the manufacturing method thereof are the same as in the first embodiment.
  • the step of forming the filling layer 73 is performed by electrolytic plating, but the nickel (Ni) filling layer 73 is formed by electrolytic plating (electrolytic nickel plating) as shown in FIG. 19.
  • the configuration of coating layer 42 and its manufacturing method are the same as those in the embodiment 2.
  • the step of forming filling layer 73 is performed by electrolytic plating, but by electrolytic plating of nickel (electrolytic nickel plating), to form nickel filling layer 73 as shown in FIG.
  • the inside of the via 10v can be completely filled without gaps with the silver filling layer 63 formed by electrolytic plating. Therefore, compared to the hollow case, it is expected that the high frequency characteristics will be improved by suppressing the heat dissipation and inductor components. Furthermore, in the sixth embodiment, since the filling layer 73 is made of nickel, there is no need to worry about copper contamination as in the first and second embodiments, and there is no concern about a decrease in electrical reliability.
  • the back surface of the high frequency device is die-bonded with gold-tin (AuSn) solder, silver-tin (SnAg) solder, etc., but when die-bonding to a gold or copper surface with solder, a thick alloy layer is formed at the interface, leading to poor conductivity, poor adhesion, and deterioration of thermal properties.
  • AuSn gold-tin
  • SnAg silver-tin
  • the nickel that constitutes the filling layer 73 at the gold and solder interface acts as a barrier layer, preventing these deteriorations in properties.
  • Embodiment 7 In the above-mentioned fifth and sixth embodiments, examples were described in which the composition of the filling layer was changed from gold to silver and nickel, as compared with the first and second embodiments. In the seventh embodiment, an example will be described in which the composition of the filling layer is changed from gold to tin.
  • FIG. 21 and 22 are intended to explain the semiconductor device and the method of manufacturing the semiconductor device according to the seventh embodiment, with FIG. 21 being an end view corresponding to FIG. 1 used in the explanation of the first embodiment and illustrating the via configuration of the semiconductor device, and FIG. 22 being an end view corresponding to FIG. 12 used in the explanation of the second embodiment and illustrating the via configuration of the semiconductor device according to the modified example. Note that parts similar to those in the first and second embodiments are given the same reference numerals, and explanations of similar parts are omitted, and FIG. 2 to FIG. 4 used in the first embodiment and FIG. 10 and FIG. 11 used in the second embodiment are used.
  • the configuration of the coating layer 42 and the manufacturing method thereof are the same as in the first embodiment.
  • the step of forming the filling layer 83 is performed by electrolytic plating, but the tin filling layer 83 is formed by electrolytic plating of tin (electrolytic tin plating) as shown in FIG. 21.
  • the configuration of coating layer 42 and the manufacturing method thereof are the same as those in the embodiment 2.
  • the step of forming filling layer 83 is performed by electrolytic plating, but by electrolytic plating of tin (electrolytic tin plating), to form tin filling layer 83 as shown in FIG.
  • the inside of the via 10v can be completely filled without gaps with the tin filling layer 83 formed by electrolytic plating. Therefore, compared to the hollow case, it is expected that the high frequency characteristics will be improved by suppressing the heat dissipation and inductor components. Furthermore, in the seventh embodiment, since the filling layer 83 is made of tin, there is no need to worry about copper contamination as in the first and second embodiments, and there is no concern about a decrease in electrical reliability.
  • the backside of the high frequency device is die-bonded using gold-tin (AuSn) solder, silver-tin (SnAg) solder, etc., but this eliminates the need to apply solder.
  • AuSn gold-tin
  • SnAg silver-tin
  • the semiconductor device 10 of the present application includes a substrate 1 made of a semiconductor material, a wiring member formed on one surface (the upper surface in the figure) of the substrate 1, a first plating layer (coating layer 42) made of gold that opens on the other surface of the substrate 1 and covers the inner wall of a cylindrical hole with the wiring member (surface electrode 3) as its bottom surface, and has a recess 42d recessed from the opening side toward the bottom surface, and a solid via 10v that has a second plating layer (filling layer 43, 53, 63, 73, 83) made of copper, silver, nickel, tin, or gold with a crystal grain size larger than that of the first plating layer (coating layer 42) that fills the recess 42d.
  • the recess 42d is configured to widen from the bottom surface toward the opening, it is possible to reliably obtain a semiconductor device with excellent electrical conductivity and heat dissipation without the generation of voids.
  • the thickness t42 of the first plating layer (coating layer 42) to the bottom surface of the recess is set to 1/4 or more of the thickness of the substrate (via height Hv), the occurrence of voids can be more reliably prevented.
  • a metal film 44 containing titanium, tantalum, tungsten, chromium, or platinum is provided between the first plating layer (coating layer 42) and the second plating layer (filling layer 43, 53, 63, 73, 83), the plating film of the filling layer 43 becomes uniform, and the embeddability in the via 10v is further improved.
  • the substrate 1 is made of silicon carbide, indium phosphide, gallium nitride, germanium silicide, germanium, or silicon, a semiconductor device with higher performance can be obtained.
  • the manufacturing method of the semiconductor device 10 of the present application includes the steps of forming a wiring member on one side of the substrate 1 of the semiconductor material, opening on the other side of the substrate 1 and forming a cylindrical hole with the wiring member (surface electrode 3) as the bottom (steps S100 to S200), forming a first gold plating layer (coating layer 42) by electroless plating so as to cover the inner wall of the cylindrical hole and form a recess 42d recessed from the opening side toward the bottom (steps S220, S220V), and forming a second plating layer (filling layer 43) of copper, silver, nickel, tin, or gold by electrolytic plating so as to fill the recess 42d (step S230).
  • step S225 of forming a metal film 44 that covers the inner surface of the recess 42d by sputtering or vapor deposition, the plating film will be uniform when the filling layer 43 is formed by electrolytic plating, and the embeddability of the via 10v will be improved.

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WO2025109755A1 (ja) * 2023-11-24 2025-05-30 三菱電機株式会社 半導体装置およびその製造方法

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JPH05102200A (ja) * 1991-10-03 1993-04-23 Mitsubishi Electric Corp 半導体装置
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JP2022070436A (ja) * 2020-10-27 2022-05-13 富士通株式会社 半導体装置及びその製造方法

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JPH05102200A (ja) * 1991-10-03 1993-04-23 Mitsubishi Electric Corp 半導体装置
JP2014112634A (ja) * 2012-10-30 2014-06-19 Mitsubishi Electric Corp 半導体素子の製造方法、半導体素子
JP2022070436A (ja) * 2020-10-27 2022-05-13 富士通株式会社 半導体装置及びその製造方法

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CN121076034B (zh) * 2025-11-04 2026-03-10 深圳市联合蓝海应用材料科技股份有限公司 一种化合物半导体背孔器件及其制备方法和晶体管

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