JPWO2023106105A5 - - Google Patents

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Publication number
JPWO2023106105A5
JPWO2023106105A5 JP2023566218A JP2023566218A JPWO2023106105A5 JP WO2023106105 A5 JPWO2023106105 A5 JP WO2023106105A5 JP 2023566218 A JP2023566218 A JP 2023566218A JP 2023566218 A JP2023566218 A JP 2023566218A JP WO2023106105 A5 JPWO2023106105 A5 JP WO2023106105A5
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JP
Japan
Prior art keywords
signal
power supply
transistor
supply line
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023566218A
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English (en)
Japanese (ja)
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JPWO2023106105A1 (https=
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Publication date
Application filed filed Critical
Priority claimed from PCT/JP2022/043303 external-priority patent/WO2023106105A1/ja
Publication of JPWO2023106105A1 publication Critical patent/JPWO2023106105A1/ja
Publication of JPWO2023106105A5 publication Critical patent/JPWO2023106105A5/ja
Pending legal-status Critical Current

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JP2023566218A 2021-12-08 2022-11-24 Pending JPWO2023106105A1 (https=)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021199650 2021-12-08
PCT/JP2022/043303 WO2023106105A1 (ja) 2021-12-08 2022-11-24 半導体記憶装置及び制御方法

Publications (2)

Publication Number Publication Date
JPWO2023106105A1 JPWO2023106105A1 (https=) 2023-06-15
JPWO2023106105A5 true JPWO2023106105A5 (https=) 2024-08-22

Family

ID=86730412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023566218A Pending JPWO2023106105A1 (https=) 2021-12-08 2022-11-24

Country Status (5)

Country Link
US (1) US20240304222A1 (https=)
JP (1) JPWO2023106105A1 (https=)
CN (1) CN118355443A (https=)
TW (1) TW202324410A (https=)
WO (1) WO2023106105A1 (https=)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227804B1 (en) * 2004-04-19 2007-06-05 Cypress Semiconductor Corporation Current source architecture for memory device standby current reduction
KR100610021B1 (ko) * 2005-01-14 2006-08-08 삼성전자주식회사 반도체 메모리 장치에서의 비트라인 전압 공급회로와 그에따른 비트라인 전압 인가방법
US7489167B2 (en) * 2006-04-26 2009-02-10 Infineon Technologies Ag Voltage detection and sequencing circuit
KR100806127B1 (ko) * 2006-09-06 2008-02-22 삼성전자주식회사 피크 커런트를 감소시키는 파워 게이팅 회로 및 파워게이팅 방법
US7751267B2 (en) * 2007-07-24 2010-07-06 International Business Machines Corporation Half-select compliant memory cell precharge circuit
JP5246123B2 (ja) * 2009-01-29 2013-07-24 富士通セミコンダクター株式会社 半導体記憶装置、半導体装置及び電子機器
JP2011123970A (ja) * 2009-12-14 2011-06-23 Renesas Electronics Corp 半導体記憶装置
GB2500907B (en) * 2012-04-04 2016-05-25 Platipus Ltd Static random access memory devices

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