JPWO2023106105A1 - - Google Patents
Info
- Publication number
- JPWO2023106105A1 JPWO2023106105A1 JP2023566218A JP2023566218A JPWO2023106105A1 JP WO2023106105 A1 JPWO2023106105 A1 JP WO2023106105A1 JP 2023566218 A JP2023566218 A JP 2023566218A JP 2023566218 A JP2023566218 A JP 2023566218A JP WO2023106105 A1 JPWO2023106105 A1 JP WO2023106105A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021199650 | 2021-12-08 | ||
| PCT/JP2022/043303 WO2023106105A1 (ja) | 2021-12-08 | 2022-11-24 | 半導体記憶装置及び制御方法 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPWO2023106105A1 true JPWO2023106105A1 (https=) | 2023-06-15 |
| JPWO2023106105A5 JPWO2023106105A5 (https=) | 2024-08-22 |
Family
ID=86730412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023566218A Pending JPWO2023106105A1 (https=) | 2021-12-08 | 2022-11-24 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20240304222A1 (https=) |
| JP (1) | JPWO2023106105A1 (https=) |
| CN (1) | CN118355443A (https=) |
| TW (1) | TW202324410A (https=) |
| WO (1) | WO2023106105A1 (https=) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7227804B1 (en) * | 2004-04-19 | 2007-06-05 | Cypress Semiconductor Corporation | Current source architecture for memory device standby current reduction |
| KR100610021B1 (ko) * | 2005-01-14 | 2006-08-08 | 삼성전자주식회사 | 반도체 메모리 장치에서의 비트라인 전압 공급회로와 그에따른 비트라인 전압 인가방법 |
| US7489167B2 (en) * | 2006-04-26 | 2009-02-10 | Infineon Technologies Ag | Voltage detection and sequencing circuit |
| KR100806127B1 (ko) * | 2006-09-06 | 2008-02-22 | 삼성전자주식회사 | 피크 커런트를 감소시키는 파워 게이팅 회로 및 파워게이팅 방법 |
| US7751267B2 (en) * | 2007-07-24 | 2010-07-06 | International Business Machines Corporation | Half-select compliant memory cell precharge circuit |
| JP5246123B2 (ja) * | 2009-01-29 | 2013-07-24 | 富士通セミコンダクター株式会社 | 半導体記憶装置、半導体装置及び電子機器 |
| JP2011123970A (ja) * | 2009-12-14 | 2011-06-23 | Renesas Electronics Corp | 半導体記憶装置 |
| GB2500907B (en) * | 2012-04-04 | 2016-05-25 | Platipus Ltd | Static random access memory devices |
-
2022
- 2022-11-23 TW TW111144814A patent/TW202324410A/zh unknown
- 2022-11-24 JP JP2023566218A patent/JPWO2023106105A1/ja active Pending
- 2022-11-24 CN CN202280080399.1A patent/CN118355443A/zh active Pending
- 2022-11-24 WO PCT/JP2022/043303 patent/WO2023106105A1/ja not_active Ceased
-
2024
- 2024-05-21 US US18/670,302 patent/US20240304222A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US20240304222A1 (en) | 2024-09-12 |
| TW202324410A (zh) | 2023-06-16 |
| WO2023106105A1 (ja) | 2023-06-15 |
| CN118355443A (zh) | 2024-07-16 |
Similar Documents
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20240501 |
|
| A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20251117 |