TW202324410A - 半導體記憶裝置及控制方法 - Google Patents

半導體記憶裝置及控制方法 Download PDF

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Publication number
TW202324410A
TW202324410A TW111144814A TW111144814A TW202324410A TW 202324410 A TW202324410 A TW 202324410A TW 111144814 A TW111144814 A TW 111144814A TW 111144814 A TW111144814 A TW 111144814A TW 202324410 A TW202324410 A TW 202324410A
Authority
TW
Taiwan
Prior art keywords
transistor
circuit
mode
signal
aforementioned
Prior art date
Application number
TW111144814A
Other languages
English (en)
Chinese (zh)
Inventor
本谷篤志
Original Assignee
日商新唐科技日本股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商新唐科技日本股份有限公司 filed Critical 日商新唐科技日本股份有限公司
Publication of TW202324410A publication Critical patent/TW202324410A/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
TW111144814A 2021-12-08 2022-11-23 半導體記憶裝置及控制方法 TW202324410A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2021199650 2021-12-08
JP2021-199650 2021-12-08

Publications (1)

Publication Number Publication Date
TW202324410A true TW202324410A (zh) 2023-06-16

Family

ID=86730412

Family Applications (1)

Application Number Title Priority Date Filing Date
TW111144814A TW202324410A (zh) 2021-12-08 2022-11-23 半導體記憶裝置及控制方法

Country Status (5)

Country Link
US (1) US20240304222A1 (https=)
JP (1) JPWO2023106105A1 (https=)
CN (1) CN118355443A (https=)
TW (1) TW202324410A (https=)
WO (1) WO2023106105A1 (https=)

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7227804B1 (en) * 2004-04-19 2007-06-05 Cypress Semiconductor Corporation Current source architecture for memory device standby current reduction
KR100610021B1 (ko) * 2005-01-14 2006-08-08 삼성전자주식회사 반도체 메모리 장치에서의 비트라인 전압 공급회로와 그에따른 비트라인 전압 인가방법
US7489167B2 (en) * 2006-04-26 2009-02-10 Infineon Technologies Ag Voltage detection and sequencing circuit
KR100806127B1 (ko) * 2006-09-06 2008-02-22 삼성전자주식회사 피크 커런트를 감소시키는 파워 게이팅 회로 및 파워게이팅 방법
US7751267B2 (en) * 2007-07-24 2010-07-06 International Business Machines Corporation Half-select compliant memory cell precharge circuit
JP5246123B2 (ja) * 2009-01-29 2013-07-24 富士通セミコンダクター株式会社 半導体記憶装置、半導体装置及び電子機器
JP2011123970A (ja) * 2009-12-14 2011-06-23 Renesas Electronics Corp 半導体記憶装置
GB2500907B (en) * 2012-04-04 2016-05-25 Platipus Ltd Static random access memory devices

Also Published As

Publication number Publication date
JPWO2023106105A1 (https=) 2023-06-15
US20240304222A1 (en) 2024-09-12
WO2023106105A1 (ja) 2023-06-15
CN118355443A (zh) 2024-07-16

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TW202324410A (zh) 半導體記憶裝置及控制方法