CN118355443A - 半导体存储装置以及控制方法 - Google Patents
半导体存储装置以及控制方法 Download PDFInfo
- Publication number
- CN118355443A CN118355443A CN202280080399.1A CN202280080399A CN118355443A CN 118355443 A CN118355443 A CN 118355443A CN 202280080399 A CN202280080399 A CN 202280080399A CN 118355443 A CN118355443 A CN 118355443A
- Authority
- CN
- China
- Prior art keywords
- transistor
- mode
- circuit
- signal
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 102
- 238000003860 storage Methods 0.000 title claims description 54
- 238000000034 method Methods 0.000 title claims description 36
- 210000004027 cell Anatomy 0.000 claims description 82
- 210000000352 storage cell Anatomy 0.000 claims description 24
- 238000010586 diagram Methods 0.000 description 15
- 238000012986 modification Methods 0.000 description 14
- 230000004048 modification Effects 0.000 description 14
- 238000001514 detection method Methods 0.000 description 10
- 230000006870 function Effects 0.000 description 10
- 238000011084 recovery Methods 0.000 description 7
- 239000000470 constituent Substances 0.000 description 5
- 230000002093 peripheral effect Effects 0.000 description 5
- 101001121408 Homo sapiens L-amino-acid oxidase Proteins 0.000 description 2
- 102100026388 L-amino-acid oxidase Human genes 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 101100012902 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) FIG2 gene Proteins 0.000 description 1
- 101100233916 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) KAR5 gene Proteins 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/148—Details of power up or power down circuits, standby circuits or recovery circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021199650 | 2021-12-08 | ||
| JP2021-199650 | 2021-12-08 | ||
| PCT/JP2022/043303 WO2023106105A1 (ja) | 2021-12-08 | 2022-11-24 | 半導体記憶装置及び制御方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118355443A true CN118355443A (zh) | 2024-07-16 |
Family
ID=86730412
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202280080399.1A Pending CN118355443A (zh) | 2021-12-08 | 2022-11-24 | 半导体存储装置以及控制方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20240304222A1 (https=) |
| JP (1) | JPWO2023106105A1 (https=) |
| CN (1) | CN118355443A (https=) |
| TW (1) | TW202324410A (https=) |
| WO (1) | WO2023106105A1 (https=) |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7227804B1 (en) * | 2004-04-19 | 2007-06-05 | Cypress Semiconductor Corporation | Current source architecture for memory device standby current reduction |
| KR100610021B1 (ko) * | 2005-01-14 | 2006-08-08 | 삼성전자주식회사 | 반도체 메모리 장치에서의 비트라인 전압 공급회로와 그에따른 비트라인 전압 인가방법 |
| US7489167B2 (en) * | 2006-04-26 | 2009-02-10 | Infineon Technologies Ag | Voltage detection and sequencing circuit |
| KR100806127B1 (ko) * | 2006-09-06 | 2008-02-22 | 삼성전자주식회사 | 피크 커런트를 감소시키는 파워 게이팅 회로 및 파워게이팅 방법 |
| US7751267B2 (en) * | 2007-07-24 | 2010-07-06 | International Business Machines Corporation | Half-select compliant memory cell precharge circuit |
| JP5246123B2 (ja) * | 2009-01-29 | 2013-07-24 | 富士通セミコンダクター株式会社 | 半導体記憶装置、半導体装置及び電子機器 |
| JP2011123970A (ja) * | 2009-12-14 | 2011-06-23 | Renesas Electronics Corp | 半導体記憶装置 |
| GB2500907B (en) * | 2012-04-04 | 2016-05-25 | Platipus Ltd | Static random access memory devices |
-
2022
- 2022-11-23 TW TW111144814A patent/TW202324410A/zh unknown
- 2022-11-24 JP JP2023566218A patent/JPWO2023106105A1/ja active Pending
- 2022-11-24 CN CN202280080399.1A patent/CN118355443A/zh active Pending
- 2022-11-24 WO PCT/JP2022/043303 patent/WO2023106105A1/ja not_active Ceased
-
2024
- 2024-05-21 US US18/670,302 patent/US20240304222A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| JPWO2023106105A1 (https=) | 2023-06-15 |
| US20240304222A1 (en) | 2024-09-12 |
| TW202324410A (zh) | 2023-06-16 |
| WO2023106105A1 (ja) | 2023-06-15 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |