JPWO2022219720A5 - - Google Patents

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Publication number
JPWO2022219720A5
JPWO2022219720A5 JP2023514225A JP2023514225A JPWO2022219720A5 JP WO2022219720 A5 JPWO2022219720 A5 JP WO2022219720A5 JP 2023514225 A JP2023514225 A JP 2023514225A JP 2023514225 A JP2023514225 A JP 2023514225A JP WO2022219720 A5 JPWO2022219720 A5 JP WO2022219720A5
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JP
Japan
Prior art keywords
current source
nmos transistor
flip
circuit
flop
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JP2023514225A
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English (en)
Japanese (ja)
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JP7558396B2 (ja
JPWO2022219720A1 (https=
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Priority claimed from PCT/JP2021/015331 external-priority patent/WO2022219720A1/ja
Publication of JPWO2022219720A1 publication Critical patent/JPWO2022219720A1/ja
Publication of JPWO2022219720A5 publication Critical patent/JPWO2022219720A5/ja
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Publication of JP7558396B2 publication Critical patent/JP7558396B2/ja
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JP2023514225A 2021-04-13 2021-04-13 半導体集積回路および半導体装置 Active JP7558396B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/015331 WO2022219720A1 (ja) 2021-04-13 2021-04-13 半導体集積回路および半導体装置

Publications (3)

Publication Number Publication Date
JPWO2022219720A1 JPWO2022219720A1 (https=) 2022-10-20
JPWO2022219720A5 true JPWO2022219720A5 (https=) 2024-01-17
JP7558396B2 JP7558396B2 (ja) 2024-09-30

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ID=83639918

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Application Number Title Priority Date Filing Date
JP2023514225A Active JP7558396B2 (ja) 2021-04-13 2021-04-13 半導体集積回路および半導体装置

Country Status (3)

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US (1) US12556168B2 (https=)
JP (1) JP7558396B2 (https=)
WO (1) WO2022219720A1 (https=)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3166281B2 (ja) * 1992-04-14 2001-05-14 株式会社日立製作所 半導体集積回路及びその製造方法
JPH0737956A (ja) 1993-07-26 1995-02-07 Nippon Telegr & Teleph Corp <Ntt> Ｃｍｏｓ型集積回路およびその検査方法
JP3641517B2 (ja) 1995-10-05 2005-04-20 株式会社ルネサステクノロジ 半導体装置
US7643576B2 (en) * 2004-05-18 2010-01-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Data-signal-recovery circuit, data-signal-characterizing circuit, and related integrated circuits, systems, and methods
JP2009513968A (ja) * 2005-10-26 2009-04-02 エヌエックスピー ビー ヴィ テスト機構を有するアナログｉｃ及びｉｃテスト方法
JP2007178345A (ja) 2005-12-28 2007-07-12 Sharp Corp 半導体集積回路、および、半導体集積回路のテストシステム
JP4592670B2 (ja) * 2006-10-23 2010-12-01 パナソニック株式会社 集積回路素子
JP2009085877A (ja) 2007-10-02 2009-04-23 Nec Saitama Ltd 複数の回路ブロックを搭載したｌｓｉの消費電流測定方式およびｌｓｉ
JP5435081B2 (ja) * 2012-05-25 2014-03-05 富士通株式会社 半導体装置
JP6242183B2 (ja) * 2013-11-22 2017-12-06 株式会社メガチップス 半導体集積回路及び該半導体集積回路の試験方法並びに該半導体集積回路におけるラッシュカレントの抑制方法
US10101403B2 (en) * 2014-07-02 2018-10-16 Intersil Americas LLC Systems and methods for an open wire scan
CN111108398A (zh) * 2017-09-29 2020-05-05 勃林格殷格翰维特梅迪卡有限公司 电路布置的测试和校准

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