JPWO2022219720A1 - - Google Patents

Info

Publication number
JPWO2022219720A1
JPWO2022219720A1 JP2023514225A JP2023514225A JPWO2022219720A1 JP WO2022219720 A1 JPWO2022219720 A1 JP WO2022219720A1 JP 2023514225 A JP2023514225 A JP 2023514225A JP 2023514225 A JP2023514225 A JP 2023514225A JP WO2022219720 A1 JPWO2022219720 A1 JP WO2022219720A1
Authority
JP
Japan
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2023514225A
Other languages
Japanese (ja)
Other versions
JP7558396B2 (ja
JPWO2022219720A5 (https=
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of JPWO2022219720A1 publication Critical patent/JPWO2022219720A1/ja
Publication of JPWO2022219720A5 publication Critical patent/JPWO2022219720A5/ja
Application granted granted Critical
Publication of JP7558396B2 publication Critical patent/JP7558396B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/353Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
    • H03K3/356Bistable circuits
    • H03K3/356017Bistable circuits using additional transistors in the input circuit
    • H03K3/356034Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
    • H03K3/356043Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003Modifications for increasing the reliability for protection
    • H03K19/00369Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01Details
    • H03K3/014Modifications of generator to ensure starting of oscillations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037Bistable circuits
    • H03K3/0375Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2023514225A 2021-04-13 2021-04-13 半導体集積回路および半導体装置 Active JP7558396B2 (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2021/015331 WO2022219720A1 (ja) 2021-04-13 2021-04-13 半導体集積回路および半導体装置

Publications (3)

Publication Number Publication Date
JPWO2022219720A1 true JPWO2022219720A1 (https=) 2022-10-20
JPWO2022219720A5 JPWO2022219720A5 (https=) 2024-01-17
JP7558396B2 JP7558396B2 (ja) 2024-09-30

Family

ID=83639918

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023514225A Active JP7558396B2 (ja) 2021-04-13 2021-04-13 半導体集積回路および半導体装置

Country Status (3)

Country Link
US (1) US12556168B2 (https=)
JP (1) JP7558396B2 (https=)
WO (1) WO2022219720A1 (https=)

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3166281B2 (ja) * 1992-04-14 2001-05-14 株式会社日立製作所 半導体集積回路及びその製造方法
JPH0737956A (ja) 1993-07-26 1995-02-07 Nippon Telegr & Teleph Corp <Ntt> Cmos型集積回路およびその検査方法
JP3641517B2 (ja) 1995-10-05 2005-04-20 株式会社ルネサステクノロジ 半導体装置
US7643576B2 (en) * 2004-05-18 2010-01-05 Avago Technologies General Ip (Singapore) Pte. Ltd. Data-signal-recovery circuit, data-signal-characterizing circuit, and related integrated circuits, systems, and methods
JP2009513968A (ja) * 2005-10-26 2009-04-02 エヌエックスピー ビー ヴィ テスト機構を有するアナログic及びicテスト方法
JP2007178345A (ja) 2005-12-28 2007-07-12 Sharp Corp 半導体集積回路、および、半導体集積回路のテストシステム
JP4592670B2 (ja) * 2006-10-23 2010-12-01 パナソニック株式会社 集積回路素子
JP2009085877A (ja) 2007-10-02 2009-04-23 Nec Saitama Ltd 複数の回路ブロックを搭載したlsiの消費電流測定方式およびlsi
JP5435081B2 (ja) * 2012-05-25 2014-03-05 富士通株式会社 半導体装置
JP6242183B2 (ja) * 2013-11-22 2017-12-06 株式会社メガチップス 半導体集積回路及び該半導体集積回路の試験方法並びに該半導体集積回路におけるラッシュカレントの抑制方法
US10101403B2 (en) * 2014-07-02 2018-10-16 Intersil Americas LLC Systems and methods for an open wire scan
CN111108398A (zh) * 2017-09-29 2020-05-05 勃林格殷格翰维特梅迪卡有限公司 电路布置的测试和校准

Also Published As

Publication number Publication date
JP7558396B2 (ja) 2024-09-30
US12556168B2 (en) 2026-02-17
WO2022219720A1 (ja) 2022-10-20
US20240162894A1 (en) 2024-05-16

Similar Documents

Publication Publication Date Title
BR112023005462A2 (https=)
BR112023012656A2 (https=)
BR112023009656A2 (https=)
BR112021017747A2 (https=)
BR112023011738A2 (https=)
BR112023004146A2 (https=)
BR112023006729A2 (https=)
BR102021018859A2 (https=)
BR102021015500A2 (https=)
BR102021007058A2 (https=)
BR112023016292A2 (https=)
BR112023011539A2 (https=)
BR112023011610A2 (https=)
BR112023008976A2 (https=)
BR102021020147A2 (https=)
BR102021018926A2 (https=)
BR102021018167A2 (https=)
BR102021017576A2 (https=)
BR102021016837A2 (https=)
BR102021016551A2 (https=)
BR102021016375A2 (https=)
BR102021016176A2 (https=)
BR102021016200A2 (https=)
BR102021015566A2 (https=)
BR102021015450A8 (https=)

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20231003

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20231003

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20240820

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20240917

R150 Certificate of patent or registration of utility model

Ref document number: 7558396

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150