JPWO2022219720A1 - - Google Patents
Info
- Publication number
- JPWO2022219720A1 JPWO2022219720A1 JP2023514225A JP2023514225A JPWO2022219720A1 JP WO2022219720 A1 JPWO2022219720 A1 JP WO2022219720A1 JP 2023514225 A JP2023514225 A JP 2023514225A JP 2023514225 A JP2023514225 A JP 2023514225A JP WO2022219720 A1 JPWO2022219720 A1 JP WO2022219720A1
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/353—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of field-effect transistors with internal or external positive feedback
- H03K3/356—Bistable circuits
- H03K3/356017—Bistable circuits using additional transistors in the input circuit
- H03K3/356034—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration
- H03K3/356043—Bistable circuits using additional transistors in the input circuit the input circuit having a differential configuration with synchronous operation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/014—Modifications of generator to ensure starting of oscillations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
- H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
- H03K3/037—Bistable circuits
- H03K3/0375—Bistable circuits provided with means for increasing reliability; for protection; for ensuring a predetermined initial state when the supply voltage has been applied; for storing the actual state when the supply voltage fails
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- Mathematical Physics (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/JP2021/015331 WO2022219720A1 (ja) | 2021-04-13 | 2021-04-13 | 半導体集積回路および半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPWO2022219720A1 true JPWO2022219720A1 (https=) | 2022-10-20 |
| JPWO2022219720A5 JPWO2022219720A5 (https=) | 2024-01-17 |
| JP7558396B2 JP7558396B2 (ja) | 2024-09-30 |
Family
ID=83639918
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023514225A Active JP7558396B2 (ja) | 2021-04-13 | 2021-04-13 | 半導体集積回路および半導体装置 |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US12556168B2 (https=) |
| JP (1) | JP7558396B2 (https=) |
| WO (1) | WO2022219720A1 (https=) |
Family Cites Families (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3166281B2 (ja) * | 1992-04-14 | 2001-05-14 | 株式会社日立製作所 | 半導体集積回路及びその製造方法 |
| JPH0737956A (ja) | 1993-07-26 | 1995-02-07 | Nippon Telegr & Teleph Corp <Ntt> | Cmos型集積回路およびその検査方法 |
| JP3641517B2 (ja) | 1995-10-05 | 2005-04-20 | 株式会社ルネサステクノロジ | 半導体装置 |
| US7643576B2 (en) * | 2004-05-18 | 2010-01-05 | Avago Technologies General Ip (Singapore) Pte. Ltd. | Data-signal-recovery circuit, data-signal-characterizing circuit, and related integrated circuits, systems, and methods |
| JP2009513968A (ja) * | 2005-10-26 | 2009-04-02 | エヌエックスピー ビー ヴィ | テスト機構を有するアナログic及びicテスト方法 |
| JP2007178345A (ja) | 2005-12-28 | 2007-07-12 | Sharp Corp | 半導体集積回路、および、半導体集積回路のテストシステム |
| JP4592670B2 (ja) * | 2006-10-23 | 2010-12-01 | パナソニック株式会社 | 集積回路素子 |
| JP2009085877A (ja) | 2007-10-02 | 2009-04-23 | Nec Saitama Ltd | 複数の回路ブロックを搭載したlsiの消費電流測定方式およびlsi |
| JP5435081B2 (ja) * | 2012-05-25 | 2014-03-05 | 富士通株式会社 | 半導体装置 |
| JP6242183B2 (ja) * | 2013-11-22 | 2017-12-06 | 株式会社メガチップス | 半導体集積回路及び該半導体集積回路の試験方法並びに該半導体集積回路におけるラッシュカレントの抑制方法 |
| US10101403B2 (en) * | 2014-07-02 | 2018-10-16 | Intersil Americas LLC | Systems and methods for an open wire scan |
| CN111108398A (zh) * | 2017-09-29 | 2020-05-05 | 勃林格殷格翰维特梅迪卡有限公司 | 电路布置的测试和校准 |
-
2021
- 2021-04-13 JP JP2023514225A patent/JP7558396B2/ja active Active
- 2021-04-13 US US18/551,014 patent/US12556168B2/en active Active
- 2021-04-13 WO PCT/JP2021/015331 patent/WO2022219720A1/ja not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| JP7558396B2 (ja) | 2024-09-30 |
| US12556168B2 (en) | 2026-02-17 |
| WO2022219720A1 (ja) | 2022-10-20 |
| US20240162894A1 (en) | 2024-05-16 |
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