JPWO2019234561A1 - 半導体装置、および半導体装置の作製方法 - Google Patents
半導体装置、および半導体装置の作製方法 Download PDFInfo
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- JPWO2019234561A1 JPWO2019234561A1 JP2020523842A JP2020523842A JPWO2019234561A1 JP WO2019234561 A1 JPWO2019234561 A1 JP WO2019234561A1 JP 2020523842 A JP2020523842 A JP 2020523842A JP 2020523842 A JP2020523842 A JP 2020523842A JP WO2019234561 A1 JPWO2019234561 A1 JP WO2019234561A1
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- oxygen
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Images
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Abstract
Description
本発明の一態様は、酸化物半導体として機能する金属酸化物(単に酸化物と呼ぶ場合がある)を有する半導体装置、およびその作製方法に関する。
以下に、本発明に係る酸化物半導体について説明する。酸化物半導体は、少なくともインジウムまたは亜鉛を含むことが好ましい。特にインジウムおよび亜鉛を含むことが好ましい。また、それらに加えて、アルミニウム、ガリウム、イットリウムまたばスズなどが含まれていることが好ましい。また、ホウ素、シリコン、チタン、鉄、ニッケル、ゲルマニウム、ジルコニウム、モリブデン、ランタン、セリウム、ネオジム、ハフニウム、タンタル、タングステン、またはマグネシウムなどから選ばれた一種、または複数種が含まれていてもよい。
ここで、本発明の一態様の金属酸化物の形成に用いることができるALD装置、およびALD法を用いた成膜方法について説明する。
以下では、本発明の一態様で開示されるトランジスタに用いることができるCAC(Cloud−Aligned Composite)−OSの構成について説明する。
酸化物半導体(金属酸化物)は、単結晶酸化物半導体と、それ以外の非単結晶酸化物半導体と、に分けられる。非単結晶酸化物半導体としては、例えば、CAAC−OS、多結晶酸化物半導体、nc−OS、擬似非晶質酸化物半導体(a−like OS:amorphous−like oxide semiconductor)、および非晶質酸化物半導体などがある。
ここで、金属酸化物中における各不純物の影響について説明する。
成膜装置4000は、搬入搬出室4002と、搬入搬出室4004と、搬送室4006と、成膜室4008と、成膜室4009と、成膜室4010と、搬送アーム4014と、を有する。ここで、搬入搬出室4002、搬入搬出室4004、及び成膜室4008乃至4010は、搬送室4006とそれぞれ独立に接続されている。これにより、成膜室4008乃至4010において大気に曝すことなく、連続成膜を行うことができ、膜中に不純物が混入するのを防ぐことができる。また、基板と膜の界面、および各膜の界面の汚染は低減され、清浄な界面が得られる。
次に、成膜装置4000に用いることができるALD装置の構成について、図4(B)を用いて説明する。ALD装置は、成膜室(チャンバー4020)と、原料供給部4021(原料供給部4021a、および4021b)、原料供給部4031と、導入量制御器である高速バルブ4022a、4022bと、原料導入口4023(原料導入口4023a、および4023b)、原料導入口4033と、原料排出口4024と、排気装置4025を有する。チャンバー4020内に設置される原料導入口4023a、4023b、および4033は供給管やバルブを介して原料供給部4021a、4021b、および4031とそれぞれ接続されており、原料排出口4024は、排出管やバルブや圧力調整器を介して排気装置4025と接続されている。
図6(A)に、図4(B)に示すALD装置を用いた成膜シーケンスを示す。まず、チャンバー4020内の基板ホルダ4026に基板4030をセットする(S101)。次に、ヒータ4027の温度調節を行う(S102)。次に、基板4030の温度が基板面内で一様になるように基板4030を基板ホルダ4026上で保持する(S103)。次に、前述の第1ステップ乃至第4ステップにより、成膜を行う。すなわち、チャンバー4020に第1の原料ガス、および第2の原料ガスを交互に導入し、基板4030上に成膜を行う(S104)。また、S103とS104の間に、チャンバー4020内部を酸素雰囲気にする処理を行ってもよい。基板4030のセット、および保持後に、チャンバー4020内部を酸素雰囲気とすることで、基板4030および基板4030上に設けられた膜に酸素を添加できる場合がある。また、成膜前の基板4030および基板4030上に設けられた膜から水素を脱離できる場合がある。基板4030中、または膜中の水素が、基板4030中、または膜中に添加された酸素と反応し、水(H2O)となって基板4030、または膜から離脱する場合がある。
本実施の形態では、本発明の一態様に係るトランジスタ200を有する半導体装置の一例について説明する。
図8は、本発明の一態様に係るトランジスタ200、およびトランジスタ200周辺の上面図および断面図である。
図8に示すように、トランジスタ200は、基板(図示せず。)の上に配置され、絶縁体216に埋め込まれるように配置された導電体205と、絶縁体216の上および導電体205の上に配置された絶縁体222と、絶縁体222の上に配置された絶縁体224と、絶縁体224の上に配置された酸化物230(酸化物230a、酸化物230b、および酸化物230c(酸化物230c1、および酸化物230c2))と、酸化物230の上に配置された絶縁体250と、絶縁体250上に配置された導電体260(導電体260a、および導電体260b)と、酸化物230bの上面の一部と接する導電体242aおよび導電体242bと、絶縁体224の上面の一部、酸化物230aの側面、酸化物230bの側面、導電体242aの側面、導電体242aの上面、導電体242bの側面、および導電体242bの上面に接して配置された絶縁体254と、を有する。
以下では、半導体装置に用いることができる構成材料について説明する。
トランジスタ200を形成する基板としては、例えば、絶縁体基板、半導体基板、または導電体基板を用いればよい。絶縁体基板としては、例えば、ガラス基板、石英基板、サファイア基板、安定化ジルコニア基板(イットリア安定化ジルコニア基板など)、樹脂基板などがある。また、半導体基板としては、例えば、シリコン、ゲルマニウムなどを材料とした半導体基板、または炭化シリコン、シリコンゲルマニウム、ヒ化ガリウム、リン化インジウム、酸化亜鉛、酸化ガリウムからなる化合物半導体基板などがある。さらには、前述の半導体基板内部に絶縁体領域を有する半導体基板、例えば、SOI(Silicon On Insulator)基板などがある。導電体基板としては、黒鉛基板、金属基板、合金基板、導電性樹脂基板などがある。または、金属の窒化物を有する基板、金属の酸化物を有する基板などがある。さらには、絶縁体基板に導電体または半導体が設けられた基板、半導体基板に導電体または絶縁体が設けられた基板、導電体基板に半導体または絶縁体が設けられた基板などがある。または、これらの基板に素子が設けられたものを用いてもよい。基板に設けられる素子としては、容量素子、抵抗素子、スイッチ素子、発光素子、記憶素子などがある。
絶縁体としては、絶縁性を有する酸化物、窒化物、酸化窒化物、窒化酸化物、金属酸化物、金属酸化窒化物、金属窒化酸化物などがある。
導電体としては、アルミニウム、クロム、銅、銀、金、白金、タンタル、ニッケル、チタン、モリブデン、タングステン、ハフニウム、バナジウム、ニオブ、マンガン、マグネシウム、ジルコニウム、ベリリウム、インジウム、ルテニウム、イリジウム、ストロンチウム、ランタンなどから選ばれた金属元素、または上述した金属元素を成分とする合金か、上述した金属元素を組み合わせた合金等を用いることが好ましい。例えば、窒化タンタル、窒化チタン、タングステン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物などを用いることが好ましい。また、窒化タンタル、窒化チタン、チタンとアルミニウムを含む窒化物、タンタルとアルミニウムを含む窒化物、酸化ルテニウム、窒化ルテニウム、ストロンチウムとルテニウムを含む酸化物、ランタンとニッケルを含む酸化物は、酸化しにくい導電性材料、または、酸素を吸収しても導電性を維持する材料であるため、好ましい。また、リン等の不純物元素を含有させた多結晶シリコンに代表される、電気伝導度が高い半導体、ニッケルシリサイドなどのシリサイドを用いてもよい。
次に、図8に示す、本発明の一態様に係るトランジスタ200を有する半導体装置の作製方法を、図10乃至図17を用いて説明する。
本実施の形態では、半導体装置の一形態を、図18乃至図23を用いて説明する。
本発明の一態様である容量素子を使用した、半導体装置(記憶装置)の一例を図18に示す。本発明の一態様の半導体装置は、トランジスタ200はトランジスタ300の上方に設けられ、容量素子100はトランジスタ200の上方に設けられている。容量素子100、またはトランジスタ300は、少なくとも一部がトランジスタ200と重畳することが好ましい。これにより、容量素子100、トランジスタ200、およびトランジスタ300の上面視における占有面積を低減することができるので、本実施の形態に係る半導体装置を微細化または高集積化させることができる。なお、本実施の形態に係る半導体装置は、例えば、CPU(Central Processing Unit)またはGPU(Graphics Processing Unit)に代表されるロジック回路、あるいはDRAM(Dynamic Random Access Memory)またはNVM(Non−Volatile Memory)に代表されるメモリ回路に適用することができる。
トランジスタ300は、基板311上に設けられ、ゲート電極として機能する導電体316、ゲート絶縁体として機能する絶縁体315、基板311の一部からなる半導体領域313、ならびにソース領域またはドレイン領域として機能する低抵抗領域314a、および低抵抗領域314bを有する。
容量素子100は、絶縁体160上の絶縁体114と、絶縁体114上の絶縁体140と、絶縁体114および絶縁体140に形成された開口の中に配置された導電体110と、導電体110および絶縁体140上の絶縁体130と、絶縁体130上の導電体120と、導電体120および絶縁体130上の絶縁体150と、を有する。ここで、絶縁体114および絶縁体140に形成された開口の中に導電体110、絶縁体130、および導電体120の少なくとも一部が配置される。
各構造体の間には、層間膜、配線、およびプラグ等が設けられた配線層が設けられていてもよい。また、配線層は、設計に応じて複数層設けることができる。ここで、プラグまたは配線として機能する導電体は、複数の構造をまとめて同一の符号を付与する場合がある。また、本明細書等において、配線と、配線と電気的に接続するプラグとが一体物であってもよい。すなわち、導電体の一部が配線として機能する場合、および導電体の一部がプラグとして機能する場合もある。
なお、トランジスタ200に、酸化物半導体を用いる場合、酸化物半導体の近傍に過剰酸素領域を有する絶縁体が設けられることがある。その場合、該過剰酸素領域を有する絶縁体と、該過剰酸素領域を有する絶縁体近傍に設ける導電体との間に、バリア性を有する絶縁体を設けることが好ましい。
本発明の一態様である半導体装置を使用した、半導体装置(記憶装置)の一例を図21に示す。図21に示す半導体装置は、図18で示した半導体装置と同様に、トランジスタ200、トランジスタ300、および容量素子100を有する。ただし、図21に示す半導体装置は、容量素子100がプレーナ型である点、およびトランジスタ200とトランジスタ300が電気的に接続されている点において、図18に示す半導体装置と異なる。
本実施の形態では、図24および図25を用いて、本発明の一態様に係る、酸化物を半導体に用いたトランジスタ(以下、OSトランジスタと呼ぶ場合がある。)、および容量素子が適用されている記憶装置(以下、OSメモリ装置と呼ぶ場合がある。)について説明する。OSメモリ装置は、少なくとも容量素子と、容量素子の充放電を制御するOSトランジスタを有する記憶装置である。OSトランジスタのオフ電流は極めて小さいので、OSメモリ装置は優れた保持特性をもち、不揮発性メモリとして機能させることができる。
図24(A)にOSメモリ装置の構成の一例を示す。記憶装置1400は、周辺回路1411、およびメモリセルアレイ1470を有する。周辺回路1411は、行回路1420、列回路1430、出力回路1440、およびコントロールロジック回路1460を有する。
図25(A)乃至(C)に、DRAMのメモリセルの回路構成例を示す。本明細書等において、1OSトランジスタ1容量素子型のメモリセルを用いたDRAMを、DOSRAM(Dynamic Oxide Semiconductor Random Access Memory)と呼ぶ場合がある。図25(A)に示す、メモリセル1471は、トランジスタM1と、容量素子CAと、を有する。なお、トランジスタM1は、ゲート(トップゲートと呼ぶ場合がある。)、及びバックゲートを有する。
図25(D)乃至(G)に、2トランジスタ1容量素子のゲインセル型のメモリセルの回路構成例を示す。図25(D)に示す、メモリセル1474は、トランジスタM2と、トランジスタM3と、容量素子CBと、を有する。なお、トランジスタM2は、トップゲート(単にゲートと呼ぶ場合がある。)、及びバックゲートを有する。本明細書等において、トランジスタM2にOSトランジスタを用いたゲインセル型のメモリセルを有する記憶装置を、NOSRAM(Nonvolatile Oxide Semiconductor RAM)と呼ぶ場合がある。
本実施の形態では、図26を用いて、本発明の半導体装置が実装されたチップ1200の一例を示す。チップ1200には、複数の回路(システム)が実装されている。このように、複数の回路(システム)を一つのチップに集積する技術を、システムオンチップ(System on Chip:SoC)と呼ぶ場合がある。
本実施の形態では、先の実施の形態に示す半導体装置を用いた記憶装置の応用例について説明する。先の実施の形態に示す半導体装置は、例えば、各種電子機器(例えば、情報端末、コンピュータ、スマートフォン、電子書籍端末、デジタルカメラ(ビデオカメラも含む)、録画再生装置、ナビゲーションシステムなど)の記憶装置に適用できる。なお、ここで、コンピュータとは、タブレット型のコンピュータ、ノート型のコンピュータ、デスクトップ型のコンピュータの他、サーバシステムのような大型のコンピュータを含むものである。または、先の実施の形態に示す半導体装置は、メモリカード(例えば、SDカード)、USBメモリ、SSD(ソリッド・ステート・ドライブ)等の各種のリムーバブル記憶装置に適用される。図27にリムーバブル記憶装置の幾つかの構成例を模式的に示す。例えば、先の実施の形態に示す半導体装置は、パッケージングされたメモリチップに加工され、様々なストレージ装置、リムーバブルメモリに用いられる。
本発明の一態様に係る半導体装置は、CPUやGPUなどのプロセッサ、またはチップに用いることができる。図28に、本発明の一態様に係るCPUやGPUなどのプロセッサ、またはチップを備えた電子機器の具体例を示す。
本発明の一態様に係るGPUまたはチップは、様々な電子機器に搭載することができる。電子機器の例としては、例えば、テレビジョン装置、デスクトップ型またはノート型の情報端末用などのモニタ、デジタルサイネージ(Digital Signage:電子看板)、パチンコ機などの大型ゲーム機、などの比較的大きな画面を備える電子機器の他、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、電子ブックリーダー、携帯電話機、携帯型ゲーム機、携帯情報端末、音響再生装置、などが挙げられる。また、本発明の一態様に係るGPUまたはチップを電子機器に設けることにより、電子機器に人工知能を搭載することができる。
図28(A)には、情報端末の一種である携帯電話(スマートフォン)が図示されている。情報端末5100は、筐体5101と、表示部5102と、を有しており、入力用インターフェースとして、タッチパネルが表示部5102に備えられ、ボタンが筐体5101に備えられている。
図28(C)は、ゲーム機の一例である携帯ゲーム機5300を示している。携帯ゲーム機5300は、筐体5301、筐体5302、筐体5303、表示部5304、接続部5305、操作キー5306等を有する。筐体5302、および筐体5303は、筐体5301から取り外すことが可能である。筐体5301に設けられている接続部5305を別の筐体(図示せず)に取り付けることで、表示部5304に出力される映像を、別の映像機器(図示せず)に出力することができる。このとき、筐体5302、および筐体5303は、それぞれ操作部として機能することができる。これにより、複数のプレイヤーが同時にゲームを行うことができる。筐体5301、筐体5302、および筐体5303の基板に設けられているチップなどに先の実施の形態に示すチップを組み込むことができる。
本発明の一態様のGPUまたはチップは、大型コンピュータに適用することができる。
本発明の一態様のGPUまたはチップは、移動体である自動車、および自動車の運転席周辺に適用することができる。
図28(H)は、電化製品の一例である電気冷凍冷蔵庫5800を示している。電気冷凍冷蔵庫5800は、筐体5801、冷蔵室用扉5802、冷凍室用扉5803等を有する。
Claims (12)
- 内部に基板が設けられたチャンバーに、第1のプリカーサを導入する工程と、
前記第1のプリカーサの導入後に、第1の酸化剤を導入する工程と、
前記第1の酸化剤の導入後に、第2のプリカーサを導入する工程と、
前記第2のプリカーサの導入後に、第2の酸化剤を導入する工程により、
前記基板上に金属酸化物を形成する半導体装置の作製方法。 - 内部に基板が設けられたチャンバーに、第1のプリカーサを導入する工程と、
前記第1のプリカーサの導入後に、第1の酸化剤を導入する工程と、
前記第1の酸化剤の導入後に、第2のプリカーサを導入する工程と、
前記第2のプリカーサの導入後に、第2の酸化剤を導入する工程と、
前記第2の酸化剤の導入後に、第3のプリカーサを導入する工程と、
前記第3のプリカーサの導入後に、第3の酸化剤を導入する工程により、
前記基板上に金属酸化物を形成する半導体装置の作製方法。 - 請求項1または請求項2において、
前記第1のプリカーサは、インジウムを含む半導体装置の作製方法。 - 請求項1または請求項3において、
前記第2のプリカーサは、亜鉛およびガリウムの少なくとも一方を含む半導体装置の作製方法。 - 請求項2または請求項3において、
前記第2のプリカーサは、亜鉛およびガリウムの一方を含む半導体装置の作製方法。 - 請求項5において、
前記第3のプリカーサは、亜鉛およびガリウムの他方を含む半導体装置の作製方法。 - 請求項1乃至請求項6のいずれか一項において、
前記金属酸化物は、インジウム、および亜鉛を含む半導体装置の作製方法。 - 請求項1乃至請求項6のいずれか一項において、
前記金属酸化物は、インジウムと、元素M(Mは、アルミニウム、ガリウム、イットリウム、または錫)と、亜鉛を含む半導体装置の作製方法。 - 請求項1乃至請求項8のいずれか一項において、
前記金属酸化物は、結晶構造を有している半導体装置の作製方法。 - 請求項1乃至請求項9のいずれか一項において、
前記第1の酸化剤は、オゾン、酸素、水から選ばれた少なくとも一つを含み、
前記第2の酸化剤は、オゾン、酸素、水から選ばれた少なくとも一つを含む半導体装置の作製方法。 - 請求項1乃至請求項10のいずれか一項において、
前記第2の酸化剤は、前記第1の酸化剤と同じ材料を含む半導体装置の作製方法。 - 請求項2において、
前記第3の酸化剤は、オゾン、酸素、水から選ばれた少なくとも一つを含む半導体装置の作製方法。
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