JPWO2019176783A1 - 半導体装置、および半導体装置の実装構造 - Google Patents
半導体装置、および半導体装置の実装構造 Download PDFInfo
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- JPWO2019176783A1 JPWO2019176783A1 JP2020506470A JP2020506470A JPWO2019176783A1 JP WO2019176783 A1 JPWO2019176783 A1 JP WO2019176783A1 JP 2020506470 A JP2020506470 A JP 2020506470A JP 2020506470 A JP2020506470 A JP 2020506470A JP WO2019176783 A1 JPWO2019176783 A1 JP WO2019176783A1
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Abstract
Description
図1〜図19は、第1実施形態に係る半導体装置を示している。図示された半導体装置A1は、複数のリード1,2、複数の第1半導体素子3、複数の第2半導体素子4、複数の第3半導体素子5、複数の電子部品49、複数のワイヤ91,92,93、支持部材6および封止樹脂7を備えている。半導体装置A1の用途は、特に限定されず、半導体装置A1は、たとえばインバータモータの駆動制御に用いられるIPM(Intelligent Power Module)として構成される。
図20および図21は、本開示の第1実施形態に係る実装構造B1を示している。実装構造B1は、半導体装置A1の実装構造の一形態であり、実装対象部材81に実装されている。実装構造B1は、半導体装置A1、実装対象部材81、介在部材82および固定部材83を備える。
図22は、半導体装置A1の第1変形例を示している。図示された半導体装置A11は、リード1Dの第1部101Dに複数の凸領域131Dおよび複数の凹領域132Dが設けられている。複数の凸領域131Dおよび複数の凹領域132Dは、上述した複数の凸領域131Aおよび複数の凹領域132Aと同様の構成である。
図23および図24は、半導体装置A1の第2変形例を示している。図示された半導体装置A12は、第1部101A,101B,101C,101Dのz方向視形状を規定する面のうち、第3面123A,123B,123C,123Dを除く部分に、複数の凸領域131A,131B,131C,131Dおよび複数の凹領域132A,132B,132C,132Dが設けられている。複数の凸領域131B,131Cおよび複数の凸領域132B,132Cは、上述した複数の凸領域131Aおよび複数の凹領域132Aと同様の構成である。
図25は、半導体装置A1の第3変形例を示している。図示された半導体装置A13は、第1部101A,101B,第1部101C,第1部101Dのz方向視形状を規定する面のすべてに、複数の凸領域131A,131B,131C,131Dおよび複数の凹領域132A,132B,132C,132Dが設けられている。
図26は、本開示の第2実施形態に係る半導体装置を示している。図示された半導体装置A2は、第1半導体素子3の構成が上述した実施形態と異なっている。
第1半導体素子と、
前記第1リードおよび前記第1半導体素子の各々の少なくとも一部を覆う封止樹脂と、を備え、
前記第1リードは、前記第1半導体素子が搭載された第1リード主面、前記第1リード主面とは反対側の第1リード裏面、および前記第1リード主面と前記第1リード裏面とが離間する厚さ方向において前記第1リード主面と前記第1リード裏面との間に位置する第1リード第1面を有する第1リード第1部を含み、
前記第1半導体素子は、前記第1リード主面に搭載されており、
前記第1リード第1面は、前記封止樹脂によって覆われており、且つ前記厚さ方向視において複数の凸領域と複数の凹領域とが交互に配置されて構成されている、半導体装置。
付記2.前記第1リードの前記第1リード裏面が固定された支持部材をさらに備える、付記1に記載の半導体装置。
付記3.前記封止樹脂は、前記第1リード主面と同じ側を向く樹脂主面、前記第1リード裏面と同じ側を向く樹脂裏面および前記厚さ方向において前記樹脂主面と前記樹脂裏面との間に位置し且つ前記厚さ方向と直角である第1方向に前記第1リード第1面から離間する樹脂第1面を有する、付記2に記載の半導体装置。
付記4.前記第1リード第1面は、前記第1リードのうち前記樹脂第1面に最も近い部位である、付記3に記載の半導体装置。
付記5.前記複数のリードは、前記第1リード第1面、前記樹脂第1面、および前記第1リード第1面の両端から第1方向に沿って前記樹脂第1面に延びる一対の第1仮想線に、前記厚さ方向視において囲まれた第1領域を避けた領域に配置されている、付記4に記載の半導体装置。
付記6.前記封止樹脂は、前記厚さ方向視において前記樹脂第1面から前記第1リード第1面側に凹む樹脂第1凹部を有する、付記5に記載の半導体装置。
付記7.前記樹脂第1凹部は、前記厚さ方向視において前記第1リード第1面、前記樹脂第1面および前記一対の第1仮想線とともに前記第1領域を囲む、付記6に記載の半導体装置。
付記8.前記支持部材は、前記第1リード主面と同じ側を向き且つ前記第1リード裏面が固定された支持部材主面、前記支持部材主面とは反対側を向く支持部材裏面、および前記厚さ方向において前記支持部材主面と前記支持部材裏面との間に位置する支持部材第1面を有しており、
前記支持部材第1面は、前記厚さ方向において前記第1リード第1面と前記樹脂第1面との間に位置している、付記3ないし7のいずれかに記載の半導体装置。
付記9.前記第1リード第1面は、厚さ方向において互いに隣接する第1面第1領域と第1面第2領域とを有しており、
前記第1面第1領域は、前記第1面第2領域よりも粗い、付記3ないし8のいずれかに記載の半導体装置。
付記10.前記第1面第1領域は、前記第1面第2領域よりも前記第1リード主面側に位置している、付記9に記載の半導体装置。
付記11.前記第1リードは、前記第1リード主面と前記第1面第1領域との間に位置し且つ前記第1リード主面から前記厚さ方向に突出する第1凸部を有する、付記10に記載の半導体装置。
付記12.前記第1リード裏面は、厚さ方向視において前記第1半導体素子と重なる部位を含む裏面第1部と、厚さ方向視において隣り合う前記凹領域の底部どうしを結ぶ線分と前記第1リード第1面とに囲まれた裏面第2部とを含み、
前記裏面第2部は、前記第1方向において前記裏面第1部から離間するほど、前記厚さ方向において前記第1リード主面に近づくように傾斜している、付記10または11に記載の半導体装置。
付記13.前記厚さ方向視において、前記凸領域の曲率半径は、前記凹領域の曲率半径よりも小さい、付記2ないし12のいずれかに記載の半導体装置。
付記14.前記複数の凸領域および前記複数の凹領域は、前記第1リード第1面の厚さ方向全域に設けられている、付記2ないし13のいずれかに記載の半導体装置。
付記15.前記第1半導体素子を制御するための第2半導体素子と、前記第2半導体素子が搭載された第2リードとをさらに備え、
前記第1リードに印加される電圧は、前記第2リードに印加される電圧よりも高い、付記2ないし14のいずれかに記載の半導体装置。
付記16.前記第2リードは、前記第2半導体素子が搭載された第2リード第1部を有し、
前記第2リード第1部は、前記第1リード第1部に対して前記厚さ方向において前記第1リード主面が向く側に位置している、付記15に記載の半導体装置。
付記17.前記第1リードおよび前記第2リードは、前記厚さ方向および前記第1方向のいずれとも直角である第2方向に互いに離間して配置されており、
前記第1リードは、前記封止樹脂から前記第2方向において前記第2リードとは反対側に突出する第1リード第2部を有し、
前記第2リードは、前記封止樹脂から前記第2方向において前記第1リードとは反対側に突出する第2リード第2部を有する、付記15または16に記載の半導体装置。
付記18.付記1ないし17のいずれかに記載の半導体装置と、
前記半導体装置を実装する実装対象部材と、
前記半導体装置の前記支持部材と前記実装対象部材との間に介在する介在部材と、
前記介在部材を挟んで前記半導体装置と前記実装対象部材とを固定する固定部材と、
を備える、半導体装置の実装構造。
Claims (18)
- 第1リードと、
第1半導体素子と、
前記第1リードおよび前記第1半導体素子の各々の少なくとも一部を覆う封止樹脂と、を備え、
前記第1リードは、前記第1半導体素子が搭載された第1リード主面、前記第1リード主面とは反対側を向く第1リード裏面、および前記第1リード主面と前記第1リード裏面とが離間する厚さ方向において前記第1リード主面と前記第1リード裏面との間に位置する第1リード第1面を有する第1リード第1部を含み、
前記第1リード第1面は、前記封止樹脂によって覆われており、且つ前記厚さ方向視において複数の凸領域と複数の凹領域とが交互に配置されて構成されている、半導体装置。 - 前記第1リードの前記第1リード裏面が固定された支持部材をさらに備える、請求項1に記載の半導体装置。
- 前記封止樹脂は、前記第1リード主面と同じ側を向く樹脂主面、前記第1リード裏面と同じ側を向く樹脂裏面、および前記厚さ方向において前記樹脂主面と前記樹脂裏面との間に位置し且つ前記厚さ方向と直角である第1方向に前記第1リード第1面から離間する樹脂第1面を有する、請求項2に記載の半導体装置。
- 前記第1リード第1面は、前記第1リードのうち前記樹脂第1面に最も近い部位である、請求項3に記載の半導体装置。
- 前記複数のリードは、前記第1リード第1面、前記樹脂第1面、および前記第1リード第1面の両端から第1方向に沿って前記樹脂第1面に延びる一対の第1仮想線に、前記厚さ方向視において囲まれた第1領域を避けた領域に配置されている、請求項4に記載の半導体装置。
- 前記封止樹脂は、前記厚さ方向視において前記樹脂第1面から前記第1リード第1面側に凹む樹脂第1凹部を有する、請求項5に記載の半導体装置。
- 前記樹脂第1凹部は、前記厚さ方向視において前記第1リード第1面、前記樹脂第1面および前記一対の第1仮想線とともに前記第1領域を囲む、請求項6に記載の半導体装置。
- 前記支持部材は、前記第1リード主面と同じ側を向き且つ前記第1リード裏面が固定された支持部材主面、前記支持部材主面とは反対側を向く支持部材裏面、および前記厚さ方向において前記支持部材主面と前記支持部材裏面との間に位置する支持部材第1面を有しており、
前記支持部材第1面は、前記厚さ方向において前記第1リード第1面と前記樹脂第1面との間に位置している、請求項3ないし7のいずれかに記載の半導体装置。 - 前記第1リード第1面は、厚さ方向において互いに隣接する第1面第1領域と第1面第2領域とを有しており、
前記第1面第1領域は、前記第1面第2領域よりも表面粗さが粗い、請求項3ないし8のいずれかに記載の半導体装置。 - 前記第1面第1領域は、前記第1面第2領域よりも前記第1リード主面側に位置している、請求項9に記載の半導体装置。
- 前記第1リードは、前記第1リード主面と前記第1面第1領域との間に位置し且つ前記第1リード主面から前記厚さ方向に突出する第1凸部を有する、請求項10に記載の半導体装置。
- 前記第1リード裏面は、厚さ方向視において前記第1半導体素子と重なる部位を含む裏面第1部と、厚さ方向視において隣り合う前記凹領域の底部どうしを結ぶ線分と前記第1リード第1面とに囲まれた裏面第2部とを含み、
前記裏面第2部は、前記第1方向において前記裏面第1部から離間するほど、前記厚さ方向において前記第1リード主面に近づくように傾斜している、請求項10または11に記載の半導体装置。 - 前記厚さ方向視において、前記凸領域の曲率半径は、前記凹領域の曲率半径よりも小さい、請求項2ないし12のいずれかに記載の半導体装置。
- 前記複数の凸領域および前記複数の凹領域は、前記第1リード第1面の厚さ方向全域に設けられている、請求項2ないし13のいずれかに記載の半導体装置。
- 前記第1半導体素子を制御するための第2半導体素子と、前記第2半導体素子が搭載された第2リードとをさらに備え、
前記第1リードに印加される電圧は、前記第2リードに印加される電圧よりも高い、請求項2ないし14のいずれかに記載の半導体装置。 - 前記第2リードは、前記第2半導体素子が搭載された第2リード第1部を有し、
前記第2リード第1部は、前記第1リード第1部に対して前記厚さ方向において前記第1リード主面が向く側に位置している、請求項15に記載の半導体装置。 - 前記第1リードおよび前記第2リードは、前記厚さ方向および前記第1方向のいずれとも直角である第2方向に互いに離間して配置されており、
前記第1リードは、前記封止樹脂から前記第2方向において前記第2リードとは反対側に突出する第1リード第2部を有し、
前記第2リードは、前記封止樹脂から前記第2方向において前記第1リードとは反対側に突出する第2リード第2部を有する、請求項15または16に記載の半導体装置。 - 請求項1ないし17のいずれかに記載の半導体装置と、
前記半導体装置を実装する実装対象部材と、
前記半導体装置の前記支持部材と前記実装対象部材との間に介在する介在部材と、
前記介在部材を挟んで前記半導体装置と前記実装対象部材とを固定する固定部材と、
を備える、半導体装置の実装構造。
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- 2019-03-08 US US16/971,584 patent/US11322459B2/en active Active
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JP2003332512A (ja) * | 2002-05-14 | 2003-11-21 | Hitachi Ltd | 電子回路装置 |
JP2010171104A (ja) * | 2009-01-21 | 2010-08-05 | Denso Corp | 半導体装置の実装構造 |
JP2013145825A (ja) * | 2012-01-16 | 2013-07-25 | Dainippon Printing Co Ltd | 半導体装置用リードフレーム |
JP2014207430A (ja) * | 2013-03-21 | 2014-10-30 | ローム株式会社 | 半導体装置 |
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JP7257380B2 (ja) | 2023-04-13 |
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US11322459B2 (en) | 2022-05-03 |
US20200388580A1 (en) | 2020-12-10 |
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DE112019001311T5 (de) | 2020-12-10 |
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