JPWO2018186026A1 - 半導体装置、半導体装置の製造方法、及び電子機器 - Google Patents
半導体装置、半導体装置の製造方法、及び電子機器 Download PDFInfo
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Abstract
Description
1.半導体装置の全体構成
2.既存の技術に対する検討
3.電極接合構造の形成方法
4.適用例
5.補足
図1を参照して、本開示の一実施形態に係る半導体装置の構成について説明する。図1は、本実施形態に係る半導体装置の概略構成を示す縦断面図である。
図1に示す半導体装置1では、第1基板110Aと第2基板110Bとが電極接合構造159aによって電気的に接続されており、第2基板110Bと第3基板110Cとが、電極接合構造159bによって電気的に接続されている。ここで、電極接合構造は、既存の積層型の半導体装置においても、基板間の導通を取るために一般的に用いられる構造である。しかしながら、既存の技術によって電極接合構造を構成するビア及び電極を形成しようとすると、その電極の形状に異常が生じ、当該電極接合構造が正常に形成されない恐れがある。ここでは、本実施形態に係る電極接合構造159の形成方法について詳細に説明するに先立ち、本開示をより明確なものとするために、既存の電極接合構造の形成方法について説明する。
図4A〜図4Iを参照して、本実施形態に係る電極接合構造159bの形成方法について説明する。図4A〜図4Iは、本実施形態に係る電極接合構造159bを構成するビア173及び電極163の形成方法について説明するための図である。図4A〜図4Iは、図1に示す半導体装置1の第2基板110Bにおけるビア173及び電極163のz軸方向と平行な断面図(図中上段)及び上面図(図中下段)を、当該ビア173及び当該電極163の形成方法における工程順に概略的に図示したものであり、当該形成方法におけるプロセスフローを表すものである。
(積層型の固体撮像装置への構成例)
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、以下で説明するような積層型の固体撮像装置に適用されてもよい。
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、図9〜図11で示すような電子機器に適用されてよい。
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、内視鏡手術システムに適用されてもよい。
本開示に係る技術(本技術)は、様々な製品へ応用することができる。例えば、本開示に係る技術は、自動車、電気自動車、ハイブリッド電気自動車、自動二輪車、自転車、パーソナルモビリティ、飛行機、ドローン、船舶、ロボット等のいずれかの種類の移動体に搭載される装置として実現されてもよい。
以上、添付図面を参照しながら本開示の好適な実施形態について詳細に説明したが、本開示の技術的範囲はかかる例に限定されない。本開示の技術分野における通常の知識を有する者であれば、特許請求の範囲に記載された技術的思想の範疇内において、各種の変更例または修正例に想到し得ることは明らかであり、これらについても、当然に本開示の技術的範囲に属するものと了解される。
(1)
所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層される多層配線層と、をそれぞれ有する複数の基板が積層されて構成され、
前記複数の基板のうちの少なくとも2つの基板間の貼り合わせ面には、当該2つの基板間を電気的に接続するための構造であって、前記貼り合わせ面にそれぞれ形成される電極同士が直接接触した状態で接合している電極接合構造が存在し、
前記2つの基板のうちの少なくともいずれかにおいて、前記電極接合構造を構成する電極、及び前記電極を前記多層配線層内の配線に接続するためのビアの少なくともいずれかについて、前記電極及び前記ビアを構成する導電材料の内部に当該導電材料の拡散を防止するための保護膜が埋め込まれた構造が存在する、
半導体装置。
(2)
前記電極及び前記ビアを構成する導電材料はCuであり、
前記保護膜は、当該Cuの拡散を防止するバリアメタル膜である、
前記(1)に記載の半導体装置。
(3)
前記バリアメタル膜は、TiN、TaN、又はWNを含む膜である、
前記(2)に記載の半導体装置。
(4)
前記導電材料の内部に埋め込まれている前記保護膜は、前記基板が積層される方向に沿って延伸する形状を有する、
前記(1)〜(3)のいずれか1項に記載の半導体装置。
(5)
前記導電材料の内部に埋め込まれている前記保護膜は、前記電極及び前記ビアの内部において、前記基板が積層される方向の全域に渡って存在する、
前記(4)に記載の半導体装置。
(6)
前記導電材料の内部に埋め込まれている前記保護膜は、前記基板が積層される方向から見た場合に、前記基板が積層される方向と直交する平面内の一方向に延伸する略直線形状を有する、
前記(1)〜(5)のいずれか1項に記載の半導体装置。
(7)
前記導電材料の内部に埋め込まれている前記保護膜は、前記基板が積層される方向から見た場合に、略ドット状の形状を有する、
前記(1)〜(5)のいずれか1項に記載の半導体装置。
(8)
前記導電材料の内部に埋め込まれている前記保護膜は、前記基板が積層される方向から見た場合に、前記基板が積層される方向と直交する平面内の第1の方向に延伸する略直線形状と、前記平面内の前記第1の方向と直交する第2の方向に延伸する略直線形状と、が交差した略十字型の形状を有する、
前記(1)〜(5)のいずれか1項に記載の半導体装置。
(9)
前記複数の基板のうちの1つである第1基板は、前記半導体基板上に画素が2次元状に配列された画素部が存在する画素基板であり、
前記半導体装置は固体撮像装置である、
前記(1)〜(8)のいずれか1項に記載の半導体装置。
(10)
前記複数の基板のうち、前記第1基板の直下に存在する第2基板には、前記画素の各々において取得される画素信号をAD変換する画素信号処理回路が存在し、
前記第1基板と前記第2基板との貼り合わせ面には、前記画素の各々について、前記画素信号を前記画素信号処理回路に伝送するための前記電極接合構造が存在する、
前記(9)に記載の半導体装置。
(11)
前記ビアは、前記半導体基板を貫通する貫通孔内に前記導電材料が埋め込まれた構造を有する、
前記(1)〜(10)のいずれか1項に記載の半導体装置。
(12)
所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層される多層配線層と、を有する複数の基板をそれぞれ作製する工程と、
前記複数の基板を積層する工程と、
を含み、
前記複数の基板のうちの少なくとも2つの基板間の貼り合わせ面には、当該2つの基板間を電気的に接続するための構造であって、前記貼り合わせ面にそれぞれ形成される電極同士が直接接触した状態で接合している電極接合構造が存在し、
前記2つの基板のうちの少なくともいずれかにおいて、前記電極接合構造を構成する電極、及び前記電極を前記多層配線層内の配線に接続するためのビアを形成する工程は、
前記基板の一面から前記配線にまで至る貫通孔を、当該貫通孔の内部の一部領域に柱状の柱状部を残存させた状態で形成する工程と、
少なくとも前記貫通孔の側壁、及び前記柱状部の側壁に、前記電極及び前記ビアを構成する導電材料の拡散を防止するための保護膜を形成する工程と、
前記貫通孔内に、前記導電材料を埋め込む工程と、
前記柱状部を除去することにより、前記柱状部が存在した領域に、前記保護膜によって側面が囲まれた空間を形成する工程と、
を含む、
半導体装置の製造方法。
(13)
前記電極接合構造は、前記貼り合わせ面にそれぞれ形成される前記電極同士が直接接触した状態で前記2つの基板を貼り合わせた後、熱処理を行い、接触している前記電極同士を接合することにより、形成される、
前記(12)に記載の半導体装置の製造方法。
(14)
前記空間は、前記電極及び前記ビアの内部において、前記基板が積層される方向に沿って延伸する長尺な形状を有する、
前記(12)又は(13)に記載の半導体装置の製造方法。
(15)
前記電極及び前記ビアの内部において、前記基板が積層される方向の全域に渡って、前記空間が存在する、
前記(14)に記載の半導体装置の製造方法。
(16)
前記空間は、前記基板が積層される方向から見た場合に、前記基板が積層される方向と直交する平面内の一方向に延伸する略長方形形状を有する、
前記(12)〜(15)のいずれか1項に記載の半導体装置の製造方法。
(17)
前記空間は、前記基板が積層される方向から見た場合に、略正方形形状を有する、
前記(12)〜(15)のいずれか1項に記載の半導体装置の製造方法。
(18)
前記空間は、前記基板が積層される方向から見た場合に、前記基板が積層される方向と直交する平面内の第1の方向に延伸する略長方形形状と、前記平面内の前記第1の方向と直交する第2の方向に延伸する略長方形形状と、が交差した略十字型の形状を有する、
前記(12)〜(15)のいずれか1項に記載の半導体装置の製造方法。
(19)
観察対象を電子的に撮影する固体撮像装置、を備え、
前記固体撮像装置は、
所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層される多層配線層と、をそれぞれ有する複数の基板が積層されて構成され、
前記複数の基板のうちの少なくとも2つの基板間の貼り合わせ面には、当該2つの基板間を電気的に接続するための構造であって、前記貼り合わせ面にそれぞれ形成される電極同士が直接接触した状態で接合している電極接合構造が存在し、
前記2つの基板のうちの少なくともいずれかにおいて、前記電極接合構造を構成する電極、及び前記電極を前記多層配線層内の配線に接続するためのビアの少なくともいずれかについて、前記電極及び前記ビアを構成する導電材料の内部に当該導電材料の拡散を防止するための保護膜が埋め込まれた構造が存在する、
電子機器。
101、121、131 Si基板
103、109、123、129、133、202、214 絶縁膜
105、125、135 多層配線層
110A 第1基板
110B 第2基板
110C 第3基板
111 CF層
113 MLアレイ
151 パッド
153a、153b パッド開口部
159、159a、159b 電極接合構造
161、162、163、164、206、208 電極
171、172、173、174、205、207 ビア
181、182 配線
203、211、215 バリアメタル膜
201、212 貫通孔
213 柱状部
204、216 Cu
218、218a、218b 空間
301 スマートフォン(電子機器)
311 デジタルカメラ(電子機器)
Claims (19)
- 所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層される多層配線層と、をそれぞれ有する複数の基板が積層されて構成され、
前記複数の基板のうちの少なくとも2つの基板間の貼り合わせ面には、当該2つの基板間を電気的に接続するための構造であって、前記貼り合わせ面にそれぞれ形成される電極同士が直接接触した状態で接合している電極接合構造が存在し、
前記2つの基板のうちの少なくともいずれかにおいて、前記電極接合構造を構成する電極、及び前記電極を前記多層配線層内の配線に接続するためのビアの少なくともいずれかについて、前記電極及び前記ビアを構成する導電材料の内部に当該導電材料の拡散を防止するための保護膜が埋め込まれた構造が存在する、
半導体装置。 - 前記電極及び前記ビアを構成する導電材料はCuであり、
前記保護膜は、当該Cuの拡散を防止するバリアメタル膜である、
請求項1に記載の半導体装置。 - 前記バリアメタル膜は、TiN、TaN、又はWNを含む膜である、
請求項2に記載の半導体装置。 - 前記導電材料の内部に埋め込まれている前記保護膜は、前記基板が積層される方向に沿って延伸する形状を有する、
請求項1に記載の半導体装置。 - 前記導電材料の内部に埋め込まれている前記保護膜は、前記電極及び前記ビアの内部において、前記基板が積層される方向の全域に渡って存在する、
請求項4に記載の半導体装置。 - 前記導電材料の内部に埋め込まれている前記保護膜は、前記基板が積層される方向から見た場合に、前記基板が積層される方向と直交する平面内の一方向に延伸する略直線形状を有する、
請求項4に記載の半導体装置。 - 前記導電材料の内部に埋め込まれている前記保護膜は、前記基板が積層される方向から見た場合に、略ドット状の形状を有する、
請求項4に記載の半導体装置。 - 前記導電材料の内部に埋め込まれている前記保護膜は、前記基板が積層される方向から見た場合に、前記基板が積層される方向と直交する平面内の第1の方向に延伸する略直線形状と、前記平面内の前記第1の方向と直交する第2の方向に延伸する略直線形状と、が交差した略十字型の形状を有する、
請求項4に記載の半導体装置。 - 前記複数の基板のうちの1つである第1基板は、前記半導体基板上に画素が2次元状に配列された画素部が存在する画素基板であり、
前記半導体装置は固体撮像装置である、
請求項1に記載の半導体装置。 - 前記複数の基板のうち、前記第1基板の直下に存在する第2基板には、前記画素の各々において取得される画素信号をAD変換する画素信号処理回路が存在し、
前記第1基板と前記第2基板との貼り合わせ面には、前記画素の各々について、前記画素信号を前記画素信号処理回路に伝送するための前記電極接合構造が存在する、
請求項9に記載の半導体装置。 - 前記ビアは、前記半導体基板を貫通する貫通孔内に前記導電材料が埋め込まれた構造を有する、
請求項1に記載の半導体装置。 - 所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層される多層配線層と、を有する複数の基板をそれぞれ作製する工程と、
前記複数の基板を積層する工程と、
を含み、
前記複数の基板のうちの少なくとも2つの基板間の貼り合わせ面には、当該2つの基板間を電気的に接続するための構造であって、前記貼り合わせ面にそれぞれ形成される電極同士が直接接触した状態で接合している電極接合構造が存在し、
前記2つの基板のうちの少なくともいずれかにおいて、前記電極接合構造を構成する電極、及び前記電極を前記多層配線層内の配線に接続するためのビアを形成する工程は、
前記基板の一面から前記配線にまで至る貫通孔を、当該貫通孔の内部の一部領域に柱状の柱状部を残存させた状態で形成する工程と、
少なくとも前記貫通孔の側壁、及び前記柱状部の側壁に、前記電極及び前記ビアを構成する導電材料の拡散を防止するための保護膜を形成する工程と、
前記貫通孔内に、前記導電材料を埋め込む工程と、
前記柱状部を除去することにより、前記柱状部が存在した領域に、前記保護膜によって側面が囲まれた空間を形成する工程と、
を含む、
半導体装置の製造方法。 - 前記電極接合構造は、前記貼り合わせ面にそれぞれ形成される前記電極同士が直接接触した状態で前記2つの基板を貼り合わせた後、熱処理を行い、接触している前記電極同士を接合することにより、形成される、
請求項12に記載の半導体装置の製造方法。 - 前記空間は、前記電極及び前記ビアの内部において、前記基板が積層される方向に沿って延伸する長尺な形状を有する、
請求項12に記載の半導体装置の製造方法。 - 前記電極及び前記ビアの内部において、前記基板が積層される方向の全域に渡って、前記空間が存在する、
請求項14に記載の半導体装置の製造方法。 - 前記空間は、前記基板が積層される方向から見た場合に、前記基板が積層される方向と直交する平面内の一方向に延伸する略長方形形状を有する、
請求項14に記載の半導体装置の製造方法。 - 前記空間は、前記基板が積層される方向から見た場合に、略正方形形状を有する、
請求項14に記載の半導体装置の製造方法。 - 前記空間は、前記基板が積層される方向から見た場合に、前記基板が積層される方向と直交する平面内の第1の方向に延伸する略長方形形状と、前記平面内の前記第1の方向と直交する第2の方向に延伸する略長方形形状と、が交差した略十字型の形状を有する、
請求項14に記載の半導体装置の製造方法。 - 観察対象を電子的に撮影する固体撮像装置、を備え、
前記固体撮像装置は、
所定の機能を有する回路が形成された半導体基板と、前記半導体基板上に積層される多層配線層と、をそれぞれ有する複数の基板が積層されて構成され、
前記複数の基板のうちの少なくとも2つの基板間の貼り合わせ面には、当該2つの基板間を電気的に接続するための構造であって、前記貼り合わせ面にそれぞれ形成される電極同士が直接接触した状態で接合している電極接合構造が存在し、
前記2つの基板のうちの少なくともいずれかにおいて、前記電極接合構造を構成する電極、及び前記電極を前記多層配線層内の配線に接続するためのビアの少なくともいずれかについて、前記電極及び前記ビアを構成する導電材料の内部に当該導電材料の拡散を防止するための保護膜が埋め込まれた構造が存在する、
電子機器。
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WO2018186026A1 (ja) | 2018-10-11 |
US20200035736A1 (en) | 2020-01-30 |
US11127773B2 (en) | 2021-09-21 |
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