JPWO2017217369A1 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JPWO2017217369A1
JPWO2017217369A1 JP2018523895A JP2018523895A JPWO2017217369A1 JP WO2017217369 A1 JPWO2017217369 A1 JP WO2017217369A1 JP 2018523895 A JP2018523895 A JP 2018523895A JP 2018523895 A JP2018523895 A JP 2018523895A JP WO2017217369 A1 JPWO2017217369 A1 JP WO2017217369A1
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Japan
Prior art keywords
wire
solder layer
semiconductor device
power semiconductor
semiconductor element
Prior art date
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Granted
Application number
JP2018523895A
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Japanese (ja)
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JP6487122B2 (en
Inventor
辰則 柳本
辰則 柳本
晋助 浅田
晋助 浅田
耕一 東久保
耕一 東久保
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Publication of JPWO2017217369A1 publication Critical patent/JPWO2017217369A1/en
Priority to JP2019028427A priority Critical patent/JP6983187B2/en
Application granted granted Critical
Publication of JP6487122B2 publication Critical patent/JP6487122B2/en
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    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00012—Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19107—Disposition of discrete passive components off-chip wires

Abstract

電力用半導体装置は、少なくとも表面に導体層を有する絶縁基板と、導体層の上に設けられたワイヤバンプと、ワイヤバンプの上に載置された半導体素子と、導体層の上に半導体素子を接合する半田層とを含み、および／またはベース板と、ベース板の上に設けられた複数のワイヤバンプと、ワイヤバンプの上に載置された、少なくとも裏面に導体層を有する絶縁基板と、ベース板の上に絶縁基板の導体層を接合する半田層とを含み、ワイヤバンプと半田層との界面に、ワイヤバンプの材料と半田層の材料からなる合金を有する。  A semiconductor device for electric power joins a semiconductor element on an insulating substrate having a conductor layer on at least a surface, a wire bump provided on the conductor layer, a semiconductor element placed on the wire bump, and the conductor layer. A solder layer, and / or a base plate, a plurality of wire bumps provided on the base plate, an insulating substrate placed on the wire bump and having a conductor layer on at least the back surface, and the base plate And a solder layer that joins the conductor layer of the insulating substrate, and has an alloy made of the material of the wire bump and the material of the solder layer at the interface between the wire bump and the solder layer.

Description

本発明は、電力用半導体装置に関し、特に、半田層の材料と合金形成が可能な材料からなるワイヤバンプを所定の位置に配置した電力用半導体装置に関する。   The present invention relates to a power semiconductor device, and more particularly to a power semiconductor device in which wire bumps made of a material capable of forming an alloy with a solder layer material are arranged at predetermined positions.

従来の電力用半導体装置では、例えばベース板と絶縁基板とを半田接合する際に、ＡｌやＣｕを主材とするワイヤを銅板の上にウェッジボンディングしてワイヤバンプを形成し、半田層の厚さを均一にしていた（例えば特許文献１、２）。   In a conventional power semiconductor device, for example, when soldering a base plate and an insulating substrate, a wire bump is formed by wedge-bonding a wire mainly composed of Al or Cu on a copper plate, and the thickness of the solder layer (For example, Patent Documents 1 and 2).

特開平１１−１８６３３１号公報JP-A-11-186331 特許第５５４２５６７号公報Japanese Patent No. 5542567

近年、電力用半導体装置では、小型化、高出力化の要求から、電力用半導体装置内部の電流密度が高くなり、高温での動作が必要となる。このため、半導体素子で発生した熱を、より効率よくベース板に伝えて放熱することが必要となる。また、半導体素子と絶縁基板や、絶縁基板とベース板を接合する半田層に亀裂が入った場合にも、亀裂の進展を抑制するこことが必要であった。   In recent years, in power semiconductor devices, due to demands for miniaturization and higher output, the current density inside the power semiconductor devices has increased, and operation at high temperatures is required. For this reason, it is necessary to transfer the heat generated in the semiconductor element to the base plate more efficiently and dissipate the heat. In addition, it is necessary to suppress the progress of cracks even when cracks occur in the solder layer that joins the semiconductor element and the insulating substrate or between the insulating substrate and the base plate.

そこで、本発明は、高温動作においても高信頼性かつ高熱伝導性を有する電力用半導体装置の提供を目的とする。
Therefore, an object of the present invention is to provide a power semiconductor device having high reliability and high thermal conductivity even in high temperature operation.

本発明は、少なくとも表面に導体層を有する絶縁基板と、導体層の上に設けられたワイヤバンプと、ワイヤバンプの上に載置された半導体素子と、導体層の上に導体層と半導体素子とを接合する半田層とを含み、ワイヤバンプと半田層との界面に、ワイヤバンプの材料と半田層の材料からなる合金を有することを特徴とする電力用半導体装置である。   The present invention includes an insulating substrate having a conductor layer on at least a surface, a wire bump provided on the conductor layer, a semiconductor element placed on the wire bump, and a conductor layer and a semiconductor element on the conductor layer. A power semiconductor device comprising a solder layer to be bonded and having an alloy made of a wire bump material and a solder layer material at an interface between the wire bump and the solder layer.

本発明は、また、ベース板と、ベース板の上に設けられた複数のワイヤバンプと、ワイヤバンプの上に載置された、少なくとも裏面に導体層を有する絶縁基板と、ベース板の上に絶縁基板の導体層を接合する半田層とを含み、ワイヤバンプと半田層との界面に、ワイヤバンプの材料と半田層の材料からなる合金が形成されたことを特徴とする電力用半導体装置でもある。   The present invention also provides a base plate, a plurality of wire bumps provided on the base plate, an insulating substrate placed on the wire bump and having a conductor layer on at least the back surface, and an insulating substrate on the base plate And a solder layer to which the conductor layer is bonded, and an alloy composed of the material of the wire bump and the material of the solder layer is formed at the interface between the wire bump and the solder layer.

以上のように、本発明にかかる電力用半導体装置では、ワイヤバンプにより半田層の膜厚を均一にできると共に、半田層中でのボイド（空隙）の発生を防止し、更に半田層の亀裂の進展を停止または遅延させることができ、高信頼性かつ高熱伝導性を有する電力用半導体装置の提供が可能となる。   As described above, in the power semiconductor device according to the present invention, the thickness of the solder layer can be made uniform by the wire bumps, the generation of voids (voids) in the solder layer can be prevented, and the crack of the solder layer can be further developed. Therefore, it is possible to provide a power semiconductor device having high reliability and high thermal conductivity.

本発明の実施の形態１にかかる電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power concerning Embodiment 1 of this invention. 図１の電力用半導体装置のＡ部分の拡大断面図である。It is an expanded sectional view of A part of the power semiconductor device of FIG. 図２の電力用半導体装置の一部の拡大断面図である。FIG. 3 is an enlarged cross-sectional view of a part of the power semiconductor device of FIG. 2. 図２の電力用半導体装置の一部の拡大断面図である。FIG. 3 is an enlarged cross-sectional view of a part of the power semiconductor device of FIG. 2. 本発明の実施の形態１にかかる電力用半導体装置のワイヤバンプの配置を示す平面図である。It is a top view which shows arrangement | positioning of the wire bump of the semiconductor device for electric power concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる電力用半導体装置のワイヤバンプの他の配置を示す平面図である。It is a top view which shows other arrangement | positioning of the wire bump of the semiconductor device for electric power concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる電力用半導体装置のワイヤバンプの他の配置を示す平面図である。It is a top view which shows other arrangement | positioning of the wire bump of the semiconductor device for electric power concerning Embodiment 1 of this invention. 本発明の実施の形態２にかかる電力用半導体装置の部分断面図である。It is a fragmentary sectional view of the power semiconductor device concerning Embodiment 2 of this invention. 本発明の実施の形態２にかかる電力用半導体装置のワイヤバンプの配置を示す平面図である。It is a top view which shows arrangement | positioning of the wire bump of the semiconductor device for electric power concerning Embodiment 2 of this invention. 図６ＡをＡ−Ａ方向に見た場合の断面図である。It is sectional drawing at the time of seeing FIG. 6A in an AA direction.

実施の形態１．
図１は、全体が１００で表される、本発明の実施の形態１にかかる電力用半導体装置の断面図である。また、図２は、図１の破線で囲んだ部分Ａの拡大断面図である。Embodiment 1 FIG.
FIG. 1 is a cross-sectional view of a power semiconductor device according to a first embodiment of the present invention, the whole being represented by 100. 2 is an enlarged sectional view of a portion A surrounded by a broken line in FIG.

電力用半導体装置１００は、ベース板１を含む。ベース板１は、例えばＣｕからなる。
ベース板１の上面には、半田層７により、絶縁基板３が固定されている。半田層７は、例えばＳｎからなる。The power semiconductor device 100 includes a base plate 1. The base plate 1 is made of Cu, for example.
An insulating substrate 3 is fixed to the upper surface of the base plate 1 by a solder layer 7. The solder layer 7 is made of, for example, Sn.

図２に示すように、絶縁基板３は、絶縁部材３ｂと、その表面と裏面にそれぞれ設けられた導体層３ａ、３ｃを含む。絶縁部材３ｂは、例えば窒化アルミニウムからなり、導体層３ａ、３ｃは、例えば銅のような金属からなる。   As shown in FIG. 2, the insulating substrate 3 includes an insulating member 3b and conductor layers 3a and 3c provided on the front and back surfaces thereof. The insulating member 3b is made of, for example, aluminum nitride, and the conductor layers 3a and 3c are made of, for example, a metal such as copper.

絶縁基板３の導体層３ａの上には、半田層７により半導体素子４が固定されている。半導体素子４は、ＭＯＳＦＥＴやＩＧＢＴ等の電力用の半導体素子（パワーデバイス）である。なお、図１に示すように、他の導体層３ａの上には、例えばショットキバリアダイオードからなる半導体素子４が固定されている。   On the conductor layer 3 a of the insulating substrate 3, the semiconductor element 4 is fixed by a solder layer 7. The semiconductor element 4 is a power semiconductor element (power device) such as a MOSFET or IGBT. As shown in FIG. 1, a semiconductor element 4 made of, for example, a Schottky barrier diode is fixed on another conductor layer 3a.

ベース板１の周囲は、例えばポリフェニルサルファイド樹脂（ＰＰＳ）またはポリブチレンテレフタレート樹脂（ＰＢＴ）からなるケース２に囲まれている。ケース２の外周には、引き出し用の端子８が設けられている。端子８は、例えば銅やアルミニウムからなる。   The periphery of the base plate 1 is surrounded by a case 2 made of, for example, polyphenyl sulfide resin (PPS) or polybutylene terephthalate resin (PBT). A lead-out terminal 8 is provided on the outer periphery of the case 2. The terminal 8 is made of, for example, copper or aluminum.

半導体素子４の電極（図示せず）と、端子８とは、ボンディングワイヤ６で電気的に接続されている。ボンディングワイヤ６は、例えば銅やアルミニウムからなる。更にケース２の内側には、半導体素子４やボンディングワイヤ６を埋め込むように、封止材５が充填されている。封止材５は、例えばシリコンゲルからなる。   An electrode (not shown) of the semiconductor element 4 and the terminal 8 are electrically connected by a bonding wire 6. The bonding wire 6 is made of, for example, copper or aluminum. Further, the inside of the case 2 is filled with a sealing material 5 so as to bury the semiconductor element 4 and the bonding wire 6. The sealing material 5 is made of, for example, silicon gel.

図２に示すように、導体層３ａと半導体素子４とを接続する半田層７の中には、スペーサとしてワイヤバンプ９が設けられている。ワイヤバンプ９は、半田層７の接合条件で、半田層７の材料と合金形成可能な材料からなる。ワイヤバンプ９は、導体層３ａと半導体素子４とを接続する半田層７の中に載置されていればよいが、例えば図３Ａに示すように、ワイヤループ９ｄの両端の接合部９ａ、９ｂが、ウェッジボンディングにより、導体層３ａと接合していれば位置ずれが発生しないために好ましい。   As shown in FIG. 2, wire bumps 9 are provided as spacers in the solder layer 7 that connects the conductor layer 3 a and the semiconductor element 4. The wire bump 9 is made of a material capable of forming an alloy with the material of the solder layer 7 under the joining condition of the solder layer 7. The wire bump 9 only needs to be placed in the solder layer 7 that connects the conductor layer 3a and the semiconductor element 4. For example, as shown in FIG. 3A, the joints 9a and 9b at both ends of the wire loop 9d are formed. If it is bonded to the conductor layer 3a by wedge bonding, it is preferable because positional displacement does not occur.

上述のようにワイヤバンプ９は、絶縁基板３の導体層３ａの上に、ボンディングワイヤをウェッジボンディングにより固相接合して形成される。図３Ｂは、ワイヤバンプ９の、接合部９ａから接合部９ｂに向かう方向（以下において「長手方向」という。）の断面図ある。図３Ｂから分かるように、ワイヤバンプ９は、両端の接合部９ａ、９ｂを導体層３ａに接合したボンディングワイヤからなることが好ましく、更に、ワイヤバンプ９の高さを均一にするために、接合部９ａ、９ｂに挟まれたワイヤループ部９ｃも導体層３ａに接していることが好ましい。   As described above, the wire bump 9 is formed on the conductor layer 3a of the insulating substrate 3 by solid-phase bonding a bonding wire by wedge bonding. FIG. 3B is a cross-sectional view of the wire bump 9 in a direction (hereinafter referred to as “longitudinal direction”) from the bonding portion 9a to the bonding portion 9b. As can be seen from FIG. 3B, the wire bump 9 is preferably made of a bonding wire in which the joint portions 9a and 9b at both ends are joined to the conductor layer 3a. Further, in order to make the height of the wire bump 9 uniform, the joint portion 9a , 9b is also preferably in contact with the conductor layer 3a.

２つのウェッジボンド接合部９ａ、９ｂの間隔は、２．０ｍｍ以下であることが好ましい。これは、この間隔が２．０ｍｍより長くなると、ボンディングワイヤの一端を導体層３ａにウェッジボンドした後に、他端をウェッジボンドするにあたり、ボンディングワイヤの張力により、ワイヤループ部９ｃを導体層３ａに接するように配置するのが困難になるためである。   The interval between the two wedge bond joints 9a and 9b is preferably 2.0 mm or less. This is because when the distance is longer than 2.0 mm, one end of the bonding wire is wedge-bonded to the conductor layer 3a, and then the other end is wedge-bonded. It is because it becomes difficult to arrange so that it may touch.

また、１本のワイヤバンプ９の両端がウェッジボンド接合されており、更に、その間にも複数のステッチボンド接合部を有する場合も同様に、ワイヤの張力によりワイヤループが形成されてバンプ高さの制御が困難となるため、ウェッジボンド接合部とステッチボンド接合部の間隔、および隣接するステッチボンド接合部の間隔は、それぞれ２．０ｍｍ未満であることが好ましい。   Similarly, when both ends of one wire bump 9 are wedge-bonded and there are a plurality of stitch bond joints between them, a wire loop is formed by the tension of the wire to control the bump height. Therefore, the distance between the wedge bond joint and the stitch bond joint and the distance between adjacent stitch bond joints are preferably less than 2.0 mm.

なお、ワイヤバンプ９を１つの接合部９ａ（または９ｂ）のみで導体層３ａに接合しても良い。   Note that the wire bump 9 may be bonded to the conductor layer 3a only by one bonding portion 9a (or 9b).

ワイヤバンプ９の上部は、半導体素子４の裏面に接し、ワイヤバンプ９が半導体素子４を支持する。   The upper part of the wire bump 9 is in contact with the back surface of the semiconductor element 4, and the wire bump 9 supports the semiconductor element 4.

図４Ａ〜４Ｃは、導体層３ａの上の、ワイヤバンプ９の配置を示す。図４Ａ〜４Ｃは、導体層３ａの上にワイヤバンプ９を接合した状態の上面図で、半田層７より上の部分は、省略している。また、破線１０は、半導体素子４を、導体層３ａの上に垂直投影した半導体素子搭載領域であり、この領域の上に、半導体素子４が載置される。   4A to 4C show the arrangement of the wire bumps 9 on the conductor layer 3a. 4A to 4C are top views of the state in which the wire bumps 9 are joined to the conductor layer 3a, and the portions above the solder layer 7 are omitted. A broken line 10 is a semiconductor element mounting region in which the semiconductor element 4 is vertically projected on the conductor layer 3a, and the semiconductor element 4 is placed on this region.

図４Ａに示すように、ワイヤバンプ９は半導体素子搭載領域１０の四隅に、長手方向が半導体素子搭載領域１０の対角線方向となるように配置されている。ワイヤバンプ９は、半導体素子搭載領域１０の対角線上に配置されても、対角線上ではないが対角線に平行になるように配置されても良い。   As shown in FIG. 4A, the wire bumps 9 are arranged at the four corners of the semiconductor element mounting region 10 so that the longitudinal direction is the diagonal direction of the semiconductor element mounting region 10. The wire bumps 9 may be arranged on a diagonal line of the semiconductor element mounting region 10 or may be arranged so as to be parallel to the diagonal line but not on the diagonal line.

このように、半導体素子搭載領域１０の四隅または四隅近傍にワイヤバンプ９を配置し、半導体素子を支えることにより、半田層７の膜厚をより均一にできる。   Thus, by arranging the wire bumps 9 at or near the four corners of the semiconductor element mounting region 10 and supporting the semiconductor elements, the thickness of the solder layer 7 can be made more uniform.

また、従来は半田７ａと合金形成しないＡｌワイヤ等によりワイヤバンプが形成されていたために、ワイヤバンプの周囲には半田材が濡れ広がらず、半田層７内にボイド（空隙）が発生していた。これに対して、本発明の実施の形態１にかかる電力用半導体装置１００では、上述のように、ワイヤバンプ９は、半田層７の形成条件で、半田層７の半田材と合金形成が可能な材料からなる。このため、ワイヤバンプ９の周囲にも半田材が濡れ広がり、ボイドの発生を防止できる。また、ワイヤバンプ９と半田層７との界面に合金を形成できる。   Conventionally, since wire bumps are formed of Al wires or the like that are not alloyed with the solder 7a, the solder material does not get wet around the wire bumps, and voids (voids) are generated in the solder layer 7. On the other hand, in the power semiconductor device 100 according to the first embodiment of the present invention, as described above, the wire bump 9 can be alloyed with the solder material of the solder layer 7 under the formation conditions of the solder layer 7. Made of material. For this reason, the solder material spreads around the wire bump 9 and the generation of voids can be prevented. Further, an alloy can be formed at the interface between the wire bump 9 and the solder layer 7.

ワイヤバンプ９に使用するワイヤの直径は１００μｍ程度が好ましいが、絶縁基板３と半導体素子４との間の半田層７をより厚くして、接合部の寿命を向上させるために、例えば直径が１５０μｍのワイヤを用いても良い。   The diameter of the wire used for the wire bump 9 is preferably about 100 μm. However, in order to increase the solder layer 7 between the insulating substrate 3 and the semiconductor element 4 and improve the life of the joint, for example, the diameter is 150 μm. A wire may be used.

一方、半導体素子４から発熱する熱をベース板１から外部に効率的に放熱するためには、半田層７の膜厚は薄い方が好ましく、例えば、半田層７の膜厚を５０μｍ程度とするために、ワイヤバンプ９に使用するワイヤの直径は５０μｍ程度としても構わない。   On the other hand, in order to efficiently dissipate the heat generated from the semiconductor element 4 from the base plate 1 to the outside, the solder layer 7 is preferably thin. For example, the solder layer 7 has a thickness of about 50 μm. Therefore, the diameter of the wire used for the wire bump 9 may be about 50 μm.

このように、本発明の実施の形態１では、図４Ａに示すように、半導体素子搭載領域１０の四隅または四隅近傍に位置にワイヤバンプ９を配置することで、半導体素子４の傾きを防止し、絶縁基板３の導体層３ａと半導体素子４を接続する半田層７の膜厚をより均一にすることができる。   As described above, in the first embodiment of the present invention, as shown in FIG. 4A, the wire bumps 9 are arranged at positions near or at the four corners of the semiconductor element mounting region 10 to prevent the inclination of the semiconductor element 4. The film thickness of the solder layer 7 connecting the conductor layer 3a of the insulating substrate 3 and the semiconductor element 4 can be made more uniform.

また、図４Ｂに示すように、図４Ａの配置に加えて、半導体素子搭載領域１０の対角線上に、４つのワイヤバンプ１９を設けても良い。４つのワイヤバンプ１９は、対角線の交点から等距離に設けるのが好ましい。図４Ｂでは、ワイヤバンプ１９の長手方向は、半導体素子搭載領域１０の一辺に平行な方向としたが、他の方向でも構わない。また、ワイヤバンプ１９の個数は４個に限らないが、対角線上に等間隔に配置するのが好ましい。   As shown in FIG. 4B, in addition to the arrangement of FIG. 4A, four wire bumps 19 may be provided on the diagonal line of the semiconductor element mounting region 10. The four wire bumps 19 are preferably provided equidistant from the intersection of the diagonal lines. In FIG. 4B, the longitudinal direction of the wire bump 19 is a direction parallel to one side of the semiconductor element mounting region 10, but may be another direction. Further, the number of wire bumps 19 is not limited to four, but it is preferable to arrange them at equal intervals on a diagonal line.

例えば、半導体素子４を導体層３ａの上にダイボンドする場合、加えられる熱で半導体素子４が反る場合があるが、ワイヤバンプ１９を設けることにより、このような半導体素子４の反りを抑制し、半田層７の膜厚を均一にすることができる。   For example, when the semiconductor element 4 is die-bonded on the conductor layer 3a, the semiconductor element 4 may be warped by the applied heat. However, by providing the wire bump 19, the warp of the semiconductor element 4 is suppressed, The film thickness of the solder layer 7 can be made uniform.

なお、ワイヤバンプ１９は、半導体素子搭載領域１０内に比較的均一に配置されれば良く、特にその位置や個数、配置方向に制限はない。   Note that the wire bumps 19 may be arranged relatively uniformly in the semiconductor element mounting region 10, and there are no particular restrictions on the position, number, and arrangement direction thereof.

また、図４Ｃに示すように、図４Ｂのワイヤバンプ９を、長手方向が半導体素子搭載領域１０の対角線に垂直になるように配置しても良い。   4C, the wire bumps 9 in FIG. 4B may be arranged so that the longitudinal direction is perpendicular to the diagonal line of the semiconductor element mounting region 10.

一般に、半導体素子４の動作時に、半導体素子４と絶縁基板３との線膨張係数の差により半田層７に発生する応力は、半導体素子搭載領域１０の半田層７の四隅近傍に集中し、ここから半田層７に亀裂が進展し始める。   In general, the stress generated in the solder layer 7 due to the difference in linear expansion coefficient between the semiconductor element 4 and the insulating substrate 3 during the operation of the semiconductor element 4 is concentrated near the four corners of the solder layer 7 in the semiconductor element mounting region 10. From this point, cracks start to develop in the solder layer 7.

本発明の実施の形態１では、ワイヤバンプ９は半田層７の半田材と合金形成が可能な材料からなる。そして、通常の半田接合プロセスにおいて、半田層７とワイヤバンプ９との界面に、Ｃｕ６Ｓｎ５やＣｕ３Ｓｎのような合金が形成される。これらの合金は、半田層７に比較して機械的強度が大きく、疲労耐性が高い。なお、これら合金が界面に形成されたワイヤバンプ９の中心部にＣｕが残存していてもよい。In the first embodiment of the present invention, the wire bump 9 is made of a material capable of forming an alloy with the solder material of the solder layer 7. In an ordinary solder joining process, an alloy such as Cu 6 Sn 5 or Cu 3 Sn is formed at the interface between the solder layer 7 and the wire bump 9. These alloys have higher mechanical strength and higher fatigue resistance than the solder layer 7. Note that Cu may remain in the center of the wire bump 9 where these alloys are formed at the interface.

従って、このような機械的強度の大きな合金が表面に形成されたワイヤバンプ９を半導体素子搭載領域１０の四隅に設けることにより、半田層７の四隅で発生した亀裂の進展をワイヤバンプ９で停止できる。特に、ワイヤバンプ９の長手方向が半導体素子搭載領域１０の対角線に垂直になるように配置することにより、亀裂を停止させる効果を大きくできる。   Therefore, by providing the wire bumps 9 formed on the surface with such an alloy having a high mechanical strength at the four corners of the semiconductor element mounting region 10, the progress of cracks generated at the four corners of the solder layer 7 can be stopped by the wire bumps 9. In particular, by arranging the wire bumps 9 so that the longitudinal direction of the wire bumps 9 is perpendicular to the diagonal line of the semiconductor element mounting region 10, the effect of stopping the cracks can be increased.

ワイヤバンプ９の配置は、半導体素子搭載領域１０の対角線にワイヤバンプ９の長手方向が平行な配置（図４Ａ参照）から、垂直な配置（図４Ｃ参照）までの間で、適宜選択可能である。   The arrangement of the wire bumps 9 can be appropriately selected from an arrangement in which the longitudinal direction of the wire bumps 9 is parallel to the diagonal line of the semiconductor element mounting region 10 (see FIG. 4A) to a vertical arrangement (see FIG. 4C).

なお、ワイヤバンプ９に到達して停止した亀裂は、ワイヤバンプ９に沿って進展する場合もあるが、半田層７に発生する応力は四隅から中心方向に発生することから、図４Ｃのように対角線に対して角度を有して配置することで、亀裂進展経路を長くすることが可能となり、半田層７の破壊を遅らせ、結果的に半導体素子４の破壊を遅らせることができる。   The crack that has stopped after reaching the wire bump 9 may develop along the wire bump 9, but the stress generated in the solder layer 7 is generated from the four corners toward the center, so that the diagonal line is formed as shown in FIG. 4C. By arranging with an angle to the crack, it is possible to lengthen the crack propagation path, delay the destruction of the solder layer 7, and consequently delay the destruction of the semiconductor element 4.

ここで、半導体素子４が正方形である場合は、前述のように半導体素子搭載領域１０の対角線に対してワイヤバンプ９の長手方向を垂直に設置するのが最も効果的である。一方、半導体素子４が正方形でない場合は、ワイヤバンプ９の長手方向が半導体素子搭載領域１０の対角線に対して一定の角度を有するように、即ち０°より大きく９０°以下の角度を有するように、ワイヤバンプ９を配置すれば良い。   Here, when the semiconductor element 4 is square, it is most effective to set the wire bump 9 in the longitudinal direction perpendicular to the diagonal line of the semiconductor element mounting region 10 as described above. On the other hand, when the semiconductor element 4 is not square, the longitudinal direction of the wire bump 9 has a certain angle with respect to the diagonal line of the semiconductor element mounting region 10, that is, has an angle greater than 0 ° and 90 ° or less. Wire bumps 9 may be disposed.

また、複数のワイヤバンプ９を、半導体素子搭載領域１０の全体に、ワイヤバンプ９の長手方向が半導体素子搭載領域１０の対角線に対して一定の角度を有するように配置しても良い。この場合、隣接するワイヤバンプ９の間の中心間の距離は、ワイヤバンプ９の直径の２倍程度であることが好ましい。ワイヤバンプ９の接合部の幅は、ワイヤバンプ９の直径の約２倍程度まで超音波接合により広げられることを考慮したものである。   A plurality of wire bumps 9 may be arranged on the entire semiconductor element mounting region 10 such that the longitudinal direction of the wire bumps 9 has a certain angle with respect to the diagonal line of the semiconductor element mounting region 10. In this case, the distance between the centers of the adjacent wire bumps 9 is preferably about twice the diameter of the wire bumps 9. The width of the bonding portion of the wire bump 9 is considered to be expanded by ultrasonic bonding to about twice the diameter of the wire bump 9.

次に、合金形成が可能な半田層７とワイヤバンプ９の材料について説明する。上述のように、ワイヤバンプ９を、半田層７の半田材と合金形成が可能な材料から形成することで、半田層７中でのボイド（空隙）の発生を防止でき、半導体素子４で発生した熱を、半田層７を介して効率良くベース板１から放熱できる。半田層７の半田付け時は還元雰囲気下、例えば水素雰囲気やギ酸雰囲気下でワイヤバンプ９を還元してから半田層７を溶融させる。   Next, the material of the solder layer 7 and the wire bump 9 capable of forming an alloy will be described. As described above, by forming the wire bump 9 from a material capable of forming an alloy with the solder material of the solder layer 7, voids (voids) in the solder layer 7 can be prevented from being generated and generated in the semiconductor element 4. Heat can be efficiently radiated from the base plate 1 through the solder layer 7. When soldering the solder layer 7, the wire bump 9 is reduced in a reducing atmosphere, for example, in a hydrogen atmosphere or a formic acid atmosphere, and then the solder layer 7 is melted.

半田層７には、Ｓｎ系半田、例えば、純Ｓｎ半田、Ｓｎ−Ａｇ−Ｃｕ系半田、Ｓｎ−Ｃｕ系半田、更にはＳｎを主成分としＮｉやＳｂが添加された半田が用いられる。   For the solder layer 7, Sn-based solder, for example, pure Sn solder, Sn-Ag-Cu-based solder, Sn-Cu-based solder, or solder containing Sn and Ni or Sb as a main component is used.

この場合、ワイヤバンプ９の材料には、通常の半田付け条件で、Ｓｎ系の半田材と合金形成が可能な材料としＣｕやＣｕ合金が用いられる。半田層７とワイヤバンプ９の界面に形成される合金は、例えばＣｕ６Ｓｎ５やＣｕ３Ｓｎとなる。In this case, Cu or Cu alloy is used as the material of the wire bump 9 as a material capable of forming an alloy with an Sn-based solder material under normal soldering conditions. An alloy formed at the interface between the solder layer 7 and the wire bump 9 is, for example, Cu 6 Sn 5 or Cu 3 Sn.

表１に、Ｓｎ、Ｃｕ、Ｓｎ−０．７Ｃｕ、Ｃｕ６Ｓｎ５、およびＣｕ３Ｓｎの融点、ヤング率、引張強度、線膨張係数および熱伝導率を示す。Table 1 shows the melting point, Young's modulus, tensile strength, coefficient of linear expansion, and thermal conductivity of Sn, Cu, Sn-0.7Cu, Cu 6 Sn 5 , and Cu 3 Sn.

Figure 2017217369
Figure 2017217369

表１から分かるように、Ｃｕ６Ｓｎ５およびＣｕ３Ｓｎの融点は、半田層７の母材であるＳｎの融点２３２℃より高く、それぞれ４１５℃と６７６℃となっている。また、機械的強度については、ヤング率は、Ｓｎ、Ｃｕ６Ｓｎ５およびＣｕ３Ｓｎについて、それぞれ５３．０ＧＰａ、１１０ＧＰａ、１４０ＧＰａであり、引張強度は、Ｓｎ、Ｃｕ６Ｓｎ５およびＣｕ３Ｓｎについて、それぞれ２８．０ＭＰａ、３１０ＭＰａ、５０７ＭＰａである。As can be seen from Table 1, the melting points of Cu 6 Sn 5 and Cu 3 Sn are higher than the melting point 232 ° C. of Sn, which is the base material of the solder layer 7, and are 415 ° C. and 676 ° C., respectively. As for mechanical strength, Young's modulus is 53.0 GPa, 110 GPa, and 140 GPa for Sn, Cu 6 Sn 5 and Cu 3 Sn, respectively, and tensile strength is Sn, Cu 6 Sn 5 and Cu 3 Sn. , 28.0 MPa, 310 MPa, and 507 MPa, respectively.

このように、半田層７とワイヤバンプ９の界面に形成される合金Ｃｕ６Ｓｎ５およびＣｕ３Ｓｎは、半田層７の母材となるＳｎやＳｎ−０．７Ｃｕ半田よりも融点が高く、機械的強度も大きい、高耐熱性でかつ高信頼性の合金である。Thus, the alloys Cu 6 Sn 5 and Cu 3 Sn formed at the interface between the solder layer 7 and the wire bump 9 have a melting point higher than that of Sn or Sn-0.7Cu solder which is the base material of the solder layer 7, and High heat resistance and high reliability alloy with high mechanical strength.

なお、半田層７とワイヤバンプ９の材料の組み合わせとして、半田層７の材料としてＺｎ系半田材料、ワイヤバンプ９の材料としてＡｌまたはＡｌ合金を組み合わせても良い。   As a combination of the material of the solder layer 7 and the wire bump 9, a Zn-based solder material may be combined as the material of the solder layer 7, and Al or an Al alloy may be combined as the material of the wire bump 9.

絶縁基板３の絶縁部材３ｂには、Ａｌ２Ｏ３、ＡｌＮ、Ｓｉ３Ｎ４等のセラミックスだけでなく、エポキシや液晶ポリマー等のバインダー材に、シリカ、アルミナ、ＢＮ等のフィラーを混練された有機絶縁材料を用いても良い。Insulating member 3b of insulating substrate 3 is not only ceramics such as Al 2 O 3 , AlN, Si 3 N 4 , but also a binder material such as epoxy or liquid crystal polymer is kneaded with fillers such as silica, alumina, and BN. An organic insulating material may be used.

また、絶縁基板３の導体層３ａ、３ｃの材料は、Ｃｕが好ましいが、ＣｕにＮｉめっきが施された材料でも良い。また、ＡｌにＮｉめっきが施された材料でもよい。   Moreover, although the material of the conductor layers 3a and 3c of the insulating substrate 3 is preferably Cu, a material obtained by applying Ni plating to Cu may be used. Alternatively, a material obtained by applying Ni plating to Al may be used.

ベース板１には、例えばＣｕ板やＡｌＳｉＣ板が用いられるが、使用にあたり電力用半導体装置１００が十分な強度を有するのであれば、ベース板１が無い構造、すなわち絶縁基板３の裏面側の導体層３ｃが露出する構造でも良い。   For example, a Cu plate or an AlSiC plate is used as the base plate 1. However, if the power semiconductor device 100 has sufficient strength in use, a structure without the base plate 1, that is, a conductor on the back side of the insulating substrate 3 is used. A structure in which the layer 3c is exposed may be used.

半導体素子４には、高温動作が可能なＳｉＣを基材とするＳｉＣ−ＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）やＳｉＣ−ＳＢＤ（Schottky Barrier Diode）、Ｓｉを基材とするＳｉ−ＩＧＢＴ（Insulated Gate Bipolar Transistor）やＳｉ−ＦＷＤ（Free Wheeling Diode）が用いられる。   The semiconductor element 4 includes SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor) based on SiC capable of high temperature operation, SiC-SBD (Schottky Barrier Diode), Si-IGBT (Insulated Gate) based on Si. Bipolar transistors) and Si-FWDs (Free Wheeling Diodes) are used.

ボンディングワイヤ６は、例えばＡｌワイヤであり、ウェッジボンディングにより半導体素子４の表面に接合される。ボンディングワイヤ６は、例えばＣｕワイヤでも良い。また、ボンディングワイヤ６の代わりに、板状の導体を用いても良い。板状の導体を用いる場合は、半導体素子４との接合は、ウェッジボンディングではなく、半導体素子４の上面に例えばＮｉ／Ａｕめっきを施し、その上に半田やＡｇ焼結材により板状の導体を接合する。   The bonding wire 6 is an Al wire, for example, and is bonded to the surface of the semiconductor element 4 by wedge bonding. The bonding wire 6 may be a Cu wire, for example. Further, instead of the bonding wire 6, a plate-like conductor may be used. When using a plate-like conductor, the bonding with the semiconductor element 4 is not wedge bonding, for example, Ni / Au plating is performed on the upper surface of the semiconductor element 4, and then the plate-like conductor is formed by solder or Ag sintered material. Join.

封止材５は、例えばシリコンゲルであるが、使用にあたり十分な絶縁性を有していればよく、フィラーが混練されたエポキシ材であっても良い。   The sealing material 5 is, for example, silicon gel, as long as it has sufficient insulating properties for use, and may be an epoxy material in which a filler is kneaded.

実施の形態２．
図５は、本発明の実施の形態２にかかる電力用半導体装置２００の一部の拡大断面図であり、図１と同一符号は、同一または相当箇所を示す。電力用半導体装置２００では、ベース板１と絶縁基板３の導体層３ｃとの間に、半田層７の材料と合金形成が可能なワイヤバンプ２９が設けられている。Embodiment 2. FIG.
FIG. 5 is an enlarged sectional view of a part of the power semiconductor device 200 according to the second embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same or corresponding parts. In the power semiconductor device 200, a wire bump 29 capable of forming an alloy with the material of the solder layer 7 is provided between the base plate 1 and the conductor layer 3 c of the insulating substrate 3.

ワイヤバンプ２９は、実施の形態１の配置と原則的に同一であり、例えば絶縁基板３の導体層３ｃの直下、即ち、導体層３ｃをベース板１の上に垂直投影した矩形形状の導体層搭載領域（実施の形態１の半導体素子搭載領域に対応）の例えば四隅に、導体層搭載領域の対角線に対して並行に設置しても良い。このようにワイヤバンプ２９を形成することにより、半田層７の膜厚を均一にすることができる。ワイヤバンプ２９は、例えば図４Ｂのように、複数設けても良い。   The wire bump 29 is basically the same as the arrangement of the first embodiment. For example, the wire bump 29 is mounted directly below the conductor layer 3 c of the insulating substrate 3, that is, a rectangular conductor layer mounted by vertically projecting the conductor layer 3 c on the base plate 1. For example, four corners of the region (corresponding to the semiconductor element mounting region of the first embodiment) may be installed in parallel to the diagonal line of the conductor layer mounting region. By forming the wire bumps 29 in this way, the thickness of the solder layer 7 can be made uniform. A plurality of wire bumps 29 may be provided as shown in FIG. 4B, for example.

また、ワイヤバンプ２９は、例えば実施の形態１の図４Ｃのように、導体層搭載領域の四隅または四隅近傍に、導体層搭載領域の対角線に対して０°より大きく９０°以下の角度で、特に９０°に設けても良い。これにより、ベース板１と絶縁基板３との線膨張係数の差により、四隅近傍から半田層７に亀裂が進展した場合でも、ワイヤバンプ２９で亀裂の進展を停止できる。   Further, as shown in FIG. 4C of the first embodiment, for example, the wire bumps 29 are formed at the four corners of the conductor layer mounting region or in the vicinity of the four corners at an angle greater than 0 ° and 90 ° or less with respect to the diagonal line of the conductor layer mounting region. It may be provided at 90 °. Thereby, even when cracks propagate from the vicinity of the four corners to the solder layer 7 due to the difference in linear expansion coefficient between the base plate 1 and the insulating substrate 3, the progress of the cracks can be stopped by the wire bumps 29.

また、ワイヤバンプ２９を、半田層７と合金形成が可能な材料から形成することで、半田層７中でのボイド（空隙）の発生を防止でき、半導体素子４で発生した熱を、半田層７を介して効率良くベース板１から放熱できる。   Further, by forming the wire bump 29 from a material capable of forming an alloy with the solder layer 7, it is possible to prevent the generation of voids (voids) in the solder layer 7, and the heat generated in the semiconductor element 4 is transferred to the solder layer 7. Can efficiently dissipate heat from the base plate 1.

なお、ワイヤバンプ２９と半田層７との材料の組み合わせは、実施の形態１の組み合わせと同様である。   The material combination of the wire bump 29 and the solder layer 7 is the same as that of the first embodiment.

ここで、ワイヤバンプ９の直径は、２００μｍ程度であることが好ましいが、絶縁基板３とベース板１との間の半田層７の膜厚を３００μｍ以上にして接合部寿命構造向上を図るのであれば、ワイヤバンプ９の直径は３００μｍ程度でも良い。また、半導体素子４からの熱をベース板１から効率的に放熱するために、半田層７を１００μｍ程度と薄くするのであれば、ワイヤバンプ９の直径は１００μｍ程度でも良い。   Here, the diameter of the wire bump 9 is preferably about 200 μm. However, if the thickness of the solder layer 7 between the insulating substrate 3 and the base plate 1 is set to 300 μm or more, the junction life structure can be improved. The diameter of the wire bump 9 may be about 300 μm. If the solder layer 7 is thinned to about 100 μm in order to efficiently dissipate heat from the semiconductor element 4 from the base plate 1, the diameter of the wire bump 9 may be about 100 μm.

図６Ａは、絶縁基板３を半田付けする前の、ベース板１の上面図である。また、図６Ｂは、図６ＡをＡ−Ａ方向に見た場合の断面図である。   FIG. 6A is a top view of the base plate 1 before the insulating substrate 3 is soldered. 6B is a cross-sectional view of FIG. 6A when viewed in the AA direction.

図６Ａ、６Ｂに示すように、ベース板１の上の、半田層形成領域２０には、複数のワイヤバンプ３９が設けられている。ワイヤバンプ３９は、半田層形成領域２０の対角線に所定の角度となるように設けられている。１つの対角線上に配置されたワイヤバンプ３９は、互いに平行で、等間隔に配置されるのが好ましい。また、図６Ａ、６Ｂでは、半田付け時に、半田層形成領域２０の外に半田が濡れ広がるのを防止するために、フォトレジスト１１で半田層形成領域２０を囲んでいる。また、図６Ａ、６Ｂは４本のワイヤにより領域を区分けするために、４辺を囲むようにワイヤバンプを載置したが、これが１本のワイヤによりステッチボンドを用いて４辺を囲むように載置してもよく、ワイヤを載置していない領域を半田が濡れ広がることから各ワイヤが端部で接触しないようにしておかなければならない。   As shown in FIGS. 6A and 6B, a plurality of wire bumps 39 are provided in the solder layer forming region 20 on the base plate 1. The wire bumps 39 are provided at a predetermined angle with the diagonal line of the solder layer forming region 20. The wire bumps 39 arranged on one diagonal line are preferably parallel to each other and arranged at equal intervals. 6A and 6B, the solder layer forming region 20 is surrounded by the photoresist 11 in order to prevent the solder from spreading outside the solder layer forming region 20 during soldering. 6A and 6B, in order to divide the region by four wires, wire bumps are placed so as to surround the four sides, but this is placed so as to surround the four sides using a stitch bond with one wire. Since the solder spreads out in the area where the wire is not placed, each wire must be kept from contacting at the end.

このようにワイヤバンプ３９を設けることにより、半田層７の膜厚を均一にするとともに、ワイヤバンプ３９の材料を半田層７の材料と合金形成が可能な材料から形成することにより、半田層７中でのボイド（空隙）の発生を防止できる。   By providing the wire bumps 39 in this manner, the film thickness of the solder layer 7 is made uniform, and the material of the wire bumps 39 is formed of a material that can be alloyed with the material of the solder layer 7. Generation of voids (voids) can be prevented.

特に、ワイヤバンプ３９を図６Ａのような配置とすることで、ベース板１と絶縁基板３との線膨張係数の差により半田層７の四隅に亀裂が形成された場合でも、ワイヤバンプ３９により亀裂の進展を停止できる。特に、複数のワイヤバンプ３９を設けることで、亀裂の進展経路が長くなり、半田層７の寿命が向上する。   In particular, by arranging the wire bumps 39 as shown in FIG. 6A, even if cracks are formed at the four corners of the solder layer 7 due to the difference in linear expansion coefficient between the base plate 1 and the insulating substrate 3, the cracks are caused by the wire bumps 39. You can stop progress. In particular, by providing a plurality of wire bumps 39, the crack propagation path becomes longer and the life of the solder layer 7 is improved.

ここで、例えば半田層７の材料としてＳｎ−０．７Ｃｕ半田を、ワイヤバンプ３９の材料としてＣｕを用いた場合、Ｃｕ−Ｓｎの状態図から分かるように、ＣｕはＳｎに、室温で０．７ｗｔ％しか固溶できない。このため、半田付け時にＳｎ−０．７Ｃｕを溶融した後、室温に冷却すると、固溶できないＣｕは、Ｃｕからなるワイヤバンプ３９の周囲に析出して合金を形成する。半田付け後は、Ｃｕワイヤバンプ３９はそのままＣｕ材として存在する。   Here, for example, when Sn-0.7Cu solder is used as the material of the solder layer 7 and Cu is used as the material of the wire bump 39, as can be seen from the Cu-Sn phase diagram, Cu is 0.7 wt. % Can only be dissolved. For this reason, when Sn-0.7Cu is melted at the time of soldering and then cooled to room temperature, Cu that cannot be dissolved is precipitated around the wire bumps 39 made of Cu to form an alloy. After the soldering, the Cu wire bump 39 exists as a Cu material as it is.

Ｃｕの熱伝導率は４０１Ｗ／ｍ・Ｋであり、熱伝導率が６６．８Ｗ／ｍ・ＫであるＳｎおよびＳｎ−Ｃｕ合金に比較して大きい。このため、半田層７とワイヤバンプ３９からなる接合部のみかけの熱伝導率は大きくなり、ワイヤバンプ３９がない半田層７のみの場合に比較して、放熱性を向上させることが可能となる。   The thermal conductivity of Cu is 401 W / m · K, which is higher than that of Sn and Sn—Cu alloys having a thermal conductivity of 66.8 W / m · K. For this reason, the apparent thermal conductivity of the joint portion composed of the solder layer 7 and the wire bump 39 is increased, and the heat dissipation can be improved as compared with the case of only the solder layer 7 without the wire bump 39.

また、半田は、液相から固相に凝固する際に体積収縮が起こる。このため、半田付け後の冷却過程において、ベース板１の温度分布に伴って、半田層７の中にいわゆる引け巣が発生する場合がある。これに対して、図６Ａ、６Ｂに示すようにワイヤバンプ３９を配置することにより、ワイヤバンプ３９によって、半田が収縮する領域が区切られ、引け巣の発生を抑制し、半田不良を低減できる。   Solder also shrinks in volume when it solidifies from a liquid phase to a solid phase. For this reason, in the cooling process after soldering, a so-called shrinkage nest may be generated in the solder layer 7 with the temperature distribution of the base plate 1. On the other hand, by arranging the wire bumps 39 as shown in FIGS. 6A and 6B, the regions where the solder contracts are delimited by the wire bumps 39, the occurrence of shrinkage cavities can be suppressed, and solder defects can be reduced.

また、図６Ａに示すワイヤバンプ３９は、例えば、直径が２００μｍのＣｕワイヤからなるワイヤバンプ３９を、４００μｍの間隔でボンディングして形成しても良い。これは、ワイヤバンプ３９の間隔を狭くすると、ボンディング時に隣接するワイヤバンプ３９にウェッジツールが接触してしまい、所望の接合を得られなくなるためである。このため、隣接するワイヤバンプ３９の間隔は、ワイヤバンプ３９の直径の１．５倍以上であることが好ましい。   The wire bump 39 shown in FIG. 6A may be formed by bonding, for example, wire bumps 39 made of Cu wire having a diameter of 200 μm at intervals of 400 μm. This is because if the interval between the wire bumps 39 is narrowed, the wedge tool comes into contact with the adjacent wire bumps 39 at the time of bonding, and a desired joint cannot be obtained. For this reason, the interval between adjacent wire bumps 39 is preferably 1.5 times or more the diameter of the wire bumps 39.

また、１本のワイヤバンプ３９の両端がベース板１にウェッジボンド接合されており、更に、その間にも複数のステッチボンド接合部を有する場合は、ワイヤの張力によりワイヤループが形成されてバンプ高さの制御が困難となる。このため、ワイヤループを形成させないために、ウェッジボンド接合部とステッチボンド接合部との間隔、および隣接するステッチボンド接合部の間隔は、それぞれ２．０ｍｍ未満であることが好ましい。   In addition, when both ends of one wire bump 39 are wedge-bonded to the base plate 1 and there are a plurality of stitch bond joints between them, a wire loop is formed by the tension of the wire, and the bump height is increased. It becomes difficult to control. For this reason, in order not to form a wire loop, it is preferable that the distance between the wedge bond joint and the stitch bond joint and the distance between adjacent stitch bond joints are each less than 2.0 mm.

実施の形態１では、絶縁基板３と半導体素子４との間の半田層７中にワイヤバンプを設けた電力用半導体装置１００について、実施の形態２では、ベース板１と絶縁基板３との間の半田層７中にワイヤバンプを設けた電力用半導体装置２００について、それぞれ説明したが、１つの電力用半導体装置が双方のワイヤバンプを備えても良い。なお、半田付け面積が大きく半田付け時の体積収縮量が大きいベース板１と絶縁基板３との間の半田層７中にワイヤバンプ９を載置するほうが、引け巣抑制効果が大きい。   In the first embodiment, the power semiconductor device 100 in which wire bumps are provided in the solder layer 7 between the insulating substrate 3 and the semiconductor element 4, in the second embodiment, between the base plate 1 and the insulating substrate 3. The power semiconductor device 200 provided with the wire bumps in the solder layer 7 has been described. However, one power semiconductor device may include both wire bumps. In addition, it is more effective to place the wire bumps 9 in the solder layer 7 between the base plate 1 and the insulating substrate 3 having a large soldering area and a large volume shrinkage during soldering.

また、実施の形態１に記載されたベース板１と絶縁基板３との間の半田層７と、実施の形態２に記載された絶縁基板３と半導体素子４との間の半田層７は、同じ材料でも、異なる材料でも良い。   Further, the solder layer 7 between the base plate 1 and the insulating substrate 3 described in the first embodiment and the solder layer 7 between the insulating substrate 3 and the semiconductor element 4 described in the second embodiment are: The same material or different materials may be used.

１ ベース板、２ ケース、３ 絶縁基板、４ 半導体素子、５ 封止材、６ ボンディングワイヤ、７ 半田層、８ 端子、９ ワイヤバンプ、１０ 半導体素子搭載領域、１１ フォトレジスト、２０ 半田層形成領域、１００、２００ 電力用半導体装置。   DESCRIPTION OF SYMBOLS 1 Base plate, 2 Case, 3 Insulating substrate, 4 Semiconductor element, 5 Sealing material, 6 Bonding wire, 7 Solder layer, 8 Terminal, 9 Wire bump, 10 Semiconductor element mounting area, 11 Photoresist, 20 Solder layer formation area, 100, 200 Power semiconductor device.

Claims (17)

少なくとも表面に導体層を有する絶縁基板と、
該導体層の上に設けられたワイヤバンプと、
該ワイヤバンプの上に載置された半導体素子と、
該導体層の上に該導体層と該半導体素子とを接合する半田層と、を含み、
該ワイヤバンプと該半田層との界面に、該ワイヤバンプの材料と該半田層の材料からなる合金を有することを特徴とする電力用半導体装置。An insulating substrate having a conductor layer on at least the surface;
Wire bumps provided on the conductor layer;
A semiconductor element mounted on the wire bump;
A solder layer that joins the conductor layer and the semiconductor element on the conductor layer;
A power semiconductor device comprising an alloy comprising a material of the wire bump and a material of the solder layer at an interface between the wire bump and the solder layer. 上記ワイヤバンプの熱伝導率は、上記半田層の熱伝導率より大きいことを特徴とする請求項１に記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein a thermal conductivity of the wire bump is larger than a thermal conductivity of the solder layer. 上記ワイヤバンプは、その両端が上記導体層にウェッジボンド接合部を有するボンディングワイヤからなることを特徴とする請求項１に記載の電力用半導体装置。   2. The power semiconductor device according to claim 1, wherein both ends of the wire bumps are made of bonding wires having wedge bond joints on the conductor layer. 3. 更に、ウェッジボンド接合部の間に、上記ボンディングワイヤが上記導体層に複数のステッチボンド接合部を有し、該ウェッジボンド接合部と該ステッチボンド接合部との間隔、および隣接する該ステッチボンド接合部の間隔は、それぞれ２ｍｍ以下であることを特徴とする請求項３に記載の電力用半導体装置。   In addition, the bonding wire has a plurality of stitch bond joints in the conductor layer between the wedge bond joints, the distance between the wedge bond joint and the stitch bond joint, and the adjacent stitch bond joints. The power semiconductor device according to claim 3, wherein the interval between the portions is 2 mm or less. 上記半導体素子を、上記導体層の上に垂直投影した、矩形形状の半導体素子搭載領域において、該半導体素子搭載領域の四隅にそれぞれ上記ワイヤバンプが設けられたことを特徴とする請求項１に記載の電力用半導体装置。   The rectangular bump-shaped semiconductor element mounting region obtained by vertically projecting the semiconductor element onto the conductor layer includes the wire bumps provided at four corners of the semiconductor element mounting region, respectively. Power semiconductor device. 上記ワイヤバンプの長手方向は、上記半導体素子搭載領域の対角線と直交することを特徴とする請求項５に記載の電力用半導体装置。   6. The power semiconductor device according to claim 5, wherein a longitudinal direction of the wire bump is orthogonal to a diagonal line of the semiconductor element mounting region. 上記ワイヤバンプの長手方向は、上記半導体素子搭載領域の対角線と、０°より大きく９０°以下の角度で交差することを特徴とする請求項５に記載の電力用半導体装置。   6. The power semiconductor device according to claim 5, wherein a longitudinal direction of the wire bump intersects with a diagonal line of the semiconductor element mounting region at an angle greater than 0 ° and not greater than 90 °. 上記半導体素子搭載領域中に、更に上記ワイヤバンプが設けられたことを特徴とする請求項５〜７のいずれかに記載の電力用半導体装置。   The power semiconductor device according to claim 5, wherein the wire bump is further provided in the semiconductor element mounting region. ベース板と、
該ベース板の上に設けられた複数のワイヤバンプと、
該ワイヤバンプの上に載置された、少なくとも裏面に導体層を有する絶縁基板と、
該ベース板の上に該絶縁基板の該導体層を接合する半田層と、を含み、
該ワイヤバンプと該半田層との界面に、該ワイヤバンプの材料と該半田層の材料からなる合金が形成されたことを特徴とする電力用半導体装置。A base plate,
A plurality of wire bumps provided on the base plate;
An insulating substrate placed on the wire bump and having a conductor layer on at least the back surface;
A solder layer that joins the conductor layer of the insulating substrate on the base plate,
A power semiconductor device, wherein an alloy made of a material of the wire bump and a material of the solder layer is formed at an interface between the wire bump and the solder layer. 上記ワイヤバンプの熱伝導率は、上記半田層の熱伝導率より大きいことを特徴とする請求項９に記載の電力用半導体装置。   The power semiconductor device according to claim 9, wherein a thermal conductivity of the wire bump is larger than a thermal conductivity of the solder layer. 上記ワイヤバンプは、その両端が上記導体層にウェッジボンド接合されたウェッジボンド接合部と、該ウェッジボンド接合部の間に、ボンディングワイヤが上記導体層にステッチボンド接合された複数のステッチボンド接合部を有し、該ウェッジボンド接合部と該ステッチボンド接合部との間隔、および隣接する該ステッチボンド接合部の間隔は、それぞれ２．０ｍｍ以下であることを特徴とする請求項９に記載の電力用半導体装置。   The wire bump has a wedge bond bonded portion in which both ends are wedge bonded to the conductor layer, and a plurality of stitch bond bonded portions in which a bonding wire is stitch bonded to the conductor layer between the wedge bond bonded portions. 10. The power use according to claim 9, wherein a distance between the wedge bond joint and the stitch bond joint and a distance between adjacent stitch bond joints are each 2.0 mm or less. Semiconductor device. 上記導体層を、上記ベース板の上に垂直投影した、矩形形状の導体層搭載領域において、該半導体素子搭載領域の四隅にそれぞれ上記ワイヤバンプが設けられたことを特徴とする請求項９に記載の電力用半導体装置。   10. The rectangular conductor layer mounting region obtained by vertically projecting the conductor layer on the base plate, wherein the wire bumps are provided at four corners of the semiconductor element mounting region, respectively. Power semiconductor device. 上記ワイヤバンプの長手方向は、上記導体層搭載領域の対角線と、０°より大きく９０°以下の角度で交差することを特徴とする請求項１２に記載の電力用半導体装置。   13. The power semiconductor device according to claim 12, wherein a longitudinal direction of the wire bump intersects with a diagonal line of the conductor layer mounting region at an angle greater than 0 ° and not greater than 90 °. 上記ベース板の上に、上記半田層が設けられる半田層形成領域を有し、該半田層形成領域の四隅、および該半田層形成領域の内部に上記ワイヤバンプが設けられたことを特徴とする請求項９に記載の電力用半導体装置。   A solder layer forming region on which the solder layer is provided is provided on the base plate, and the wire bumps are provided in four corners of the solder layer forming region and in the solder layer forming region. Item 10. The power semiconductor device according to Item 9. 上記ワイヤバンプはＣｕからなり、上記半田層はＳｎ系半田材料からなることを特徴とする請求項１〜１４のいずれかに記載の電力用半導体装置。   The power semiconductor device according to claim 1, wherein the wire bump is made of Cu, and the solder layer is made of an Sn-based solder material. 上記ワイヤバンプの材料と半田層の材料からなる合金は、Ｃｕ６Ｓｎ５またはＣｕ３Ｓｎであることを特徴とする請求項１５に記載の電力用半導体装置。16. The power semiconductor device according to claim 15, wherein the alloy made of the wire bump material and the solder layer material is Cu 6 Sn 5 or Cu 3 Sn. 上記ベース板と上記絶縁基板との間の上記半田層と、上記絶縁基板と上記半導体素子との間の上記半田層とが、異なる材料からなることを特徴とする請求項１〜１６のいずれかに記載の電力用半導体装置。   The solder layer between the base plate and the insulating substrate and the solder layer between the insulating substrate and the semiconductor element are made of different materials. The power semiconductor device according to the above.
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