JP2012028433A - Packaging method of electronic component - Google Patents

Packaging method of electronic component Download PDF

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JP2012028433A
JP2012028433A JP2010163779A JP2010163779A JP2012028433A JP 2012028433 A JP2012028433 A JP 2012028433A JP 2010163779 A JP2010163779 A JP 2010163779A JP 2010163779 A JP2010163779 A JP 2010163779A JP 2012028433 A JP2012028433 A JP 2012028433A
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electronic component
conductive
layer
substrate
coating agent
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Masashi Kikuchi
昌司 菊池
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NEC Network Products Ltd
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NEC Network Products Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/292—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Abstract

PROBLEM TO BE SOLVED: To bury a plurality of conductive solid spacers which regulate the interval of a substrate and an electronic component at predetermined positions in a bonding layer which bond the substrate and electronic component, by a simple process at a low cost.SOLUTION: In a packaging method of an electronic component each of the following steps are sequentially implemented: A step (1A) for forming a coating agent layer 21 by applying a paste-like coating agent containing a solvent and a conductive material which is in solid state at normal temperature and melted by heating onto a substrate 10, a step (1B) for burying a plurality of conductive solid spacers 23 which do not change the shape by heating and regulate the interval of the substrate 10 and an electronic component 30 in the coating agent layer 21, a step (1C) for mounting the electronic component 30 on the coating agent layer 21, and a step (1D) for bonding the electronic component 30 to the substrate 10 by heating the substrate 10 while pressing the electronic component 30 against the substrate 10, melting the conductive material in the coating agent layer 21, and then solidifying the conductive material again by natural temperature drop or cooling.

Description

本発明は、電子部品の実装方法に関するものである。   The present invention relates to an electronic component mounting method.

従来、基材上への半導体チップ等の電子部品の実装は主に、リフロー法による半田接合によって実施されている。
図３（Ａ）〜（Ｄ）を参照して、従来のリフロー法を用いた電子部品の実装方法について説明する。図３（Ａ）〜（Ｄ）は工程図であり、各図は断面図を示している。 Conventionally, electronic components such as semiconductor chips are mounted on a substrate mainly by soldering using a reflow method.
An electronic component mounting method using a conventional reflow method will be described with reference to FIGS. 3A to 3D are process diagrams, and each drawing shows a cross-sectional view.

図３（Ａ）に示す基材１１０に対して、図３（Ｂ）に示すように、半田と溶剤を含む半田ペーストを塗布（印刷）して、半田ペースト層１２１を形成する。この上に、図３（Ｃ）に示すように、電子部品１３０を載置する。
図３（Ｃ）に示す状態で加熱を行うと、半田ペースト１２１中の溶剤は揮発し、半田は溶融する。基材１１０が常温まで降温すると、図３（Ｄ）に示すように、半田が固化して半田接合層１２０が形成される。
以上のようにして、基材１１０と電子部品１３０とが半田接合層１２０を介して電気的に接合された実装品１００が得られる。 As shown in FIG. 3B, a solder paste containing solder and a solvent is applied (printed) to the base material 110 shown in FIG. On this, as shown in FIG.3 (C), the electronic component 130 is mounted.
When heating is performed in the state shown in FIG. 3C, the solvent in the solder paste 121 volatilizes and the solder melts. When the temperature of the substrate 110 is lowered to room temperature, the solder is solidified and the solder bonding layer 120 is formed as shown in FIG.
As described above, the mounted product 100 in which the base 110 and the electronic component 130 are electrically bonded via the solder bonding layer 120 is obtained.

上記の電子部品の実装方法において、半田接合層１２０の高さ（厚み）Ｈは、塗布された半田ペーストの量とリフロー条件によって概ね決まるが、半田のセルフアライメントによる表面張力と半田が溶融する際の熱の加わり方による溶融偏りによって変化するため、面内ばらつきが生じる場合がある。例えば、図４（Ａ）に示すように、基材１１０に対して電子部品１３０が傾いて実装されることがある。   In the above electronic component mounting method, the height (thickness) H of the solder bonding layer 120 is generally determined by the amount of applied solder paste and the reflow conditions. In-plane variation may occur due to a change in the melting bias due to the heat applied. For example, as shown in FIG. 4A, the electronic component 130 may be mounted inclined with respect to the base 110.

半田接合層１２０の高さＨの面内ばらつきが生じると、応力集中が起こる部分が発生する場合がある。
実装品１００は常に温度変化等の外部環境変化によって熱膨張と熱収縮が繰り返されており、この熱膨張と熱収縮によって実装品１００に応力が加わる。この際、半田接合層１２０の高さＨの面内ばらつきによって生じた応力集中部分があると、図４（Ｂ）に示すように、応力集中部分を起点として、基材１１０及び／又は電子部品１３０にクラックＣ等の破損が発生する恐れがある。 When in-plane variation of the height H of the solder bonding layer 120 occurs, a portion where stress concentration occurs may occur.
The mounted product 100 is constantly subjected to thermal expansion and thermal contraction due to changes in the external environment such as temperature changes, and stress is applied to the mounted product 100 due to the thermal expansion and thermal contraction. At this time, if there is a stress concentration portion caused by the in-plane variation of the height H of the solder bonding layer 120, the base 110 and / or the electronic component starts from the stress concentration portion as shown in FIG. 4B. There is a possibility that damage such as crack C may occur in 130.

半田接合層１２０の高さＨの面内ばらつきはまた、熱の拡散にも偏りを発生させ、放熱性の良くない部分が生じる場合もある。
電子部品１３０を動作させると、熱が発生する。そこで、例えば図４（Ｃ）に示すように、電子部品１３０上にヒートシンク１５０を搭載することで、放熱Ｅを行っている。この放熱Ｅの他に、基材１１０の裏面側からの放熱Ｆもある。
基材１１０の裏面側からの放熱Ｆに関しては、半田接合層１２０の高さＨの面内ばらつきがあると、基材１１０側への放熱性にばらつきが生じ、放熱性の良くない部分が生じる恐れがある。図４（Ｃ）に示すように、半田接合層１２０の高さＨの薄い部分からの放熱量が多く、厚い部分からの放熱量が少なくなる傾向にある。 The in-plane variation in the height H of the solder bonding layer 120 may also cause a bias in heat diffusion, resulting in a portion with poor heat dissipation.
When the electronic component 130 is operated, heat is generated. Therefore, for example, as shown in FIG. 4C, heat dissipation E is performed by mounting a heat sink 150 on the electronic component 130. In addition to this heat dissipation E, there is also heat dissipation F from the back side of the substrate 110.
Regarding the heat dissipation F from the back surface side of the base material 110, if there is an in-plane variation in the height H of the solder bonding layer 120, the heat dissipation performance to the base material 110 side varies, and a portion with poor heat dissipation results. There is a fear. As shown in FIG. 4C, the heat radiation amount from the thin portion of the solder bonding layer 120 having a high height H is large, and the heat radiation amount from the thick portion tends to be small.

なお、図４（Ａ）〜（Ｃ）においては、視認しやすくするため、上記問題を誇張して図示している。   In FIGS. 4A to 4C, the above problem is exaggerated for easy visual recognition.

上記のように、応力集中部分と放熱性の良くない部分の発生を抑制するために、半田接合層の高さを面内均一にすることが、実装品の信頼性を上げる重要な要素となっている。   As described above, in order to suppress the occurrence of stress concentration parts and parts with poor heat dissipation, it is an important factor to improve the reliability of the mounted product by making the solder bonding layer height in-plane uniform. ing.

また、電子部品の発熱時に、基材と電子部品との間の熱膨張係数差によって応力（熱応力）が発生し、実装品の反りやクラック等が生じる場合がある。したがって、基材と電子部品との間の熱膨張係数差による熱応力を緩和できることが好ましい。   In addition, when the electronic component generates heat, stress (thermal stress) is generated due to a difference in thermal expansion coefficient between the base material and the electronic component, and the mounted product may be warped or cracked. Therefore, it is preferable that the thermal stress due to the difference in thermal expansion coefficient between the substrate and the electronic component can be relaxed.

特許文献１には、半導体素子（１５Ａ）の角部に対応する領域の半田（１８）に、金属粉（１９）を混入させた回路装置が開示されている（請求項１、図１（ｃ）、図２）。
特許文献１には、単一粒径の金属粉（１９）を用いることにより、半田（１８）の厚みを正確にコントロールすることができ、例えば、粒径が１００μｍの金属粉（１９）を半田（１８）に混入させることにより、半田（１８）の厚みを１００μｍ程度以上にすることができることが記載されている（段落００３０）。 Patent Document 1 discloses a circuit device in which metal powder (19) is mixed in solder (18) in a region corresponding to a corner of a semiconductor element (15A) (Claim 1, FIG. 1 (c). ), FIG. 2).
In Patent Document 1, the thickness of the solder (18) can be accurately controlled by using the metal powder (19) having a single particle diameter. For example, the metal powder (19) having a particle diameter of 100 μm is soldered. It is described that the thickness of the solder (18) can be increased to about 100 μm or more by mixing in (18) (paragraph 0030).

特許文献１には、半導体素子の発熱時に、基板と半導体素子との熱膨張係数差によって熱応力が発生することが記載されている（段落０００５）。
特許文献１では、半導体素子の角部に対応する領域の半田に、半田よりも熱膨張係数の小さい金属粉を混入させることにより、基板と半導体素子との熱膨張係数差による熱応力を低減できると記載されている（段落００３４）。 Patent Document 1 describes that when a semiconductor element generates heat, thermal stress is generated due to a difference in thermal expansion coefficient between the substrate and the semiconductor element (paragraph 0005).
In Patent Document 1, thermal stress due to a difference in thermal expansion coefficient between a substrate and a semiconductor element can be reduced by mixing metal powder having a smaller thermal expansion coefficient than that of solder into a solder corresponding to a corner portion of the semiconductor element. (Paragraph 0034).

特許文献１には、ランド（１３Ａ）上に金属粉（１９）を含まない溶融状態の第２の半田（２２）を形成し、その上に金属粉（１９）を含むペースト状あるいは粉状の第１の半田（２１）を載置し、その後リフロー工程を実施する実装方法が記載されている（図３（Ａ）〜（Ｃ）及び図４（Ａ）〜（Ｃ））。
特許文献１には、リフロー工程により、半田は溶融するが、金属粉（１９）は溶融せずに固体のままで存在するため、角部に配置された金属粉（１９）により、所定の厚みが確保され、半導体素子（１５Ａ）が傾くことが抑止されると記載されている（段落００３９）。 In Patent Document 1, a second solder (22) in a molten state not including metal powder (19) is formed on a land (13A), and a paste or powder including metal powder (19) is formed thereon. A mounting method is described in which the first solder (21) is placed and then the reflow process is performed (FIGS. 3A to 3C and 4A to 4C).
In Patent Document 1, the solder is melted by the reflow process, but the metal powder (19) remains in a solid state without being melted. Therefore, the metal powder (19) disposed at the corners has a predetermined thickness. Is ensured and the semiconductor element (15A) is prevented from tilting (paragraph 0039).

特許文献２には、回路基板（２１）上の接合部と半導体素子（２２）との間に、半田付け温度で溶融可能な接合金属（１２）と、半田付け温度で溶融不能かつ誘導加熱可能な位置決め金属（１３）とを含む接合金属層（１１）を備えた半導体装置が開示されている（請求項１、図１、図２）。
位置決め金属（１３）の形状としては、球体、立方体、及び多面体等が挙げられている（段落００２６）。
特許文献２には、位置決め金属（１３）の粒径が接合金属（１２）の厚さとほぼ同じであり、各位置決め金属（１３）が接合金属（１２）に完全に埋設された状態が好ましいと記載されている（段落００２７）。
特許文献２には、回路基板（２１）の金属回路（２３）上に、接合金属（１２）と位置決め金属（１３）とを含む金属接合材料（１１）を介して半導体素子（２２）を配置し、その後、高周波加熱コイル（３６）に高周波電流を流して高周波の磁束を発生させ、これによって接合金属（１２）を溶融させる誘導加熱を実施して、金属回路（２３）と半導体素子（２２）とを接合する方法が記載されている（段落００３７、００４０）。
特許文献２には、半導体素子（２２）上に錘（４１）を載置した状態で、上記誘導加熱を実施する方法も記載されている（段落００５４）。
特許文献２には、位置決め金属１３によって半導体素子２２が傾くのが抑制されることが記載されている（段落００４５）。 In Patent Document 2, a bonding metal (12) that can be melted at a soldering temperature between a bonding portion on a circuit board (21) and a semiconductor element (22), and that cannot be melted at the soldering temperature and can be induction-heated. A semiconductor device having a bonding metal layer (11) including a positioning metal (13) is disclosed (claims 1, 1 and 2).
Examples of the shape of the positioning metal (13) include a sphere, a cube, and a polyhedron (paragraph 0026).
In Patent Document 2, it is preferable that the particle diameter of the positioning metal (13) is substantially the same as the thickness of the bonding metal (12), and that each positioning metal (13) is completely embedded in the bonding metal (12). (Paragraph 0027).
In Patent Document 2, a semiconductor element (22) is arranged on a metal circuit (23) of a circuit board (21) through a metal bonding material (11) including a bonding metal (12) and a positioning metal (13). Thereafter, high frequency current is passed through the high frequency heating coil (36) to generate high frequency magnetic flux, and thereby induction heating is performed to melt the bonding metal (12), and the metal circuit (23) and the semiconductor element (22) ) Is described (paragraphs 0037 and 0040).
Patent Document 2 also describes a method of performing the induction heating in a state where the weight (41) is placed on the semiconductor element (22) (paragraph 0054).
Patent Document 2 describes that the semiconductor element 22 is prevented from being inclined by the positioning metal 13 (paragraph 0045).

特許文献３には、半導体装置（８）と配線基板（１）との間隔を規制する球状粒子を含む導電性樹脂ペースト（６）を用い、半導体装置（８）のパッド電極（９）と、このパッド電極（９）に対応する配線基板（１）の配線導体（２）上に導電性樹脂ペースト（６）によるバンプ電極（７）を印刷した配線基材（１）とを対向せしめ、パッド電極（９）とバンプ電極（７）とを当接させた後、導電性樹脂ペーストを硬化させて接続する半導体装置の実装方法が開示されている（請求項１、図４、図５）。   In Patent Document 3, a conductive resin paste (6) containing spherical particles that regulate the distance between the semiconductor device (8) and the wiring substrate (1) is used, and the pad electrode (9) of the semiconductor device (8), The wiring substrate (1) on which the bump electrode (7) made of the conductive resin paste (6) is printed on the wiring conductor (2) of the wiring substrate (1) corresponding to the pad electrode (9) is opposed to the pad. A method of mounting a semiconductor device is disclosed in which a conductive resin paste is cured and connected after contacting an electrode (9) and a bump electrode (7) (claims 1, 4 and 5).

特許文献３に記載の実装方法では、半導体装置（８）と配線基板（１）との間隔を規制する球状粒子を含む導電性樹脂ペースト（６）を、配線基材（１）上に部分的に塗布して、球状粒子の粒子径よりも厚いバンプ電極（７）を形成している（図２、図４）。半導体装置（８）と配線基板（１）との接合時に導電性樹脂ペースト（６）が広がり、半導体装置（８）と配線基材（１）との間隔が球状粒子の径に等しくなる（図５）。
特許文献３には、半導体装置（８）と配線基板（１）との間隔が球状粒子の直径で規制できることが記載されている（段落００１４）。 In the mounting method described in Patent Document 3, a conductive resin paste (6) containing spherical particles that regulate the distance between the semiconductor device (8) and the wiring substrate (1) is partially applied on the wiring substrate (1). A bump electrode (7) thicker than the particle diameter of the spherical particles is formed (FIGS. 2 and 4). When the semiconductor device (8) and the wiring board (1) are joined, the conductive resin paste (6) spreads, and the distance between the semiconductor device (8) and the wiring substrate (1) becomes equal to the diameter of the spherical particles (FIG. 5).
Patent Document 3 describes that the distance between the semiconductor device (8) and the wiring board (1) can be regulated by the diameter of the spherical particles (paragraph 0014).

特開2006-073554号公報JP 2006-073554 A 特開2008-112955号公報JP 2008-112955 A 特開平07-094554号公報Japanese Unexamined Patent Publication No. 07-094554

特許文献１に記載の実装方法では、ランド（１３Ａ）上に金属粉（１９）を含まない溶融状態の第２の半田（２２）を形成し、その上に金属粉（１９）を含むペースト状あるいは粉状の第１の半田（２１）を載置し、その後リフロー工程を実施している（図３（Ａ）〜（Ｃ）及び図４（Ａ）〜（Ｃ））。
かかる方法では、所定の位置にのみ金属粉を埋設させることができるので、半田よりも熱膨張係数の小さい金属粉を用いて半田接合層の熱膨張係数を部分的に変えて、基板と半導体素子との熱膨張係数差による熱応力を低減することができる。
しかしながら、特許文献１に記載の方法では、２種類の半田を用意し、これらを２度に分けて塗布する必要があるので、プロセスが煩雑で、工程数が多く、実装コストも高くつく。
また、特許文献１の図３（Ｂ）及び図４（Ｂ）に示されるように、第２の半田（２２）上に第１の半田（２１）を重ねて塗布した部分は塗布しない部分より盛り上がった状態になる。そのため、その後のリフロー工程によってある程度全体的に平坦化しても、半田接合層において第１の半田（２１）を塗布した部分は塗布しない部分より高さが高くなりやすく、半田接合層の高さを均一化することが難しい。 In the mounting method described in Patent Document 1, a melted second solder (22) not including metal powder (19) is formed on a land (13A), and a paste including metal powder (19) is formed thereon. Or the powdery 1st solder (21) is mounted and the reflow process is implemented after that (FIG. 3 (A)-(C) and FIG. 4 (A)-(C)).
In such a method, since the metal powder can be embedded only in a predetermined position, the substrate and the semiconductor element can be obtained by partially changing the thermal expansion coefficient of the solder joint layer using metal powder having a smaller thermal expansion coefficient than that of the solder. It is possible to reduce the thermal stress due to the difference in the thermal expansion coefficient.
However, in the method described in Patent Document 1, two types of solder must be prepared and applied in two steps, so that the process is complicated, the number of steps is large, and the mounting cost is high.
Further, as shown in FIG. 3B and FIG. 4B of Patent Document 1, the portion where the first solder (21) is applied over the second solder (22) is more than the portion where it is not applied. It gets excited. Therefore, even if the entire surface is flattened to some extent by the subsequent reflow process, the portion where the first solder (21) is applied in the solder bonding layer tends to be higher than the portion where the first solder (21) is not applied, and the height of the solder bonding layer is increased. It is difficult to make uniform.

特許文献２に記載の実装方法では、接合金属（１２）と位置決め金属（１３）とを含む金属接合材料（１１）をあらかじめ用意し、これを金属回路（２３）上に塗布している（図１、図２）。
この方法では、特許文献２の図１に示されるように、金属接合材料（１１）内全体に多数の位置決め金属（１３）が分散され、所定の位置にのみ位置決め金属（１３）を埋設することができない。したがって、多数の位置決め金属（１３）が必要となり、コスト高になる。また、所定の位置にのみ位置決め金属（１３）を埋設して、接合層の熱膨張係数を部分的に変えて、熱応力を低減することができない。 In the mounting method described in Patent Document 2, a metal bonding material (11) including a bonding metal (12) and a positioning metal (13) is prepared in advance and applied to the metal circuit (23) (FIG. 1, FIG. 2).
In this method, as shown in FIG. 1 of Patent Document 2, a large number of positioning metals (13) are dispersed throughout the metal bonding material (11), and the positioning metals (13) are embedded only at predetermined positions. I can't. Therefore, a large number of positioning metals (13) are required, resulting in high costs. Further, it is not possible to bury the positioning metal (13) only at a predetermined position and partially change the thermal expansion coefficient of the bonding layer to reduce the thermal stress.

特許文献３に記載の実装方法では、半導体装置（８）と配線基板（１）との間隔を規制する球状粒子を含む導電性樹脂ペースト（６）をあらかじめ用意し、これを配線基材（１）の所定の位置に部分的に塗布して、球状粒子の粒子径よりも厚いバンプ電極（７）を形成している（図２、図４、図５）。その後、半導体装置（８）と配線基板（１）との接合時に導電性樹脂ペースト（６）が広がり、導電性樹脂ペースト（６）中の複数の球状粒子も合わせて周囲に広がるが、複数の球状粒子が集って良好に分散せず、所望の厚みを有する均一な接合層が形成されない場合が起こり得る。また、球状粒子の位置制御も難しい。
特許文献３に記載の実装方法においても、多数の球状粒子が必要となり、コスト高になる。また、所定の位置にのみ球状粒子を埋設して、接合層の熱膨張係数を部分的に変えて、熱応力を低減することができない。 In the mounting method described in Patent Document 3, a conductive resin paste (6) containing spherical particles that regulate the distance between the semiconductor device (8) and the wiring substrate (1) is prepared in advance, and this is used as the wiring substrate (1). The bump electrode (7) thicker than the particle diameter of the spherical particles is formed (FIGS. 2, 4, and 5). Thereafter, when the semiconductor device (8) and the wiring board (1) are joined, the conductive resin paste (6) spreads, and the plurality of spherical particles in the conductive resin paste (6) also spread to the periphery. There may be a case where the spherical particles gather and are not dispersed well, and a uniform bonding layer having a desired thickness is not formed. In addition, it is difficult to control the position of the spherical particles.
Also in the mounting method described in Patent Document 3, a large number of spherical particles are required, which increases the cost. Further, it is impossible to embed spherical particles only at predetermined positions and partially change the thermal expansion coefficient of the bonding layer to reduce thermal stress.

本発明は上記事情に鑑みてなされたものであり、簡易なプロセスでかつ低コストに、基材と電子部品とを接合する接合層内の所定の位置に、基材と電子部品との間隔を規制する複数の導電性の固体スペーサを埋設することができ、接合層の面内高さのばらつきが抑制され、応力集中が抑制され、放熱性が良好で、電子部品の動作時の熱応力が低減された電子部品の実装方法を提供することを目的とするものである。   The present invention has been made in view of the above circumstances, and in a simple process and at a low cost, the distance between the base material and the electronic component is set at a predetermined position in the bonding layer for joining the base material and the electronic component. It is possible to embed a plurality of conductive solid spacers to be regulated, suppressing variations in in-plane height of the bonding layer, suppressing stress concentration, good heat dissipation, and thermal stress during operation of electronic components It is an object of the present invention to provide a reduced electronic component mounting method.

本発明の第１の電子部品の実装方法は、
基材上に、常温にて固体で加熱により溶融する導電材を介して、電子部品を実装する電子部品の実装方法であって、
前記基材上に前記導電材と溶剤とを含むペースト状の塗布剤を塗布して、塗布剤層を形成する工程（１Ａ）と、
前記塗布剤層内に、前記基材と前記電子部品との間隔を規制する、加熱により形状変化しない複数の導電性の固体スペーサを埋設する工程（１Ｂ）と、
前記複数の固体スペーサが埋設された前記塗布剤層上に、前記電子部品を載置する工程（１Ｃ）と、
前記電子部品を前記基材に対して押圧しながら前記基材を加熱して、前記塗布剤層内の前記導電材を溶融させた後、自然降温又は冷却により前記導電材を再固化させて、前記基材に対して前記電子部品を接合する工程（１Ｄ）とを有するものである。 The first electronic component mounting method of the present invention comprises:
An electronic component mounting method for mounting an electronic component on a base material via a conductive material that is solid at room temperature and melts by heating,
Applying a paste-like coating agent containing the conductive material and a solvent on the substrate to form a coating agent layer (1A);
In the coating agent layer, a step of embedding a plurality of conductive solid spacers that regulate the distance between the base material and the electronic component and do not change shape by heating, (1B);
A step (1C) of placing the electronic component on the coating layer in which the plurality of solid spacers are embedded;
The base material is heated while pressing the electronic component against the base material, and after the conductive material in the coating agent layer is melted, the conductive material is re-solidified by natural cooling or cooling, And (1D) joining the electronic component to the base material.

本発明において、複数の導電性の固体スペーサが「加熱により形状変化しない」とは、工程（１Ｄ）の加熱によって形状変化しないことを意味する。   In the present invention, the phrase “the shape does not change due to heating” of the plurality of conductive solid spacers means that the shape does not change due to the heating in the step (1D).

本発明の第２の電子部品の実装方法は、
基材上に、導電性ペースト又は導電性接着剤を用いて電子部品を実装する電子部品の実装方法であって、
前記基材上に前記導電性ペースト又は導電性接着剤を塗布して、導電性ペースト層又は導電性接着剤層を形成する工程（２Ａ）と、
前記導電性ペースト層又は導電性接着剤層内に、前記基材と前記電子部品との間隔を規制する、前記導電性ペースト又は導電性接着剤の硬化条件において形状変化しない複数の導電性の固体スペーサを埋設する工程（２Ｂ）と、
前記複数の固体スペーサが埋設された前記導電性ペースト層又は導電性接着剤層上に、前記電子部品を載置する工程（２Ｃ）と、
前記電子部品を前記基材に対して押圧しながら前記導電性ペースト層又は導電性接着剤層を硬化させて、前記基材に対して前記電子部品を接合する工程（２Ｄ）とを有するものである。 The second electronic component mounting method of the present invention comprises:
An electronic component mounting method for mounting an electronic component on a substrate using a conductive paste or a conductive adhesive,
Applying the conductive paste or conductive adhesive on the substrate to form a conductive paste layer or conductive adhesive layer (2A);
In the conductive paste layer or conductive adhesive layer, a plurality of conductive solids that regulate the distance between the substrate and the electronic component and do not change in shape under the curing conditions of the conductive paste or conductive adhesive A step (2B) of embedding a spacer;
A step (2C) of placing the electronic component on the conductive paste layer or the conductive adhesive layer in which the plurality of solid spacers are embedded;
A step (2D) of curing the conductive paste layer or the conductive adhesive layer while pressing the electronic component against the substrate and bonding the electronic component to the substrate. is there.

本発明によれば、簡易なプロセスでかつ低コストに、基材と電子部品とを接合する接合層内の所定の位置に、基材と電子部品との間隔を規制する複数の導電性の固体スペーサを埋設することができ、接合層の面内高さのばらつきが抑制され、応力集中が抑制され、放熱性が良好で、電子部品の動作時の熱応力が低減された電子部品の実装方法を提供することができる。   According to the present invention, a plurality of conductive solids that regulate the distance between the base material and the electronic component at a predetermined position in the bonding layer for joining the base material and the electronic component at a low cost with a simple process. Spacer can be embedded, variation in in-plane height of bonding layer is suppressed, stress concentration is suppressed, heat dissipation is good, and thermal stress during operation of electronic component is reduced. Can be provided.

（Ａ）〜（Ｅ）は本発明に係る第１実施形態の電子部品の実装方法を示す工程図である。(A)-(E) is process drawing which shows the mounting method of the electronic component of 1st Embodiment which concerns on this invention. （Ａ）〜（Ｅ）は本発明に係る第２実施形態の電子部品の実装方法を示す工程図である。(A)-(E) are process drawings which show the mounting method of the electronic component of 2nd Embodiment which concerns on this invention. （Ａ）〜（Ｄ）は従来の電子部品の実装方法を示す工程図である。(A)-(D) are process drawings which show the mounting method of the conventional electronic component. （Ａ）〜（Ｃ）は従来の課題を説明する説明図である。(A)-(C) are explanatory drawings explaining the conventional subject.

「第１実施形態」
図面を参照して、本発明に係る第１実施形態の電子部品の実装方法について説明する。図１（Ａ）〜（Ｅ）は工程図であり、各図は断面図を示している。
視認しやすくするため、図面上は各構成の縮尺や位置を実際のものとは適宜異ならせてある。 “First Embodiment”
With reference to the drawings, an electronic component mounting method according to a first embodiment of the present invention will be described. 1A to 1E are process diagrams, and each drawing shows a cross-sectional view.
In order to facilitate visual recognition, the scale and position of each component are appropriately changed from those in the drawings.

本実施形態では、基板に必要に応じて電極、配線、及びビアホール等の導電構造が形成された基材１０に対して、導電材からなる接合層２０を介して半導体チップ等の電子部品３０を実装して、実装品１を得る方法について説明する。   In the present embodiment, an electronic component 30 such as a semiconductor chip is attached to a base material 10 on which a conductive structure such as an electrode, a wiring, and a via hole is formed on a substrate as necessary via a bonding layer 20 made of a conductive material. A method of mounting and obtaining the mounted product 1 will be described.

はじめに、図１（Ａ）に示す基材１０上に、図１（Ｂ）に示すように、常温にて固体で加熱により溶融する導電材と溶剤とを含むペースト状の塗布剤を各種印刷法等により塗布して、塗布剤層２１を形成する（工程（１Ａ））。
導電材としては特に制限されず、半田等の導電金属が好ましい。導電材が半田である場合、塗布剤としては市販の半田ペーストを用いることができる。 First, as shown in FIG. 1 (B), a paste-like coating agent containing a conductive material and a solvent that melts by heating at room temperature is applied to the substrate 10 shown in FIG. 1 (A) by various printing methods. Etc. to form the coating agent layer 21 (step (1A)).
The conductive material is not particularly limited, and a conductive metal such as solder is preferable. When the conductive material is solder, a commercially available solder paste can be used as the coating agent.

工程（１Ａ）において、塗布剤層２１の厚みＴは、後工程で用いる複数の導電性の固体スペーサ２３の高さＨ以上とする（Ｔ≧Ｈ）。
図面上は簡略化して、塗布剤層２１の厚みＴ＝固体スペーサ２３の高さＨとして図示してあるが、通常、後のリフロー工程（１Ｄ）において、塗布剤層２１の厚みは初期の厚みより薄くなるため、リフロー工程（１Ｄ）において塗布剤層２１が薄くなる厚みをΔＴとしたとき、Ｔ≧Ｈ＋ΔＴとすることが好ましい。 In the step (1A), the thickness T of the coating agent layer 21 is not less than the height H of the plurality of conductive solid spacers 23 used in the subsequent step (T ≧ H).
For simplicity, the thickness T of the coating agent layer 21 is shown as the height H of the solid spacer 23. Usually, in the subsequent reflow process (1D), the thickness of the coating agent layer 21 is the initial thickness. In order to make it thinner, it is preferable that T ≧ H + ΔT, where ΔT is the thickness at which the coating agent layer 21 becomes thinner in the reflow step (1D).

次に、図１（Ｃ）に示すように、塗布剤層２１内に、基材１０と電子部品３０との間隔を規制する、加熱により形状変化しない複数の導電性の固体スペーサ２３を埋設する（工程（１Ｂ））。
複数の導電性の固体スペーサ２３が「加熱により形状変化しない」とは、後の工程（１Ｄ）の加熱によって形状変化しないことを意味する。 Next, as shown in FIG. 1 (C), a plurality of conductive solid spacers 23 are embedded in the coating agent layer 21 to regulate the distance between the base material 10 and the electronic component 30 and do not change in shape due to heating. (Step (1B)).
The phrase “the shape does not change due to heating” of the plurality of conductive solid spacers 23 means that the shape does not change due to heating in the subsequent step (1D).

本実施形態において、複数の固体スペーサ２３はいずれも、基材１０と電子部品３０との所望の間隔に合わせた高さＨを有するものである。
固体スペーサ２３の形状は特に制限されず、基材１０と電子部品３０との所望の間隔に合わせた高さＨを有するものであればよい。
固体スペーサ２３の形状は、球状、円柱状、角柱状、円錐状、角錐状など任意であり、不定形状でもよい。
本実施形態では、基材１０と電子部品３０との所望の間隔に合わせた高さＨを有するように固体スペーサ２３を埋設する必要がある。固体スペーサ２３がいずれの向きで埋設されても、所望の高さＨが得られることから、固体スペーサ２３の形状としては、球状が特に好ましい。固体スペーサ２３が球状である場合について図示してある。
高さＨは特に制限されず、例えば５０〜２００μｍが好ましい。 In the present embodiment, each of the plurality of solid spacers 23 has a height H that matches a desired distance between the base material 10 and the electronic component 30.
The shape of the solid spacer 23 is not particularly limited as long as it has a height H that matches the desired distance between the substrate 10 and the electronic component 30.
The shape of the solid spacer 23 is arbitrary such as a spherical shape, a cylindrical shape, a prism shape, a conical shape, and a pyramid shape, and may be an indefinite shape.
In the present embodiment, it is necessary to embed the solid spacer 23 so as to have a height H that matches the desired distance between the substrate 10 and the electronic component 30. Since the desired height H can be obtained regardless of the orientation of the solid spacer 23, the shape of the solid spacer 23 is particularly preferably spherical. The case where the solid spacer 23 is spherical is illustrated.
The height H is not particularly limited, and is preferably 50 to 200 μm, for example.

工程（１Ｂ）においては例えば、１個又は複数個の固体スペーサ２３を把持し、かつそれを所定の位置に移動させて離すことが可能な把持具を用いて、固体スペーサ２３を１個ずつ又は複数個ずつ埋設することができる。複数の固体スペーサ２３の埋設作業は、実装作業者が手動で実施してもよいし、上記把持具を備え、これを機械的に自動操作する装置を用いて実施してもよい。
あらかじめ塗布した塗布剤層２１内に複数の固体スペーサ２３を埋設する上記方法では、塗布剤層２１内の所定の位置にのみ複数の固体スペーサ２３を埋設することができる。 In the step (1B), for example, one or a plurality of solid spacers 23 are grasped, and the solid spacers 23 are moved one by one using a gripper that can be moved to a predetermined position and separated. A plurality can be buried. The embedding operation of the plurality of solid spacers 23 may be performed manually by a mounting operator, or may be performed using a device that includes the gripping tool and mechanically automatically operates the mounting tool.
In the above-described method of embedding a plurality of solid spacers 23 in the coating agent layer 21 applied in advance, the plurality of solid spacers 23 can be embedded only at predetermined positions in the coating agent layer 21.

本実施形態では、塗布剤層２１内の所定の位置にのみ複数の固体スペーサ２３を埋設することができるので、必要最小限の個数の固体スペーサ２３を用いて、基材１０と電子部品３０との間隔を規制できる。
例えば、電子部品３０が平面視略矩形状である場合、塗布剤層２１内の電子部品３０の４つの角部に対応する位置にそれぞれ少なくとも１個の固体スペーサ２３を埋設すればよい。
電子部品３０の４つの角部に対応する位置と合わせて、塗布剤層２１の周縁部（平面視略矩形状の電子部品３０の各辺に沿った端部）全体に、複数の固体スペーサ２３を埋設してもよい。かかる場合でも、塗布剤層２１内全体に複数の固体スペーサ２３を埋設するよりも、必要な固体スペーサ２３の個数が少なくて済む。
本明細書において、「略矩形状」には、矩形状及びその角が面取りされた形状が含まれる。 In the present embodiment, since a plurality of solid spacers 23 can be embedded only in a predetermined position in the coating agent layer 21, the substrate 10, the electronic component 30, Can be controlled.
For example, when the electronic component 30 has a substantially rectangular shape in plan view, at least one solid spacer 23 may be embedded in each of the positions corresponding to the four corners of the electronic component 30 in the coating agent layer 21.
In combination with the positions corresponding to the four corners of the electronic component 30, a plurality of solid spacers 23 are formed on the entire periphery of the coating agent layer 21 (ends along each side of the electronic component 30 having a substantially rectangular shape in plan view). May be buried. Even in such a case, the number of necessary solid spacers 23 is smaller than embedding a plurality of solid spacers 23 in the entire coating agent layer 21.
In the present specification, the “substantially rectangular shape” includes a rectangular shape and a shape whose corners are chamfered.

本実施形態では、塗布剤層２１内の所定の位置に複数の固体スペーサ２３を埋設することができるので、接合層２０の導電材と異なる熱膨張係数の材質の固体スペーサ２３を用いることで、接合層２０の熱膨張係数を部分的に変えることができる。   In the present embodiment, since a plurality of solid spacers 23 can be embedded at predetermined positions in the coating agent layer 21, by using the solid spacers 23 having a material having a different thermal expansion coefficient from the conductive material of the bonding layer 20, The thermal expansion coefficient of the bonding layer 20 can be partially changed.

接合層２０の導電材よりも熱膨張係数の小さい材質の複数の固体スペーサ２３を塗布剤層２１内に埋設することで、基材１０と電子部品３０との間の熱膨張係数差によって、電子部品３０の動作時に生じる熱応力を低減し、基材１０の実装品の反りやクラック等を抑制することができる。   By embedding a plurality of solid spacers 23 made of a material having a smaller thermal expansion coefficient than the conductive material of the bonding layer 20 in the coating agent layer 21, the difference in thermal expansion coefficient between the base material 10 and the electronic component 30 causes the electronic Thermal stress generated during operation of the component 30 can be reduced, and warpage, cracks, and the like of the mounted product of the base material 10 can be suppressed.

例えば、Ａｌ基板を用いた基材１０に、Ｓｉ基板を用いた半導体チップからなる電子部品３０を実装する場合、Ａｌの熱膨張係数は３２．１×１０−６／℃であり、Ｓｉの熱膨張係数は２．６×１０−６／℃である。かかる関係では、電子部品３０の動作時の発熱で基材１０の方がより大きく熱膨張し、降温時に基材１０の方がより大きく収縮するため、実装品１に熱応力がかかる。 For example, when the electronic component 30 made of a semiconductor chip using a Si substrate is mounted on the base material 10 using an Al substrate, the thermal expansion coefficient of Al is 32.1 × 10 −6 / ° C., and the heat of Si The expansion coefficient is 2.6 × 10 −6 / ° C. In this relationship, the base material 10 is more thermally expanded due to heat generated during the operation of the electronic component 30, and the base material 10 is more contracted when the temperature is lowered, so that the mounted product 1 is subjected to thermal stress.

導電材として半田を用いる場合、その熱膨張係数は、２３.０×１０−６／℃程度である。それより熱膨張係数の小さい材質としては、銅（熱膨張係数：１６．５×１０−６／℃）、及びニッケル（熱膨張係数１３．４×１０−６／℃）等が挙げられる。
したがって、導電材として半田を用いる場合、固体スペーサ２３として銅及び／又はニッケルを含む金属スペーサを用いることが好ましい。 When solder is used as the conductive material, the thermal expansion coefficient is about 23.0 × 10 −6 / ° C. Examples of the material having a smaller thermal expansion coefficient include copper (thermal expansion coefficient: 16.5 × 10 −6 / ° C.), nickel (thermal expansion coefficient 13.4 × 10 −6 / ° C.), and the like.
Therefore, when using solder as the conductive material, it is preferable to use a metal spacer containing copper and / or nickel as the solid spacer 23.

導電材よりも熱膨張係数の小さい材質の複数の固体スペーサ２３を、塗布剤層２１内の例えば４つの角部、あるいは周縁部全体に埋設することで、基材１０と電子部品３０との間の熱膨張係数差によって電子部品３０の動作時に生じる熱応力を低減し、基材１０の実装品の反りやクラック等を抑制することができる。   By embedding a plurality of solid spacers 23 having a smaller thermal expansion coefficient than that of the conductive material in, for example, four corners or the entire periphery of the coating material layer 21, a space between the base material 10 and the electronic component 30 is obtained. The thermal stress generated during the operation of the electronic component 30 due to the difference in thermal expansion coefficient can be reduced, and warpage, cracks, and the like of the mounted product of the substrate 10 can be suppressed.

次に、図１（Ｄ）及び図１（Ｅ）に示すように、複数の固体スペーサ２３が埋設された塗布剤層２１上に電子部品３０を載置し（工程（１Ｃ））、電子部品３０を基材１０に対して押圧しながら基材１０を加熱して、塗布剤層２１内の溶剤を除去しつつ導電材を溶融させた後、自然降温又は冷却により導電材を再固化させる（工程（１Ｄ））。
工程（１Ｄ）後に、塗布剤層２１は導電材２２中に複数の固体スペーサ２３が埋設された接合層２０となる。 Next, as shown in FIGS. 1D and 1E, an electronic component 30 is placed on the coating agent layer 21 in which a plurality of solid spacers 23 are embedded (step (1C)). The substrate 10 is heated while pressing the substrate 30 against the substrate 10 to melt the conductive material while removing the solvent in the coating agent layer 21, and then the conductive material is re-solidified by natural cooling or cooling ( Step (1D)).
After the step (1D), the coating agent layer 21 becomes the bonding layer 20 in which a plurality of solid spacers 23 are embedded in the conductive material 22.

工程（１Ｄ）は、リフロー工程である。電子部品３０を基材１０に対して押圧しながらリフロー工程を実施することにより、電子部品３０が基材１０に対して、基材１０と電子部品３０との所望の間隔Ｈよりも浮いて実装される恐れがなく、基材１０と電子部品３０との間隔を、全体的に固体スペーサ２３の高さＨに確実に規制することができる。
図示するように、工程（１Ｄ）においては電子部品３０上に板状の錘４０を載置し、その上から電子部品３０を加圧することが好ましい。板状の錘４０を用いることで、電子部品３０全体を均一に加圧することができる。
加熱温度は特に制限されず、導電材が溶融する温度であればよい。 Step (1D) is a reflow step. By carrying out the reflow process while pressing the electronic component 30 against the base material 10, the electronic component 30 is mounted on the base material 10 in such a way that it floats more than the desired distance H between the base material 10 and the electronic component 30. The distance between the base material 10 and the electronic component 30 can be reliably regulated to the height H of the solid spacer 23 as a whole.
As shown in the drawing, in the step (1D), it is preferable to place a plate-like weight 40 on the electronic component 30 and pressurize the electronic component 30 from above. By using the plate-like weight 40, the entire electronic component 30 can be uniformly pressurized.
The heating temperature is not particularly limited as long as the conductive material melts.

以上のようにして、基材１０に対して接合層２０を介して電子部品３０が接合された実装品１が得られる。   As described above, the mounted product 1 in which the electronic component 30 is bonded to the base material 10 via the bonding layer 20 is obtained.

本実施形態の電子部品の実装方法では、接合層２０内に基材１０と電子部品３０との間隔を規制する複数の固体スペーサ２３を埋設させているので、接合層２０の高さＨの面内ばらつきを抑制することができる。
そのため、接合層２０の高さＨの面内ばらつきによって生じる応力集中部分と基材１０側からの放熱性の良くない部分の発生が抑制され、信頼性の高い実装品１を安定的に提供することができる。 In the electronic component mounting method of the present embodiment, a plurality of solid spacers 23 that regulate the distance between the base material 10 and the electronic component 30 are embedded in the bonding layer 20. The internal variation can be suppressed.
Therefore, the generation of the stress concentration portion caused by the in-plane variation of the height H of the bonding layer 20 and the portion with poor heat dissipation from the substrate 10 side is suppressed, and the highly reliable mounted product 1 is stably provided. be able to.

本実施形態の電子部品の実装方法では、基材１０上に導電材と溶剤とを含むペースト状の塗布剤を塗布して塗布剤層２１を形成してから、塗布剤層２１内に複数の導電性の固体スペーサ２３を埋設し、その後、電子部品３０の実装を行っている。
かかる方法では、簡易なプロセスで、基材１０と電子部品３０とを接合する接合層２０内の所定の位置に、基材１０と電子部品３０との間隔を規制する複数の固体スペーサ２３を埋設することができる。 In the electronic component mounting method of the present embodiment, a paste-like coating agent containing a conductive material and a solvent is applied on the base material 10 to form the coating agent layer 21, and then a plurality of coating agents are formed in the coating agent layer 21. The conductive solid spacer 23 is embedded, and then the electronic component 30 is mounted.
In such a method, a plurality of solid spacers 23 for embedding the distance between the base material 10 and the electronic component 30 are embedded in a predetermined position in the bonding layer 20 for bonding the base material 10 and the electronic component 30 by a simple process. can do.

本実施形態の実装方法では、接合層２０内の所定の位置に複数の固体スペーサ２３を埋設することができるので、必要最小限の個数の固体スペーサ２３で基材１０と電子部品３０との間隔を良好に規制することができ、低コストである。
また、導電材と異なる熱膨張係数の材質の固体スペーサ２３を用いることで、接合層２０の熱膨張係数を部分的に変えることができ、基材１０と電子部品３０の熱膨張係数差による熱応力を低減することができる。 In the mounting method of the present embodiment, a plurality of solid spacers 23 can be embedded at a predetermined position in the bonding layer 20, so that the distance between the base material 10 and the electronic component 30 is the minimum number of solid spacers 23. Can be well controlled and low cost.
Further, by using the solid spacer 23 made of a material having a different thermal expansion coefficient from that of the conductive material, the thermal expansion coefficient of the bonding layer 20 can be partially changed, and the heat caused by the difference in thermal expansion coefficient between the base material 10 and the electronic component 30 can be changed. Stress can be reduced.

なお、塗布剤内にあらかじめ固体スペーサを混入させてから塗布を行う特許文献２〜３に記載の実装方法では、塗布剤層内の所定の位置に複数の固体スペーサを埋設することができない。
また、固体スペーサを混入させない塗布剤と、固体スペーサを混入させた塗布剤との２種類の塗布剤を用いる特許文献１に記載の方法では、プロセスが煩雑で、高コストである。 Note that in the mounting methods described in Patent Documents 2 to 3 in which the solid spacers are mixed in advance in the coating agent and then applied, a plurality of solid spacers cannot be embedded at predetermined positions in the coating agent layer.
Moreover, in the method of patent document 1 using the coating agent which does not mix a solid spacer, and the coating agent which mixed the solid spacer, the process is complicated and expensive.

以上説明したように、本実施形態によれば、簡易なプロセスでかつ低コストに、基材１０と電子部品３０とを接合する接合層２０内の所定の位置に、基材１０と電子部品３０との間隔を規制する複数の導電性の固体スペーサ２３を埋設することができ、接合層２０の面内高さＨのばらつきが抑制され、応力集中が抑制され、放熱性が良好で、電子部品３０の動作時の熱応力が低減された電子部品の実装方法を提供することができる。   As described above, according to the present embodiment, the base material 10 and the electronic component 30 are arranged at predetermined positions in the bonding layer 20 for bonding the base material 10 and the electronic component 30 with a simple process and at low cost. A plurality of conductive solid spacers 23 that regulate the distance between the bonding layer 20 and the in-plane height H of the bonding layer 20 are suppressed, stress concentration is suppressed, heat dissipation is good, and electronic components It is possible to provide a method for mounting an electronic component in which the thermal stress during operation 30 is reduced.

本実施形態では、複数の固体スペーサ２３はいずれも、基材１０と電子部品３０との所望の間隔に合わせた高さＨを有する場合について説明したが、本実施形態では、塗布剤層２１内の所定の位置に複数の固体スペーサ２３を埋設することができるので、複数の固体スペーサ２３の高さＨを固体スペーサ２３ごとに変えることもできる。
したがって、基材１０に対して敢えて電子部品３０を傾けて実装するなども可能である。 In the present embodiment, a case has been described in which each of the plurality of solid spacers 23 has a height H that matches a desired distance between the base material 10 and the electronic component 30, but in the present embodiment, the inside of the coating agent layer 21. Since the plurality of solid spacers 23 can be embedded at predetermined positions, the height H of the plurality of solid spacers 23 can be changed for each solid spacer 23.
Therefore, the electronic component 30 can be mounted with an inclination relative to the base material 10.

「第２実施形態」
図２（Ａ）〜（Ｅ）を参照して、本発明に係る第２実施形態の電子部品の実装方法について説明する。 “Second Embodiment”
With reference to FIG. 2 (A)-(E), the mounting method of the electronic component of 2nd Embodiment which concerns on this invention is demonstrated.

はじめに、図２（Ａ）に示す基材１０上に導電性ペースト又は導電性接着剤を塗布して、導電性ペースト層又は導電性接着剤層５１を形成する（工程（２Ａ））。
次に、導電性ペースト層又は導電性接着剤層５１内の所定の位置に、基材１０と電子部品３０との間隔を規制する、導電性ペースト又は導電性接着剤の硬化条件において形状変化しない複数の導電性の固体スペーサ５３を埋設する（工程（２Ｂ））。 First, a conductive paste or a conductive adhesive is applied to the base material 10 shown in FIG. 2A to form a conductive paste layer or a conductive adhesive layer 51 (step (2A)).
Next, in a predetermined position in the conductive paste layer or the conductive adhesive layer 51, the shape does not change under the curing conditions of the conductive paste or the conductive adhesive that regulates the distance between the base material 10 and the electronic component 30. A plurality of conductive solid spacers 53 are embedded (step (2B)).

導電性ペースト層又は導電性接着剤層５１の厚みＴは、第１実施形態の塗布剤層２１と同様である。
固体スペーサ２３の形状、高さＨの好ましい範囲、及び好ましい材質は、第１実施形態と同様である。 The thickness T of the conductive paste layer or the conductive adhesive layer 51 is the same as that of the coating agent layer 21 of the first embodiment.
The shape of the solid spacer 23, the preferred range of the height H, and the preferred material are the same as in the first embodiment.

導電性ペースト又は導電性接着剤を用いる場合にも、あらかじめ導電性ペースト層又は導電性接着剤層５１を形成した後に複数の導電性の固体スペーサ５３を埋設することにより、第１実施形態と同様、所定の位置にのみ複数の導電性の固体スペーサ５３を埋設することができる。   Even in the case of using a conductive paste or a conductive adhesive, a plurality of conductive solid spacers 53 are embedded after forming a conductive paste layer or a conductive adhesive layer 51 in advance, as in the first embodiment. A plurality of conductive solid spacers 53 can be embedded only at predetermined positions.

次に、複数の固体スペーサ５３が埋設された導電性ペースト層又は導電性接着剤層５１上に電子部品３０を載置する（工程（２Ｃ））。
その後、好ましくは板状の錘４０を用いて、電子部品３０を基材１０に対して押圧しながら導電性ペースト層又は導電性接着剤層５１を硬化させる（工程（２Ｄ））。
硬化方法は、用いる導電性ペースト又は導電性接着剤の硬化方法を採用する。例えば、熱硬化性であれば加熱により導電性ペースト層又は導電性接着剤層５１を硬化させることができる。
以上のようにして、基材１０に対して、複数の固体スペーサ５３が埋設された導電材５２からなる接合層５０を介して電子部品３０が接合された実装品２が得られる。 Next, the electronic component 30 is placed on the conductive paste layer or the conductive adhesive layer 51 in which the plurality of solid spacers 53 are embedded (step (2C)).
Thereafter, the conductive paste layer or the conductive adhesive layer 51 is cured while pressing the electronic component 30 against the substrate 10 preferably using the plate-like weight 40 (step (2D)).
The curing method employs a curing method for the conductive paste or conductive adhesive used. For example, if it is thermosetting, the conductive paste layer or the conductive adhesive layer 51 can be cured by heating.
As described above, the mounted product 2 in which the electronic component 30 is bonded to the base material 10 through the bonding layer 50 made of the conductive material 52 in which a plurality of solid spacers 53 are embedded is obtained.

以上のように、本発明は、半田等の導電材を含むペースト状の塗布剤の代わりに、導電性ペースト又は導電性接着剤を用いて実装を行う場合にも適用することができる。
本実施形態によっても、第１実施形態と同様、簡易なプロセスでかつ低コストに、基材１０と電子部品３０とを接合する接合層５０内の所定の位置に、基材１０と電子部品３０との間隔を規制する複数の導電性の固体スペーサ２３を埋設することができ、接合層２０の面内高さＨのばらつきが抑制され、応力集中が抑制され、放熱性が良好で、電子部品３０の動作時の熱応力が低減された電子部品の実装方法を提供することができる。 As described above, the present invention can also be applied to a case where mounting is performed using a conductive paste or a conductive adhesive instead of a paste-like coating agent containing a conductive material such as solder.
Also in the present embodiment, as in the first embodiment, the base material 10 and the electronic component 30 are placed at predetermined positions in the bonding layer 50 for bonding the base material 10 and the electronic component 30 with a simple process and at low cost. A plurality of conductive solid spacers 23 that regulate the distance between the bonding layer 20 and the in-plane height H of the bonding layer 20 are suppressed, stress concentration is suppressed, heat dissipation is good, and electronic components It is possible to provide a method for mounting an electronic component in which the thermal stress during operation 30 is reduced.

（設計変更）
本発明は上記実施形態に限らず、本発明の趣旨を逸脱しない範囲内において適宜設計変更が可能である。 (Design changes)
The present invention is not limited to the above-described embodiment, and design changes can be made as appropriate without departing from the spirit of the present invention.

本発明の電子部品の実装方法は、電気・電子部品産業及び自動車産業等の電装品、及びこれらに用いられる部品の実装に適用することができる。   The electronic component mounting method of the present invention can be applied to mounting of electrical components in the electrical / electronic component industry and the automobile industry, and components used in these.

１、２ 実装品
１０ 基材
２０ 接合層
２１ 塗布剤層
２２ 導電材
２３ 固体スペーサ
３０ 電子部品
４０ 錘
２ 実装品
５０ 接合層
５１ 導電性ペースト層又は導電性接着剤層
５２ 導電材
５３ 固体スペーサ DESCRIPTION OF SYMBOLS 1, 2 Mounted product 10 Base material 20 Bonding layer 21 Coating agent layer 22 Conductive material 23 Solid spacer 30 Electronic component 40 Weight 2 Mounted product 50 Bonding layer 51 Conductive paste layer or conductive adhesive layer 52 Conductive material 53 Solid spacer

Claims (6)

基材上に、常温にて固体で加熱により溶融する導電材を介して、電子部品を実装する電子部品の実装方法であって、
前記基材上に前記導電材と溶剤とを含むペースト状の塗布剤を塗布して、塗布剤層を形成する工程（１Ａ）と、
前記塗布剤層内に、前記基材と前記電子部品との間隔を規制する、加熱により形状変化しない複数の導電性の固体スペーサを埋設する工程（１Ｂ）と、
前記複数の固体スペーサが埋設された前記塗布剤層上に、前記電子部品を載置する工程（１Ｃ）と、
前記電子部品を前記基材に対して押圧しながら前記基材を加熱して、前記塗布剤層内の前記導電材を溶融させた後、自然降温又は冷却により前記導電材を再固化させて、前記基材に対して前記電子部品を接合する工程（１Ｄ）とを有する電子部品の実装方法。 An electronic component mounting method for mounting an electronic component on a base material via a conductive material that is solid at room temperature and melts by heating,
Applying a paste-like coating agent containing the conductive material and a solvent on the substrate to form a coating agent layer (1A);
In the coating agent layer, a step of embedding a plurality of conductive solid spacers that regulate the distance between the base material and the electronic component and do not change shape by heating, (1B);
A step (1C) of placing the electronic component on the coating layer in which the plurality of solid spacers are embedded;
The base material is heated while pressing the electronic component against the base material, and after the conductive material in the coating agent layer is melted, the conductive material is re-solidified by natural cooling or cooling, The electronic component mounting method comprising a step (1D) of bonding the electronic component to the base material. 前記電子部品が平面視略矩形状であり、工程（１Ｂ）において、前記塗布剤層内の少なくとも前記電子部品の４つの角部に対応する位置に前記複数の固体スペーサを埋設する請求項１に記載の電子部品の実装方法。   The electronic component has a substantially rectangular shape in plan view, and in the step (1B), the plurality of solid spacers are embedded in positions corresponding to at least four corners of the electronic component in the coating agent layer. The electronic component mounting method described. 前記固体スペーサとして、前記導電材より熱膨張係数が小さいものを用いる請求項１又は２に記載の電子部品の実装方法。   The electronic component mounting method according to claim 1, wherein the solid spacer has a smaller thermal expansion coefficient than the conductive material. 前記導電材が半田であり、前記固体スペーサとして銅及び／又はニッケルを含む金属スペーサを用いる請求項３に記載の電子部品の実装方法。   The electronic component mounting method according to claim 3, wherein the conductive material is solder, and a metal spacer containing copper and / or nickel is used as the solid spacer. 基材上に、導電性ペースト又は導電性接着剤を用いて電子部品を実装する電子部品の実装方法であって、
前記基材上に前記導電性ペースト又は導電性接着剤を塗布して、導電性ペースト層又は導電性接着剤層を形成する工程（２Ａ）と、
前記導電性ペースト層又は導電性接着剤層内に、前記基材と前記電子部品との間隔を規制する、前記導電性ペースト又は導電性接着剤の硬化条件において形状変化しない複数の導電性の固体スペーサを埋設する工程（２Ｂ）と、
前記複数の固体スペーサが埋設された前記導電性ペースト層又は導電性接着剤層上に、前記電子部品を載置する工程（２Ｃ）と、
前記電子部品を前記基材に対して押圧しながら前記導電性ペースト層又は導電性接着剤層を硬化させて、前記基材に対して前記電子部品を接合する工程（２Ｄ）とを有する電子部品の実装方法。 An electronic component mounting method for mounting an electronic component on a substrate using a conductive paste or a conductive adhesive,
Applying the conductive paste or conductive adhesive on the substrate to form a conductive paste layer or conductive adhesive layer (2A);
In the conductive paste layer or conductive adhesive layer, a plurality of conductive solids that regulate the distance between the substrate and the electronic component and do not change in shape under the curing conditions of the conductive paste or conductive adhesive A step (2B) of embedding a spacer;
A step (2C) of placing the electronic component on the conductive paste layer or the conductive adhesive layer in which the plurality of solid spacers are embedded;
An electronic component having a step (2D) of curing the conductive paste layer or the conductive adhesive layer while pressing the electronic component against the substrate and bonding the electronic component to the substrate. How to implement 前記電子部品が平面視略矩形状であり、工程（２Ｂ）において、前記導電性ペースト層又は導電性接着剤層内の少なくとも前記電子部品の４つの角部に対応する位置に前記複数の固体スペーサを埋設する請求項５に記載の電子部品の実装方法。   The electronic component has a substantially rectangular shape in plan view, and in the step (2B), the plurality of solid spacers at positions corresponding to at least four corners of the electronic component in the conductive paste layer or the conductive adhesive layer The electronic component mounting method according to claim 5, wherein the electronic component is embedded.
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