JP6406996B2 - Semiconductor device - Google Patents

Description

  The present invention relates to die bonding of semiconductor elements including power modules.

  Power modules are spreading in various products from industrial equipment to home appliances and information terminals, and miniaturization and high efficiency are particularly required for modules installed in home appliances. In addition, it is also required to have a package form that can be applied to SiC semiconductors that are likely to become mainstream in the future because of high operating temperature and excellent efficiency.

  Power modules are spreading not only in transportation and industrial equipment but also in home appliances such as air conditioners, and not only long-term reliability but also miniaturization and high efficiency are being demanded. As the heat generation density increases with downsizing, the influence of the quality of the die bond part (void or unjoined part) on the heat dissipation becomes significant. Further, as the chip becomes thinner for higher efficiency, it becomes difficult to diffuse the heat in the semiconductor element itself, and the influence on the heat dissipation and the like due to the quality of the die bond portion is increasing. Conventionally, in order to suppress the generation of voids and unjoined parts, expensive processes such as vacuum soldering have been used and processes that require a large number of man-hours such as scrubbing have been used, but fundamental voids have not been suppressed. It was. Further, in a high-performance SiC semiconductor, the operating temperature is higher than in the past, so it is considered that ensuring heat dissipation is more important than ever.

  In recent years, die bonding techniques for reducing voids in soldered portions by soldering while reducing pressure are becoming common. However, with this method, there is a problem in that the wire is difficult to be bonded because the solder repels at the timing when the void is removed from the outer periphery of the power semiconductor element at the time of decompression, and the minute solder scatters and adheres to the adjacent power semiconductor element. is there.

  Further, the rigidity of the semiconductor element is reduced due to the thinning of the semiconductor element, and if a large void is present directly under the wire bond electrode, the chip may be broken by the impact of the wire bond. As a structure for suppressing voids, Patent Document 1 proposes a soldering method in which the bottom surface of a heat sink is processed into a pyramid shape to promote void removal during soldering.

JP 07-297329 A

  In Patent Document 1, a void between the heat sink and the circuit pattern can be suppressed, but a void between the chip of the power semiconductor device and the heat sink cannot be suppressed. If the void between the chip and the heat sink is suppressed with the same configuration as that between the heat sink and the circuit pattern, the back surface (die bond surface) of the chip is machined on a brittle Si chip having a thickness of 100 μm. However, this machining is difficult, and even if it can be done, there is a problem that the processing strain affects the reliability.

  The present invention has been made to solve the above-described problems, and an object thereof is to obtain a semiconductor device capable of suppressing voids in a die bond portion by a simple process.

The present invention relates to a semiconductor device in which an element fixing surface, which is one surface of a semiconductor element, is fixed to a substrate fixing surface, which is one surface of a substrate, by solder so that the element fixing surface is concave or convex with respect to the substrate fixing surface. The element is curved, and the distance between the element fixing surface and the substrate fixing surface is gradually increased in one direction.

  According to the present invention, it is possible to provide a semiconductor device in which voids in the die bond portion are suppressed by a simple process.

FIG. 2 is a side sectional view and a top view showing the configuration of the semiconductor device according to the first embodiment of the present invention. It is a conceptual diagram which shows the die-bonding process of the semiconductor device by Embodiment 1 of this invention. It is a schematic diagram explaining the effect of the semiconductor device by Embodiment 1 of this invention. It is side surface sectional drawing which shows another structure of the semiconductor device by Embodiment 1 of this invention. It is a top view which shows another structure of the semiconductor device by Embodiment 1 of this invention. It is a top view which shows another structure of the semiconductor device by Embodiment 1 of this invention. It is side surface sectional drawing and the top view which show the structure of the semiconductor device by Embodiment 2 of this invention. It is a top view which shows another structure of the semiconductor device by Embodiment 2 of this invention. It is side surface sectional drawing which shows the structure of the semiconductor device by Embodiment 3 of this invention. It is a conceptual diagram which shows the die-bonding process of the semiconductor device by Embodiment 3 of this invention. It is side surface sectional drawing which shows the detailed structure of the semiconductor device by Embodiment 3 of this invention. It is side surface sectional drawing which shows the detailed structure of the semiconductor device by Embodiment 4 of this invention.

Embodiment 1 FIG.
1A and 1B are diagrams showing a configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 1A is a side sectional view and FIG. 1B is a top view. FIG. 2 is a conceptual diagram of the die bonding process of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 2A, an epoxy resin projection 4 (diameter 0.5 mm, height 0.2 mm) is heated on a 10 mm × 10 mm × 1 mm Cu heat spreader 2 and then heated and cured. Form in two places. Next, as shown in FIG. 1B, for example, a solder ribbon 31 (Sn—Ag—Cu eutectic: melting point 217 ° C.) having a size of 5 mm × 5 mm × thickness 0.2 mm is disposed, and 7 mm × 7 mm × thickness 0. 2 mm power semiconductor device 1 (IGBT: Insulated Gate Bipolar Transistor, back metallization layer: Al
/ Ni / Au, surface metallized layer: AlSi / Ni / Au). Finally, as shown in FIG. 2C, the solder die bond portion 32 is formed by heating in a reflow furnace and melting the solder. The solder die bond portion 32 has a thickness of about 0.2 mm on the side where the projection 4 is present, and has a thickness of about 0.05 mm on the side where the projection is not present. That is, the element fixing surface 101 of the semiconductor element 1 is inclined with respect to the substrate fixing surface 201 of the heat spreader 2 as a substrate so that the side length of the semiconductor element is 7 mm and the thickness of the die bond portion 32 is different by 150 μm. The distance is fixed so as to gradually increase in one direction. Note that the above dimensions are typical examples, and it goes without saying that the present invention can be applied to semiconductor devices having various dimensions depending on the semiconductor elements used and the like. In FIG. 1 (a), the dimensional ratio between the vertical direction, that is, the thickness direction and the horizontal direction is not shown as an actual dimensional ratio. It shows. Similarly in the subsequent drawings, the dimension in the thickness direction is shown enlarged compared to the horizontal direction.

  Regarding the void discharge mechanism, the principle of movement of the void in the solder will be described. According to the document "Experiment on bubble behavior in a horizontal narrow rectangular channel" (The Japan Society of Mechanical Engineers (B), Vol.61, No.581, (1995), pp201-207), it is sandwiched between flat plates. The gas in the liquid may move toward the larger cross-sectional area of the liquid due to the action of surface tension. In the semiconductor device according to the first embodiment of the present invention, as shown in the schematic diagram using the side cross-sectional view of FIG. 3, the solder die bond portion 32 is directed from the side having no projection toward the side having the projection, that is, The thickness gradually increases in one direction. When a vaporized component comes out of the metallization layer of the solder or the power semiconductor element and a void is generated and a plurality of voids are connected and enlarged, the void 51 is flattened between the power semiconductor element 1 and the heat spreader 2. Eventually, the void 51 moves toward the larger solder thickness so that it can take a shape close to a sphere with a small surface area, and becomes a void 52 that is close to a sphere. The voids can be reduced by discharging the voids to the outside as they are. At this time, by using the reduced pressure reflow furnace, not only the void is reduced at the time of return pressure, but also the above movement is facilitated by the increase of the void at the time of pressure reduction. Note that how much the thickness of the die bond portion 32 should be increased depends on parameters such as viscosity at the time of melting the solder.

  FIG. 4 is a side sectional view showing another configuration of the semiconductor device according to the first embodiment of the present invention. The semiconductor element 1 is fixed to a ceramic substrate 20 having conductive films formed on both surfaces by solder die bonding portions 32. Similar to the semiconductor device shown in FIG. 1, the element fixing surface 101 of the semiconductor element 1 and the substrate fixing surface 201 of the ceramic substrate 20 are relatively inclined, and the distance between both the fixing surfaces gradually increases in one direction. Yes. The ceramic substrate 20 is fixed to the conductor base substrate 21 with solder 33. The other surface 202 of the ceramic substrate 20 and the one surface 211 of the base substrate 21 are relatively inclined, and the distance between the two fixing surfaces gradually increases in one direction. In this way, even when a semiconductor element such as a diode is soldered to a substrate, or a ceramic substrate having a conductor layer formed on the front and back is soldered to a base substrate, the distance between the fixing surfaces is one-way. By arranging and soldering so as to gradually increase, voids can be suppressed.

  Moreover, although the thermosetting epoxy resin was used here as the protrusion 4, a conductive adhesive in which an Ag filler is dispersed may be used, and the protrusion can be formed even by using a wire bond made of Al or Cu. Become. Further, the same effect can be obtained by installing a ball-like spacer made of Cu or Ni between the element fixing surface of the power semiconductor element 1 and the substrate fixing surface of the heat spreader. Further, the same effect can be obtained by forming the protrusion on the element fixing surface of the upper power semiconductor element 1 instead of the lower layer heat spreader or the ceramic substrate side to be soldered. In addition, Sn—Ag—Cu eutectic solder is used here as the solder material, but the same effect can be obtained with a solder material having other composition such as Sn—Cu series or Sn—Pb series.

  Further, although two protrusions 4 are provided in FIG. 1, only one protrusion may be provided as shown in FIG. Further, as shown in FIG. 6, by arranging two projections 41 having a large height (for example, about 0.2 mm in height) and two small projections 42 (for example having a height of about 0.1 mm) on two opposing sides, It is possible to prevent the temperature cycle performance from deteriorating due to an excessively small solder height on the side having no protrusion and a large distortion due to a difference in thermal expansion coefficient.

  As described above, according to the semiconductor device according to the first embodiment of the present invention, the distance between the element fixing surface 101 of the semiconductor element 1 and the substrate fixing surface 201 of the substrate such as the heat spreader 2 is directed in one direction. Since it is gradually increased, voids are discharged to the outside while the solder is melted, and voids in the die bond portion can be suppressed. As one specific configuration method, a separation member that maintains the distance between the element fixing surface 101 and the substrate fixing surface 201, such as the protrusion 4 or the spacer, is at least 1 at a position offset from the center of the element fixing surface 101 of the semiconductor element 1. The distance between the element fixing surface 101 of the semiconductor element 1 and the substrate fixing surface 201 of the substrate such as the heat spreader 2 with the inclination is determined by the position and height of the separating member and the dimension of the semiconductor element 1 Can be gradually increased in one direction.

  In the semiconductor device in which the other surface 202 of the substrate 20 to which the semiconductor element 1 is fixed on one surface and the one surface 211 of the base substrate 21 are fixed by solder, the distance between the other surface 202 of the substrate 20 and the one surface 211 of the base substrate 21. Is gradually increased in one direction, voids are discharged to the outside while the solder is melted, and voids in the die bond portion can be suppressed. Also in this case, as one specific configuration method, a separation member that maintains the distance between the other surface 202 of the substrate 20 and the one surface 211 of the base substrate 21, such as the protrusion 40 and the spacer, is the center of the other surface 202 of the substrate 20. The distance between the other surface 202 of the substrate 20 and the one surface 211 of the base substrate 21 with an inclination determined by the position and height of the separating member and the dimensions of the substrate 20 is provided. Can be gradually increased in one direction.

Embodiment 2. FIG.
7A and 7B are a side sectional view and a top view, respectively, showing the configuration of the semiconductor device according to the second embodiment of the present invention. In the second embodiment, a plurality of semiconductor elements are fixed to one substrate. For example, as shown in FIG. 7, there are cases where diodes 12, which are power semiconductor elements constituting a 1 in 1 package, are paired with a heat spreader 2 and die-bonded when used in pairs with IGBTs 11, which are power semiconductor elements. In this case, by forming the protrusions 4 on the outer sides, the thick portions of the solder die bond portions 32 are on the outer sides. By arranging in this way, it is possible to control the direction in which the void is removed to the opposite side with respect to the adjacent semiconductor element, preventing solder adhesion on the adjacent semiconductor element due to solder scattering when the void is flipped. It becomes possible to do.

  Further, as shown in FIG. 8, a plurality of pairs of IGBTs 11 and diodes 12 may be arranged on the same heat spreader 2 and die bonded. In such a case, the adjacent semiconductor elements are not present in the direction in which the distance between the element fixing surface of one semiconductor element and the substrate fixing surface of the substrate such as the heat spreader 2 which is the fixing partner gradually increases. That's fine.

Embodiment 3 FIG.
FIG. 9 is a side sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention, and FIG. 10 is a conceptual diagram of the die bonding process of the semiconductor device according to the third embodiment. As shown in FIG. 10A, an epoxy resin protrusion 4 (for example, a diameter of 0.5 mm and a height of 0.2 mm) is dispensed on a 10 mm × 10 mm × 1 mm Cu heat spreader 2 and then heat-cured. To form in two places. Next, as shown in FIG. 10B, a solder ribbon 31 (Sn—Ag—Cu eutectic: melting point 217 ° C.) having a size of 5 mm × 5 mm × thickness 0.2 mm is disposed, and a convex warp on the circuit surface (upper surface). The power semiconductor element 13 (IGBT: Insulated Gate Bipolar Transistor, back surface metallization layer: Al / Ni / Au, surface metallization layer: AlSi / Ni / Au) having a thickness of 7 mm × 7 mm × thickness 0.2 mm is mounted. Finally, as shown in FIG. 10C, the solder die bond portion 32 is formed by heating in a reflow furnace to melt the solder. The solder die bond portion 32 has a thickness of about 0.2 mm on the side where the projection 4 is present, and has a thickness of about 0.05 mm on the side where the projection is not present. At this time, by using the reduced pressure reflow furnace, not only the void is reduced at the time of return pressure, but also the above movement is facilitated by the increase of the void at the time of pressure reduction.

  As shown in FIG. 9, the power semiconductor element 13 is warped and curved so that the fixing surface side is concave. Since the power semiconductor element 13 is curved, the rate of change in the distance between the element fixing surface 101 and the substrate fixing surface 201 varies depending on the position. For this reason, in the protrusion 4 portion, the inclination of the element fixing surface 101 becomes gentle, that is, the rate of change of the distance between the element fixing surface 101 and the substrate fixing surface 201 becomes small, and the circuit surface of the power semiconductor element is almost flat. Become. By forming the wire bond 5 in the portion in a nearly flat state, a good bonding state can be maintained over a relatively wide area, and reliability can be ensured.

  In detail, as shown in FIG. 11, the IGBT can be connected to the main terminal 132 (emitter terminal) by soldering 33 to the electrode plate 6 or the like. In that case, the power semiconductor element is flattened. However, the gate terminal 133 and the temperature sense terminal are still often connected by wire bonds, and in that case, the flatness of the power semiconductor element is important for reliability. Therefore, these wire bond connecting portions of the power semiconductor element need to be flat. The metallization thickness of the gate terminal 133 and the main terminal 132 on the circuit surface (upper surface) of the Si base portion 130 is formed thinner than the metallization layer 131 on the back surface, and the difference in film stress generated on each surface is different. By providing, it becomes possible to give a warp to the power semiconductor element. Even when it is difficult to provide a difference in film thickness, it is possible to make the total area of the gate terminal 133 and the main terminal 132 smaller than the area of the back surface metallization.

  Here, the case where the power semiconductor element is die-bonded to the heat spreader has been described. However, the semiconductor element is not limited to the power semiconductor element but may be other semiconductor elements such as a diode, and the semiconductor element may be fixed. However, the same effect can be obtained even with a ceramic substrate. In addition, even when a ceramic layer with a semiconductor element fixed on one side is soldered to the base substrate of the conductor, a warp is applied to the ceramic substrate to which the semiconductor element is fixed. By arranging and soldering so that the distance between the surfaces gradually increases in one direction, an effect of suppressing voids can be obtained.

  Moreover, although the thermosetting epoxy resin was used here as the protrusion 4, a conductive adhesive in which an Ag filler is dispersed may be used, and the protrusion can be formed even by using a wire bond made of Al or Cu. Become. Further, the same effect can be obtained even when a ball-shaped spacer made of Cu or Ni is arranged. Further, the same effect can be obtained if the protrusions are formed not on the lower heat spreader or the ceramic substrate side where the soldering is performed but on the bottom surface of the upper power semiconductor element or the ceramic substrate.

  In addition, Sn—Ag—Cu eutectic solder is used here as the solder material, but the same effect can be obtained with a solder material having other composition such as Sn—Cu series or Sn—Pb series. Here, soldering is used for electrical joining of the main terminals 132 on the upper surface of the power semiconductor element 13, but the same effect can be obtained by using a conductive adhesive or Ag nanopowder.

Embodiment 4 FIG.
FIG. 12 is a side sectional view showing a detailed configuration of the semiconductor device according to the fourth embodiment of the present invention. On the heat spreader 2 made of Cu of 10 mm × 10 mm × 1 mm, epoxy resin projections 4 (diameter 0.5 mm, height 0.2 mm) are supplied to a dispenser and then heat-cured to form in two places. Next, a solder ribbon 31 (Sn—Ag—Cu eutectic: melting point 217 ° C.) of 5 mm × 5 mm × thickness 0.2 mm was placed, and a warp was applied to the element fixing surface 101 side so as to be convex, 7 mm × A power semiconductor element 13 (IGBT: Insulated Gate Bipolar Transistor, back surface metallization layer: Al / Ni / Au, surface metallization layer: AlSi / Ni / Au) of 7 mm × 0.2 mm thickness is mounted. Finally, it is heated in a reflow furnace to melt the solder and form the solder die bond portion 32. The solder die bond portion 32 has a thickness of about 0.2 mm on the side where the projection 4 is present, and has a thickness of about 0.05 mm on the side where the projection is not present. At this time, by using the reduced pressure reflow furnace, not only the void is reduced at the time of return pressure, but also the above movement is facilitated by the increase of the void at the time of pressure reduction.

  As shown in FIG. 12, the power semiconductor element 13 is warped and curved so as to protrude toward the fixing surface. Since the power semiconductor element 13 is curved, the rate of change in the distance between the element fixing surface 101 and the substrate fixing surface 201 varies depending on the position. For this reason, the rate of change of the distance between the element fixing surface 101 and the substrate fixing surface 201 becomes small on the side without the projection 4, and the circuit surface of the power semiconductor element 13 on the side without the projection 4 becomes almost flat. By forming the wire bond 5 in the portion in a nearly flat state, a good bonding state can be maintained over a relatively wide area, and reliability can be ensured. Specifically, as shown in FIG. 12, the IGBT can be connected to the main terminal 132 (emitter terminal) by soldering 33 to the electrode plate 6 or the like, and in this case, the power semiconductor element is flattened. However, the gate terminal 133 and the temperature sense terminal are still often connected by wire bonds, and in that case, the flatness of the power semiconductor element is important for reliability. Therefore, these wire bond connecting portions of the power semiconductor element 13 need to be flat. In order to give warpage to the power semiconductor element 13, the metallized thickness of the gate terminal 133 and the main terminal 132 on the circuit surface (upper surface) of the Si base portion 130 is formed thicker than the metallized layer 131 on the back surface. This is possible by providing a difference in the film stress generated on each surface.

  Here, the case where the power semiconductor element is die-bonded to the heat spreader has been described. However, the semiconductor element is not limited to the power semiconductor element but may be other semiconductor elements such as a diode, and the semiconductor element may be fixed. However, the same effect can be obtained even with a ceramic substrate. In addition, even when the conductor layer is formed on the front and back, and the other surface of the ceramic substrate with the semiconductor element fixed on one side is soldered to the base substrate of the conductor, the ceramic substrate with the semiconductor element fixed is warped. And the effect that a void can be suppressed is acquired by arrange | positioning and soldering so that the distance between fixed surfaces may increase gradually to one direction.

  Moreover, although the thermosetting epoxy resin was used here as the protrusion 4, a conductive adhesive in which an Ag filler is dispersed may be used, and the protrusion can be formed even by using a wire bond made of Al or Cu. Become. The same effect can be obtained by using a ball spacer made of Cu or Ni. Further, the same effect can be obtained if the protrusions are formed not on the lower heat spreader or the ceramic substrate side where the soldering is performed but on the bottom surface of the upper power semiconductor element or the ceramic substrate.

  In addition, Sn—Ag—Cu eutectic solder is used here as the solder material, but the same effect can be obtained with a solder material having other composition such as Sn—Cu series or Sn—Pb series. Here, soldering is used for electrical joining of the main terminals 132 on the upper surface of the power semiconductor element 13, but the same effect can be obtained by using a conductive adhesive or Ag nanopowder.

  In the present invention, the embodiments can be appropriately combined, modified, and omitted within the scope of the invention.

DESCRIPTION OF SYMBOLS 1 Power semiconductor element, 2 Heat spreader, 11 IGBT, 12 Diode, 13 Power semiconductor element which provided the warp, 4 Protrusion (separation member), 5 Wire bond, 20 Ceramic substrate, 21 Base substrate, 31 Solder ribbon, 32 Solder die bond part , 101 Device fixing surface, 133 Gate terminal (wire bond connection part), 201 Substrate fixing surface, 202 Other surface of ceramic substrate, 211 One surface of base substrate

Claims (9)

In a semiconductor device in which an element fixing surface which is one surface of a semiconductor element is fixed to a substrate fixing surface which is one surface of a substrate by solder,
The semiconductor element is curved such that the element fixing surface is concave or convex with respect to the substrate fixing surface,
A distance between the element fixing surface and the substrate fixing surface is gradually increased in one direction. The semiconductor device according to claim 1, wherein the semiconductor element is curved so that the element fixing surface is concave with respect to the substrate fixing surface. A separation member for maintaining a distance between the element fixing surface and the substrate fixing surface is provided at a position between the element fixing surface and the substrate fixing surface and deviating from a center of the element fixing surface. The semiconductor device according to claim 1 or 2 . The semiconductor device according to claim 3 , wherein the separation member is a protrusion formed on the substrate fixing surface. The semiconductor device according to claim 3 , wherein the separation member is a spacer disposed between the element fixing surface and the substrate fixing surface. A plurality of semiconductor elements are fixed to one surface of the substrate, and there are no adjacent semiconductor elements in a direction in which the distance between the element fixing surface of one semiconductor element and the substrate fixing surface gradually increases. The semiconductor device according to any one of claims 1 to 5 . The wire bond connection portion is disposed on a surface of the semiconductor element on a side opposite to the element fixing surface on a side where a change rate of a distance between the element fixing surface and the substrate fixing surface is small. Item 3. The semiconductor device according to Item 1 or 2 . The main terminal of the semiconductor element is disposed on the surface of the semiconductor element opposite to the element fixing surface, on the side where the change rate of the distance between the element fixing surface and the substrate fixing surface is large. 8. The semiconductor device according to claim 7, wherein the terminal is connected to a plate electrode plate. Between the element fixing surface and the substrate fixing surface, a plate-like member having a conductor layer on both sides is disposed, between the element fixing surface and the plate-like member, and between the plate-like member and the substrate fixing surface. 2. The semiconductor device according to claim 1, wherein the distance between and increases gradually in one direction in the opposite direction.

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