JP4146785B2 - Power semiconductor device - Google Patents

Power semiconductor device Download PDF

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Publication number
JP4146785B2
JP4146785B2 JP2003389254A JP2003389254A JP4146785B2 JP 4146785 B2 JP4146785 B2 JP 4146785B2 JP 2003389254 A JP2003389254 A JP 2003389254A JP 2003389254 A JP2003389254 A JP 2003389254A JP 4146785 B2 JP4146785 B2 JP 4146785B2
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Japan
Prior art keywords
semiconductor device
power semiconductor
chip
power
wire
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Expired - Lifetime
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JP2003389254A
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Japanese (ja)
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JP2005150595A (en
Inventor
建一 林
寿 川藤
竜征 竹下
興宣 井上
弘幸 尾崎
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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Priority to JP2003389254A priority Critical patent/JP4146785B2/en
Publication of JP2005150595A publication Critical patent/JP2005150595A/en
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Publication of JP4146785B2 publication Critical patent/JP4146785B2/en
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
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    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
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    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
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Description

本発明は、電力用半導体装置に関し、特に、小型でかつ信頼性の高い電力用半導体装置の提供を目的とする。   The present invention relates to a power semiconductor device, and in particular, provides a power semiconductor device that is small and highly reliable.

電力用半導体装置は、パワーチップと、パワーチップを制御するための制御チップ（ロジックチップ）とをフレーム上にダイボンドし、チップ同士をワイヤで接続し、更にチップ等を樹脂でモールドして形成される。制御チップとパワーチップとの間は、制御チップとフレーム上の中継パッドとが金のワイヤで接続され、更に、中継パッドとパワーチップとがアルミニウムのワイヤで接続されている（例えば、特許文献１）。
これに対して、電力用半導体装置の小型化には、かかる中継パッドをなくして制御チップとパワーチップとを直接、ワイヤで接続するのが好ましい。
特開２０００−１３８３４３号公報 A power semiconductor device is formed by die-bonding a power chip and a control chip (logic chip) for controlling the power chip on a frame, connecting the chips together with a wire, and further molding the chip with a resin. The Between the control chip and the power chip, the control chip and the relay pad on the frame are connected by a gold wire, and further, the relay pad and the power chip are connected by an aluminum wire (for example, Patent Document 1). ).
On the other hand, to reduce the size of the power semiconductor device, it is preferable to directly connect the control chip and the power chip with a wire without the relay pad.
JP 2000-138343 A

制御チップとパワーチップとを、金のワイヤで直接接続した場合、パワーチップの表面電極を形成するアルミニウムとワイヤを形成する金が接続される。パワーチップは、発熱により温度が上昇するため、アルミニウムと金が合金化し、接合部の強度の劣化や断線が発生するという問題があった。一方、制御チップとパワーチップとをアルミニウムのワイヤで直接接続した場合には、ワイヤの強度に問題があった。また、ワイヤの強度を上げるためにワイヤを太くした場合、制御チップのワイヤボンディングパッドを大きくせざるを得ず、チップの大型化やコストアップの原因となるという問題もあった。   When the control chip and the power chip are directly connected by a gold wire, the aluminum that forms the surface electrode of the power chip and the gold that forms the wire are connected. Since the temperature of the power chip rises due to heat generation, there is a problem that aluminum and gold are alloyed, and the strength of the joint portion is deteriorated or the wire breaks. On the other hand, when the control chip and the power chip are directly connected with an aluminum wire, there is a problem in the strength of the wire. Further, when the wire is thickened to increase the strength of the wire, the wire bonding pad of the control chip has to be enlarged, which causes a problem of increasing the size and cost of the chip.

そこで、本発明は、制御チップとパワーチップが直接接続された小型で信頼性の高い電力用半導体装置の提供を目的とする。   Therefore, an object of the present invention is to provide a small and highly reliable power semiconductor device in which a control chip and a power chip are directly connected.

本発明は、モールド樹脂から複数のリードが突出した電力用半導体装置であって、第１ダイパッド部を含む第１リードと、第１ダイパッド部の表面に載置されたパワーチップと、第１ダイパッド部の裏面に取り付けられた、モールド樹脂より熱伝導率の大きな樹脂からなる絶縁シートと、第２ダイパッド部を含む第２リードと、第２ダイパッド部上に載置された制御チップと、パワーチップと制御チップとを直接接続する金を主成分とするワイヤと、第１リードと第２リードの端部がそれぞれ突出するように制御チップとパワーチップとを埋め込むモールド樹脂とを含み、絶縁シートとモールド樹脂との界面に、それぞれの材料が混ざった混合層を有することを特徴とする電力用半導体装置である。
The present invention is a power semiconductor device in which a plurality of leads protrude from a mold resin, and includes a first lead including a first die pad portion, a power chip placed on the surface of the first die pad portion, and a first die pad. An insulating sheet made of a resin having a higher thermal conductivity than the mold resin, a second lead including a second die pad part, a control chip placed on the second die pad part, and a power chip A wire mainly composed of gold that directly connects the control chip and the control chip, and a mold resin that embeds the control chip and the power chip so that the ends of the first lead and the second lead protrude, respectively, A power semiconductor device having a mixed layer in which respective materials are mixed at an interface with a mold resin.

以上の説明から明らかなように、本発明にかかる電力用半導体装置では、小型でかつ信頼性の高い電力用半導体装置の提供が可能となる。   As is clear from the above description, the power semiconductor device according to the present invention can provide a power semiconductor device that is small and highly reliable.

実施の形態１．
図１は、全体が１００で表される、本実施の形態にかかる電力用半導体装置の斜視図であり、図２は、図１のＩ−Ｉ方向の断面図である。
図２に示すように、電力用半導体装置１００は、複数のリード１を含む。一のリード１は、ボンディングパッド部１ａと、ボンディングパッド部１ａより低い位置にあるダイパッド部１ｂを含む。ボンディングパッド部１ａとダイパッド部１ｂは、リード１を曲げることにより形成される。他方のリード１は、ボンディングパッド部１ａと略同一高さのボンディングパッド部１ｃを含む。リードは、例えば銅などの導電性の良い金属からなる。 Embodiment 1 FIG.
FIG. 1 is a perspective view of a power semiconductor device according to the present embodiment, indicated as a whole by 100, and FIG. 2 is a cross-sectional view in the II direction of FIG.
As shown in FIG. 2, the power semiconductor device 100 includes a plurality of leads 1. One lead 1 includes a bonding pad portion 1a and a die pad portion 1b located at a position lower than the bonding pad portion 1a. The bonding pad portion 1 a and the die pad portion 1 b are formed by bending the lead 1. The other lead 1 includes a bonding pad portion 1c having substantially the same height as the bonding pad portion 1a. The lead is made of a highly conductive metal such as copper.

ダイパッド部１ｂの上には、ＩＧＢＴ（Insulate Gate Bipolar Transistor）２１、ＦＷＤｉ（Free Wheeling Diode）２２の２つのパワーチップ２がはんだで固着されている。パワーチップ２の表面電極とリード１のボンディングパッド部１ａ、パワーチップ２の表面電極同士は、アルミニウムのワイヤ５により接続されている。   On the die pad portion 1b, two power chips 2 of IGBT (Insulate Gate Bipolar Transistor) 21 and FWDi (Free Wheeling Diode) 22 are fixed with solder. The surface electrode of the power chip 2, the bonding pad portion 1 a of the lead 1, and the surface electrodes of the power chip 2 are connected by an aluminum wire 5.

一方、パワーチップ２を制御するための制御チップ３は、フレーム１のボンディングパッド部１ｃにはんだで固着されている。制御チップ３の表面電極と、パワーチップ２の表面電極とは、金のワイヤ４により接続されている。パワーチップ２上には金からなるバンプ９が形成され、ワイヤ４はバンプ９に接続されている。   On the other hand, the control chip 3 for controlling the power chip 2 is fixed to the bonding pad portion 1c of the frame 1 with solder. The surface electrode of the control chip 3 and the surface electrode of the power chip 2 are connected by a gold wire 4. Bumps 9 made of gold are formed on the power chip 2, and the wires 4 are connected to the bumps 9.

図３は、パワー半導体装置１００に用いるリードフレームであり、図３（ａ）はその上面図、図３（ｂ）はリードを組み込んだパワー半導体装置の概略図である。
リードフレームには、予め所定の回路が形成されており、その上に、ＩＧＢＴ２１、ＦＷＤｉ２２、制御チップ３が固着される。リード１とＩＧＢＴ２１との間は金のワイヤ４により接続される。また、リード１とＦＷＤｉ２２との間、ＩＧＢＴ２１とＦＷＤｉ２２との間は、アルミニウムのワイヤ５で接続される。 3A and 3B are lead frames used in the power semiconductor device 100, FIG. 3A is a top view thereof, and FIG. 3B is a schematic diagram of the power semiconductor device in which leads are incorporated.
A predetermined circuit is formed in advance on the lead frame, and the IGBT 21, the FWDi 22, and the control chip 3 are fixed thereon. The lead 1 and the IGBT 21 are connected by a gold wire 4. Further, the lead 1 and the FWDi 22 and the IGBT 21 and the FWDi 22 are connected by an aluminum wire 5.

パワーチップ２の表面は、パワーチップ２の発熱により高温になる。このため、ワイヤ４の材料である金と、パワーチップ２の表面電極を形成するアルミニウムとの間で、金−アルミニウム合金が形成される。金−アルミニウム合金の形成が進むと、機械的強度や電気的特性が劣化し、電力用半導体装置１００の特性不良の原因となる。   The surface of the power chip 2 becomes high temperature due to heat generated by the power chip 2. For this reason, a gold-aluminum alloy is formed between gold which is the material of the wire 4 and aluminum which forms the surface electrode of the power chip 2. As the formation of the gold-aluminum alloy progresses, the mechanical strength and electrical characteristics deteriorate, which causes the characteristic failure of the power semiconductor device 100.

そこで、本実施の形態にかかる電力用半導体装置１００では、モールド樹脂６よりも、熱伝導率の大きな絶縁樹脂シート７を、ダイパッド部１ｂの下に配置し、パワーチップ２からの放熱特性を向上させている。このため、パワーチップ２と制御チップ３とを金のワイヤ４で直接接続しても、パワーチップ２の昇温が小さいため、金−アルミニウム合金層の形成が抑制される。   Therefore, in the power semiconductor device 100 according to the present embodiment, the insulating resin sheet 7 having a thermal conductivity higher than that of the mold resin 6 is disposed under the die pad portion 1b to improve the heat dissipation characteristics from the power chip 2. I am letting. For this reason, even if the power chip 2 and the control chip 3 are directly connected by the gold wire 4, since the temperature rise of the power chip 2 is small, the formation of the gold-aluminum alloy layer is suppressed.

具体的には、ダイパッド部１ｂの裏面に、モールド樹脂６より熱伝導率の大きい絶縁樹脂シート７が、直接固着される。絶縁樹脂シート７の大きさはダイパッド部１ｂよりも大きく、樹脂シート７の他方の面には銅箔８が固着される。更に、銅箔８の裏面が外部に露出するように、パワーチップ２等がモールド樹脂６で封止されている。   Specifically, an insulating resin sheet 7 having a thermal conductivity higher than that of the mold resin 6 is directly fixed to the back surface of the die pad portion 1b. The size of the insulating resin sheet 7 is larger than that of the die pad portion 1b, and the copper foil 8 is fixed to the other surface of the resin sheet 7. Further, the power chip 2 and the like are sealed with the mold resin 6 so that the back surface of the copper foil 8 is exposed to the outside.

ここで、絶縁樹脂シート７には、Ａｌ２Ｏ３、Ｓｉ３Ｎ４、ＡｌＮ等のセラミック、ＳｉＯ２、絶縁材料でコーティングした金属から選択される少なくとも１種類以上の材料の微粒子を含む樹脂を用いても良い。 Here, the insulating resin sheet 7 includes a resin containing fine particles of at least one material selected from ceramics such as Al 2 O 3 , Si 3 N 4 , and AlN, SiO 2 , and a metal coated with an insulating material. It may be used.

上述のように、熱伝導性の高い絶縁樹脂シート７を設けることにより、パワーチップ２に対する冷却性能が向上し、パワーチップ２と制御チップ３とを、中継パッドを介することなく直接金のワイヤ４で接続できる。この結果、電力用半導体装置１００の小型化が可能となる。   As described above, by providing the insulating resin sheet 7 having high thermal conductivity, the cooling performance for the power chip 2 is improved, and the power chip 2 and the control chip 3 are directly connected to the gold wire 4 without using a relay pad. Can be connected. As a result, the power semiconductor device 100 can be reduced in size.

また、モールド樹脂６中のフィラーの材質、量、形状に対する制約が大きく緩和され、粘度の小さなモールド樹脂の選択が可能となり、モールド樹脂注入時に懸念される金のワイヤの変形等を防止できる。この結果、ワイヤの変形等による不具合を防止できるとともに、金のワイヤ４を細くして、低コスト化を図ることができる。   In addition, restrictions on the material, amount, and shape of the filler in the mold resin 6 are greatly relaxed, and a mold resin having a low viscosity can be selected, so that deformation of a gold wire, which is a concern at the time of mold resin injection, can be prevented. As a result, it is possible to prevent problems due to wire deformation and the like and to reduce the cost by making the gold wire 4 thinner.

更に、銅箔８は、絶縁樹脂シート７を保護しており、パワー半導体装置１００の信頼性、取扱いの容易性を向上させている。   Further, the copper foil 8 protects the insulating resin sheet 7 and improves the reliability and ease of handling of the power semiconductor device 100.

ここで、モールド樹脂６と絶縁樹脂シート７と接触する部分では、両者の混合層１０が形成されている。例えば、絶縁樹脂シート７、モールド樹脂６ともに、エポキシ樹脂を用い、モールド時に同時に硬化させれば、容易に混合層１０が形成できる。混合層１０の形成により、モールド樹脂６と絶縁樹脂シート７との間の明確な界面が消滅し、沿面絶縁耐力が向上する。つまり、沿面絶縁距離を小さくでき、パワー半導体装置１００の小型化が可能となる。   Here, the mixed layer 10 of both is formed in the part which contacts the mold resin 6 and the insulating resin sheet 7. For example, the mixed layer 10 can be easily formed by using an epoxy resin for both the insulating resin sheet 7 and the mold resin 6 and simultaneously curing at the time of molding. By forming the mixed layer 10, a clear interface between the mold resin 6 and the insulating resin sheet 7 disappears, and the creeping dielectric strength is improved. That is, the creeping insulation distance can be reduced, and the power semiconductor device 100 can be downsized.

なお、ワイヤ４には、金の他に、金にパラジウムを添加した合金を用いても良い。かかる合金のワイヤ４を用いることにより、表面電極との間で金−アルミニウムの合金が成長するのを抑制できる。つまり、ワイヤ４にパラジウムを添加した金を用いることにより、金−アルミニウム合金の成長を更に抑制し、信頼性を一層向上させることができる。   The wire 4 may be made of an alloy obtained by adding palladium to gold in addition to gold. By using the wire 4 of such an alloy, it is possible to suppress the growth of a gold-aluminum alloy with the surface electrode. That is, by using gold added with palladium for the wire 4, the growth of the gold-aluminum alloy can be further suppressed, and the reliability can be further improved.

次に、電力用半導体装置１００におけるチップ周囲での絶縁について説明する。電力用半導体装置１００では、ＩＧＢＴ２１等のパワーチップ２などに数百Ｖ以上の高電圧が印加される。図４（ａ）は、ＩＧＢＴ２１の上面図であり、図４（ｂ）は（ａ）をIV−IV方向に見た断面図である。
図４（ａ）に示すように、ＩＧＢＴ２１は、ＩＧＢＴ２１自身の耐圧を確保するために、高電圧領域３４がガードリング部３３で囲まれた構造となっている。高電圧領域３４に接続される金のワイヤ４においても、周囲との耐圧の確保が重要な課題となる。即ち、ワイヤ４とチップ端部３５との間で高い絶縁耐圧を得るには、空間距離ｄ４１（ＩＧＢＴ２１の周辺端部３５における、ＩＧＢＴ２１とワイヤ４との垂直方向の距離：図４（ｂ）参照）を所定の絶縁距離以上に保つことが必要となる。ここで、所定の絶縁距離としては、例えば、モールド樹脂を充填した後においては数百μｍ程度の距離となる。この点が、特に耐圧を必要としない一般のＩＣ等と異なり、電力用半導体装置固有の課題であると言える。因みに、一般のＩＣでは、絶縁距離は１０μｍ程度である。 Next, the insulation around the chip in the power semiconductor device 100 will be described. In the power semiconductor device 100, a high voltage of several hundred volts or more is applied to the power chip 2 such as the IGBT 21. 4A is a top view of the IGBT 21, and FIG. 4B is a cross-sectional view of FIG. 4A viewed in the IV-IV direction.
As shown in FIG. 4A, the IGBT 21 has a structure in which a high voltage region 34 is surrounded by a guard ring portion 33 in order to ensure the breakdown voltage of the IGBT 21 itself. Also in the gold wire 4 connected to the high voltage region 34, securing the breakdown voltage with the surroundings is an important issue. That is, in order to obtain a high withstand voltage between the wire 4 and the chip end portion 35, the spatial distance d41 (the vertical distance between the IGBT 21 and the wire 4 at the peripheral end portion 35 of the IGBT 21: see FIG. 4B). ) Must be kept above a predetermined insulation distance. Here, the predetermined insulation distance is, for example, a distance of about several hundred μm after the mold resin is filled. This can be said to be a problem unique to a power semiconductor device, unlike a general IC that does not particularly require a withstand voltage. Incidentally, in a general IC, the insulation distance is about 10 μm.

次に、ワイヤ４とＩＧＢＴ２１との接続部の構造について、図５を参照しながら説明する。図５は、ワイヤ４のボンディング工程の概略図であり、図５では、説明を容易にするために、制御チップ３とパワーチップ２（ＩＧＢＴ２１）の表面が、略同じ高さにあるものとする。   Next, the structure of the connecting portion between the wire 4 and the IGBT 21 will be described with reference to FIG. FIG. 5 is a schematic view of the bonding process of the wire 4. In FIG. 5, it is assumed that the surfaces of the control chip 3 and the power chip 2 (IGBT 21) are substantially at the same height for easy explanation. .

ボンディング工程では、まず、図５（ａ）に示すように、制御チップ３の電極上に、金のワイヤ４が、ツール３０によりボールボンディングされる（以下、「１ｓｔボンディング」という。）。   In the bonding step, first, as shown in FIG. 5A, the gold wire 4 is ball-bonded on the electrode of the control chip 3 by the tool 30 (hereinafter referred to as “1st bonding”).

次に、図５（ｂ）（ｃ）に示すように、ワイヤ４に所定のループを形成する。   Next, as shown in FIGS. 5B and 5C, a predetermined loop is formed in the wire 4.

次に、図５（ｄ）（ｅ）に示すように、ＩＧＢＴ２１の表面電極上に、ステッチボンディングを行なう（以下、「２ｎｄボンディング」という。）。   Next, as shown in FIGS. 5D and 5E, stitch bonding is performed on the surface electrode of the IGBT 21 (hereinafter referred to as “2nd bonding”).

このような工程で作製したワイヤ４では、図５（ｅ）に示すように、ＩＧＢＴ２１の端部において、ワイヤ４とＩＧＢＴ２１との空間距離ｄ４１が小さくなる。このため、空間距離ｄ４１を所定の絶縁距離にするためには、ＩＧＢＴ２１とワイヤ４との接続部をＩＧＢＴ２１の中央方向（図５では右方向）に移動せざるを得ず、ＩＧＢＴ２１上でワイヤ４が延在する距離（助走距離）ｄｘが大きくなる。   In the wire 4 manufactured by such a process, the spatial distance d41 between the wire 4 and the IGBT 21 becomes small at the end of the IGBT 21, as shown in FIG. For this reason, in order to make the spatial distance d41 a predetermined insulation distance, the connection portion between the IGBT 21 and the wire 4 must be moved in the center direction of the IGBT 21 (rightward in FIG. 5), and the wire 4 on the IGBT 21. The distance (running distance) dx over which is extended becomes larger.

即ち、制御チップ３とＩＧＢＴ２１とを、中継パッドを介さずに、ワイヤ４で直接接した場合、空間距離ｄ４１を所定の絶縁距離にするにはワイヤ４が長くなり、樹脂モールド時にワイヤ４が変形し、不具合が発生するという問題があった。   That is, when the control chip 3 and the IGBT 21 are in direct contact with the wire 4 without using a relay pad, the wire 4 becomes long to make the spatial distance d41 a predetermined insulation distance, and the wire 4 is deformed during resin molding. However, there was a problem that a malfunction occurred.

また、金のワイヤ４の使用量が増えるため、製造コストの増加原因ともなっていた。   Moreover, since the usage-amount of the gold wire 4 increases, it has also become a cause of an increase in manufacturing cost.

更に、ＩＧＢＴ２１の設計の自由度を制限し、結果としてチップサイズの増大を招き、製品の小型化や低コスト化を阻害するという問題もあった。   Furthermore, there is a problem that the degree of freedom in designing the IGBT 21 is limited, resulting in an increase in chip size, which hinders downsizing and cost reduction of the product.

そこで、本実施の形態にかかる電力用半導体装置１００では、図２に示すように、制御チップ３がＩＧＢＴ２１より上方に配置されるため、このような問題の発生が防止できる。
即ち、図６（ａ）に示すように、ＩＧＢＴ２１上での２ｎｄボンディングにおいて、ワイヤ４の立ち上がり角度が大きくなる。この結果、空間距離ｄ４１を所定の絶縁距離にするための、助走距離ｄｘを短くできる。 Therefore, in the power semiconductor device 100 according to the present embodiment, as shown in FIG. 2, since the control chip 3 is disposed above the IGBT 21, such a problem can be prevented.
That is, as shown in FIG. 6A, in the 2nd bonding on the IGBT 21, the rising angle of the wire 4 is increased. As a result, the run-up distance dx for making the spatial distance d41 a predetermined insulation distance can be shortened.

これにより、ワイヤ４が長くなることに起因する不具合、高コスト化を防止できるとともに、電力用半導体装置１００の小型化も可能となる。   As a result, it is possible to prevent problems due to the length of the wire 4 and an increase in cost, and it is possible to reduce the size of the power semiconductor device 100.

ここで、パワーチップ３からの放熱効率を上げるためには、パワーチップ３を電力用半導体装置１００の下方に配置することが好ましい。これは、電力用半導体装置１００の裏面に取り付けられる放熱フィン（図示せず）にパワーチップを近づけることにより、放熱性を良好にするためである。よって、本実施の形態にかかる電力用半導体装置１００では、上方に制御チップ３、下方にパワーチップ２を配置するとともに、制御チップ３側で１ｓｔボンディングを行ない、続いてパワーチップ２側で２ｎｄボンディングを行ない、両者の接続を行なっている。   Here, in order to increase the heat dissipation efficiency from the power chip 3, it is preferable to dispose the power chip 3 below the power semiconductor device 100. This is to improve heat dissipation by bringing the power chip closer to the heat dissipating fins (not shown) attached to the back surface of the power semiconductor device 100. Therefore, in the power semiconductor device 100 according to the present embodiment, the control chip 3 is disposed on the upper side, the power chip 2 is disposed on the lower side, the first bonding is performed on the control chip 3 side, and then the 2nd bonding is performed on the power chip 2 side. To connect the two.

また、図６（ｂ）に示すように、ＩＧＢＴ２１上に、予め金のバンプ１１を形成し、その上に２ｎｄボンディングを行うことにより、更に、所定の絶縁距離の確保が容易となる。即ち、バンプ１１は、空間距離ｄ４１を所定の絶縁距離にするためのスペーサとして機能する。また、このバンプ１１は、ＩＧＢＴ２１へのボンディングツール（図示せず）の衝突等による損傷を防止できるという効果もある。   Further, as shown in FIG. 6B, a predetermined insulation distance can be easily ensured by forming gold bumps 11 on the IGBT 21 in advance and performing 2nd bonding thereon. That is, the bump 11 functions as a spacer for setting the spatial distance d41 to a predetermined insulation distance. In addition, the bump 11 has an effect of preventing damage due to a collision of a bonding tool (not shown) to the IGBT 21.

更に、２ｎｄボンディングが、ＩＧＢＴ２１の表面電極に直接ボンディングされる場合の、金とアルミニウムとの接合より、プロセスマージンの広い金と金との接合となるため、製造容易性が増すという効果もある。   Furthermore, since the 2nd bonding is a bonding between gold and gold having a wider process margin than the bonding between gold and aluminum when bonding directly to the surface electrode of the IGBT 21, there is also an effect that the manufacturability is increased.

次に、図７を参照しながら、図６（ａ）に示すバンプ１１の形成方法について説明する。バンプ１１の形成工程では、図７（ａ）〜（ｃ）に示すように、通常のボンディング方法を用いてＩＧＢＴ２１上にツール３０でボールボンディングを行なう。次に、図７（ｄ）に示すように、図５（ｃ）のようなループを形成することなくステッチボンディングを行なう。ステッチボンディングは、ボールボンディング部の上からＩＧＢＴ２１の内部に向って行なうのが好ましい。
かかるボンディング工程により、図７（ｄ）に示すように、バンプ１１の断面（紙面に平行な方向の断面）を略デルタ形状にすることができる。 Next, a method for forming the bump 11 shown in FIG. 6A will be described with reference to FIG. In the bump 11 formation process, as shown in FIGS. 7A to 7C, ball bonding is performed with the tool 30 on the IGBT 21 using a normal bonding method. Next, as shown in FIG. 7D, stitch bonding is performed without forming a loop as shown in FIG. Stitch bonding is preferably performed from above the ball bonding portion toward the inside of the IGBT 21.
By this bonding step, as shown in FIG. 7D, the cross section of the bump 11 (the cross section in the direction parallel to the paper surface) can be formed into a substantially delta shape.

なお、バンプ１１の形状は、高さの最も高い部分が、ＩＧＢＴ２１の周辺部に寄った形状とすることが好ましい。即ち、図７（ｄ）のバンプ形状の場合、図の左側がＩＧＢＴ２１の周辺部、右側がＩＧＢＴ２１の中央部となる。   In addition, it is preferable that the shape of the bump 11 is a shape in which the highest part is close to the peripheral portion of the IGBT 21. That is, in the case of the bump shape of FIG. 7D, the left side of the figure is the peripheral portion of the IGBT 21 and the right side is the central portion of the IGBT 21.

図８は、図７（ｄ）に示す略デルタ形状のバンプ１１上に、ワイヤ４を接合した場合を示す。図８から明らかなように、バンプ１１を用いることにより、空間距離ｄ４１を、容易に所定の絶縁距離とすることができる。   FIG. 8 shows a case where the wire 4 is bonded onto the substantially delta-shaped bump 11 shown in FIG. As apparent from FIG. 8, by using the bumps 11, the spatial distance d41 can be easily set to a predetermined insulating distance.

また、図８に示すように、バンプ１１とワイヤ４とが接する２ｎｄボンディング位置は、バンプ１１の中心よりもＩＧＢＴ２１の中央側であることが好ましい。このようにすることにより、バンプ１１がワイヤ４を支え、バンプ１１の斜面に沿ってワイヤ４が延在する。このため、ＩＧＢＴ２１とワイヤ１１のなす角度を大きくでき、空間距離ｄ４１を、容易に所定の絶縁距離以上にすることができる。また、助走距離ｄｘを小さくでき、電力用半導体装置１００の小型化、低コスト化が可能となる。   Further, as shown in FIG. 8, the 2nd bonding position where the bump 11 and the wire 4 are in contact with each other is preferably closer to the center of the IGBT 21 than the center of the bump 11. By doing so, the bump 11 supports the wire 4, and the wire 4 extends along the slope of the bump 11. For this reason, the angle which IGBT21 and the wire 11 make can be enlarged, and the spatial distance d41 can be easily made more than predetermined insulation distance. Further, the running distance dx can be reduced, and the power semiconductor device 100 can be reduced in size and cost.

また、かかる構造を用いることにより、空間距離ｄ４１を確実に所定の絶縁距離以上にできる。このため、絶縁距離を確保するための設計マージンを、バンプ１１を用いない構造よりも小さく設定できる。   In addition, by using such a structure, the spatial distance d41 can be surely made greater than or equal to a predetermined insulation distance. For this reason, the design margin for ensuring the insulation distance can be set smaller than the structure using no bump 11.

なお、本実施の形態では、絶縁樹脂シート７を用いた電力用半導体装置１００について説明したが、熱伝導率がモールド樹脂６よりも大きな他の絶縁材料を、絶縁樹脂シート７に代えて用いても構わない。この場合には、ダイパッド部１ｂとかかる絶縁材料との間を、熱伝導性の接着材料で固定しても構わない。   In the present embodiment, the power semiconductor device 100 using the insulating resin sheet 7 has been described. However, another insulating material having a thermal conductivity higher than that of the mold resin 6 is used instead of the insulating resin sheet 7. It doesn't matter. In this case, the die pad portion 1b and the insulating material may be fixed with a heat conductive adhesive material.

また、本実施の形態では、パワーチップ２としてＩＧＢＴ２１を用いる場合について説明したが、制御チップ３で制御されるパワーチップ２であれば、例えばＭＯＳＦＥＴ等の他のチップであっても良い。   Further, in the present embodiment, the case where the IGBT 21 is used as the power chip 2 has been described. However, as long as the power chip 2 is controlled by the control chip 3, another chip such as a MOSFET may be used.

また、本実施の形態では、パワーチップ２や制御チップ３をはんだで固着する場合について説明したが、機能的に問題が無ければ、例えば導電性接着剤等の他の固着材料を用いても良い。   In the present embodiment, the case where the power chip 2 and the control chip 3 are fixed with solder has been described. However, if there is no functional problem, another fixing material such as a conductive adhesive may be used. .

実施の形態２．
図９は、全体が２００で表される、本実施の形態にかかる電力用半導体装置の断面図である。図９は、図１のＩ−Ｉと同じ方向に見た場合の断面図であり、図９中、図１、２と同一符号は、同一又は相当箇所を示す。 Embodiment 2. FIG.
FIG. 9 is a cross-sectional view of the power semiconductor device according to the present embodiment, indicated as a whole by 200. 9 is a cross-sectional view when viewed in the same direction as II in FIG. 1, and in FIG. 9, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding portions.

電力用半導体装置２００では、リード１のダイパッド部１ｂの裏面に、絶縁樹脂シート７に代えて、セラミック板５０を用いる。セラミック板５０以外の構造は、上述の電力用半導体装置１００とほぼ同じである。セラミック板５０の材料には、例えば、Ａｌ２Ｏ３、ＡｌＮ、Ｓｉ３Ｎ４等が用いられる。 In the power semiconductor device 200, the ceramic plate 50 is used instead of the insulating resin sheet 7 on the back surface of the die pad portion 1 b of the lead 1. The structure other than the ceramic plate 50 is almost the same as that of the power semiconductor device 100 described above. For example, Al 2 O 3 , AlN, Si 3 N 4 or the like is used as the material of the ceramic plate 50.

セラミック板５０とダイパッド部１ｂとの間には、放熱性をより向上させるために、高熱伝導性、絶縁性を有する接着剤を用いることが好ましい。接着剤としては、例えばエポキシ樹脂やシリコーン樹脂等からなるベース樹脂に、Ａｌ２Ｏ３、ＢＮ、ＡｌＮ、Ｓｉ３Ｎ４、ＳｉＯ２等から選択される微粒子を加えた接着材が用いられる。特に、セラミック板５０とダイパッド部１ｂとの膨張係数のミスマッチを緩和するためには弾性率が小さい方が好ましいため、シリコーン樹脂がベース基材であることが好ましい。 It is preferable to use an adhesive having high thermal conductivity and insulation between the ceramic plate 50 and the die pad portion 1b in order to further improve heat dissipation. As the adhesive, for example, an adhesive is used in which fine particles selected from Al 2 O 3 , BN, AlN, Si 3 N 4 , SiO 2 and the like are added to a base resin made of, for example, an epoxy resin or a silicone resin. In particular, in order to relieve the mismatch in expansion coefficient between the ceramic plate 50 and the die pad portion 1b, it is preferable that the elastic modulus is small. Therefore, it is preferable that the silicone resin is the base substrate.

図１０に、ＩＧＢＴ２１上の金のバンプ９の形成工程を示す。形成工程では、図１０（ａ）（ｂ）に示すように、ツール５０を用いて金のワイヤ４をＩＧＢＴ２１の表面にボールボンディングした後、図１０（ｃ）に示すように、ワイヤ４を上方に引き上げて、引き千切るように切断する。
このように、金のワイヤ４を用いてバンプ９を形成することにより、金の使用量を最小限に抑え、製造コストの低コスト化が可能となる。 FIG. 10 shows a step of forming the gold bump 9 on the IGBT 21. In the forming process, as shown in FIGS. 10A and 10B, the gold wire 4 is ball-bonded to the surface of the IGBT 21 using the tool 50, and then the wire 4 is moved upward as shown in FIG. 10C. Pull it up and cut it into pieces.
Thus, by forming the bumps 9 using the gold wires 4, the amount of gold used can be minimized and the manufacturing cost can be reduced.

実施の形態３．
図１１は、全体が３００で表される、本実施の形態にかかる電力用半導体装置の断面図である。図１１は、図１のＩ−Ｉと同じ方向に見た場合の断面図であり、図１１中、図１、２と同一符号は、同一又は相当箇所を示す。 Embodiment 3 FIG.
FIG. 11 is a cross-sectional view of the power semiconductor device according to the present embodiment, indicated as a whole by 300. 11 is a cross-sectional view when viewed in the same direction as I-I in FIG. 1. In FIG. 11, the same reference numerals as those in FIGS. 1 and 2 indicate the same or corresponding portions.

電力用半導体装置３００では、リード１のダイパッド部１ｂの裏面に、絶縁樹脂シート７に代えて、絶縁板５１が取りつけられる。絶縁板５１は、樹脂モールド６から露出し、その裏面にアルミニウム等からなる外部ヒートシンク６０が取りつけられている。他の構造は、上述の電力用半導体装置１００とほぼ同じである。   In the power semiconductor device 300, an insulating plate 51 is attached to the back surface of the die pad portion 1 b of the lead 1 instead of the insulating resin sheet 7. The insulating plate 51 is exposed from the resin mold 6, and an external heat sink 60 made of aluminum or the like is attached to the back surface of the insulating plate 51. Other structures are almost the same as those of the power semiconductor device 100 described above.

このように、絶縁板５１を、樹脂モールド６の外部に形成することにより、例えば、絶縁板５１とダイパッド部１ｂとの間の絶縁が不充分な場合には、電力用半導体装置３００全体を廃棄する必要はなく、絶縁材５１の交換等で解決できる場合もある。
この結果、電力用半導体装置３００の製造コストを低減することが可能となる In this way, by forming the insulating plate 51 outside the resin mold 6, for example, when the insulation between the insulating plate 51 and the die pad portion 1 b is insufficient, the entire power semiconductor device 300 is discarded. It may not be necessary to solve the problem by replacing the insulating material 51.
As a result, the manufacturing cost of the power semiconductor device 300 can be reduced.

本発明の実施の形態１にかかる電力用半導体装置の斜視図である。1 is a perspective view of a power semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１にかかる電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power concerning Embodiment 1 of this invention. 本発明の実施の形態１にかかる電力用半導体装置の用いるリードフレームである。1 is a lead frame used by a power semiconductor device according to a first embodiment of the present invention. 本発明の実施の形態１にかかる電力用半導体装置のＩＧＢＴである。1 is an IGBT of a power semiconductor device according to a first embodiment of the present invention. 従来のワイヤボンディング工程である。This is a conventional wire bonding process. 本発明の実施の形態１で用いるワイヤボンディング工程である。It is a wire bonding process used in Embodiment 1 of the present invention. 本発明の実施の形態１で用いるバンプ形成工程である。It is a bump formation process used in Embodiment 1 of the present invention. 本発明の実施の形態１で用いるワイヤボンディング工程である。It is a wire bonding process used in Embodiment 1 of the present invention. 本発明の実施の形態２にかかる電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power concerning Embodiment 2 of this invention. 本発明の実施の形態２で用いるバンプ形成工程である。It is a bump formation process used in Embodiment 2 of the present invention. 本発明の実施の形態３にかかる電力用半導体装置の断面図である。It is sectional drawing of the semiconductor device for electric power concerning Embodiment 3 of this invention.

符号の説明Explanation of symbols

１ リード、２ パワーチップ、３ 制御チップ、４、５ ワイヤ、６ モールド樹脂、７ 絶縁樹脂シート、８ 銅箔、９、１１ バンプ、１０ 反応層、２１ ＩＧＢＴ、２２ ＦＷＤｉ、１００ 電力用半導体装置。

1 Lead, 2 Power chip, 3 Control chip, 4, 5 Wire, 6 Mold resin, 7 Insulating resin sheet, 8 Copper foil, 9, 11 Bump, 10 Reaction layer, 21 IGBT, 22 FWDi, 100 Power semiconductor device.

Claims (8)

モールド樹脂から複数のリードが突出した電力用半導体装置であって、
第１ダイパッド部を含む第１リードと、
該第１ダイパッド部の表面に載置されたパワーチップと、
該第１ダイパッド部の裏面に取り付けられた、該モールド樹脂より熱伝導率の大きな樹脂からなる絶縁シートと、
第２ダイパッド部を含む第２リードと、
該第２ダイパッド部上に載置された制御チップと、
該パワーチップと該制御チップとを直接接続する金を主成分とするワイヤと、
該第１リードと該第２リードの端部がそれぞれ突出するように該制御チップと該パワーチップとを埋め込む該モールド樹脂とを含み、
該絶縁シートと該モールド樹脂との界面に、それぞれの材料が混ざった混合層を有することを特徴とする電力用半導体装置。 A power semiconductor device in which a plurality of leads protrudes from a mold resin,
A first lead including a first die pad portion;
A power chip placed on the surface of the first die pad part;
An insulating sheet made of a resin having a higher thermal conductivity than the mold resin, attached to the back surface of the first die pad portion;
A second lead including a second die pad portion;
A control chip mounted on the second die pad portion;
A wire mainly composed of gold that directly connects the power chip and the control chip;
Look including a said mold resin to embed the control chip and the power chip so that the end portion of the first lead and the second lead respectively protrude,
A power semiconductor device comprising a mixed layer in which respective materials are mixed at an interface between the insulating sheet and the mold resin . 上記ワイヤが、金とパラジウムとの合金材料からなることを特徴とする請求項１に記載の電力用半導体装置。 The power semiconductor device according to claim 1, wherein the wire is made of an alloy material of gold and palladium. 上記ワイヤは、その第１端部が上記制御チップにボールボンディングされ、その第２端部が上記パワーチップにステッチボンディングされたことを特徴とする請求項１または２に記載の電力用半導体装置。 3. The power semiconductor device according to claim 1 , wherein a first end portion of the wire is ball-bonded to the control chip and a second end portion is stitch-bonded to the power chip. 更に、上記パワーチップ上にバンプを有し、上記第２端部が該バンプ上にステッチボンディングされたことを特徴とする請求項３に記載の電力用半導体装置。 4. The power semiconductor device according to claim 3 , further comprising a bump on the power chip, wherein the second end portion is stitch-bonded on the bump. 上記バンプは、上記パワーチップの表面に対して垂直方向の断面が、略デルタ形状であることを特徴とする請求項４に記載の電力用半導体装置。 The power semiconductor device according to claim 4 , wherein the bump has a substantially delta cross section in a direction perpendicular to the surface of the power chip. 上記略デルタ形状のバンプがデルタ形状の２辺を形成する２つの斜面を含み、上記第２端部が該斜面上にステッチボンディングされたことを特徴とする請求項５に記載の電力用半導体装置。 6. The power semiconductor device according to claim 5 , wherein the substantially delta-shaped bump includes two inclined surfaces forming two sides of the delta shape, and the second end portion is stitch-bonded on the inclined surface. . 上記第２端部が、上記制御チップからの距離が遠い方の上記斜面上にステッチボンディングされたことを特徴とする請求項６に記載の電力用半導体装置。 The power semiconductor device according to claim 6 , wherein the second end portion is stitch-bonded on the slope that is farther from the control chip. 上記バンプが、上記パワーチップ上にボールボンディングされたワイヤのボールボンディング部からなることを特徴とする請求項４に記載の電力用半導体装置。 5. The power semiconductor device according to claim 4 , wherein the bump comprises a ball bonding portion of a wire that is ball-bonded on the power chip.
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