JP6183226B2 - Method for manufacturing power semiconductor device - Google Patents

Method for manufacturing power semiconductor device Download PDF

Info

Publication number
JP6183226B2
JP6183226B2 JP2014006992A JP2014006992A JP6183226B2 JP 6183226 B2 JP6183226 B2 JP 6183226B2 JP 2014006992 A JP2014006992 A JP 2014006992A JP 2014006992 A JP2014006992 A JP 2014006992A JP 6183226 B2 JP6183226 B2 JP 6183226B2
Authority
JP
Japan
Prior art keywords
die pad
power
semiconductor element
power semiconductor
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2014006992A
Other languages
Japanese (ja)
Other versions
JP2015135907A (en
Inventor
裕史 川島
裕史 川島
中川　信也
信也 中川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2014006992A priority Critical patent/JP6183226B2/en
Priority to CN201510023708.3A priority patent/CN104795337A/en
Publication of JP2015135907A publication Critical patent/JP2015135907A/en
Application granted granted Critical
Publication of JP6183226B2 publication Critical patent/JP6183226B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1305—Bipolar Junction Transistor [BJT]
    • H01L2924/13055—Insulated gate bipolar transistor [IGBT]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Description

本発明は、樹脂で封止した電力用半導体装置の製造方法に関する。 The present invention relates to a method of manufacturing a power semiconductor device sealed with resin.

半導体装置の中でも電力用半導体装置は、鉄道車両、ハイブリッドカー、電気自動車等の車両、家電機器、産業用機械等において、比較的大きな電力を制御、整流するために利用されている。使用時に電力用半導体素子が発熱するため、電力用半導体装置には素子の放熱性が要求される。また数百Ｖ以上の高電圧が印加されることから装置外部との絶縁が必要となる。   Among semiconductor devices, power semiconductor devices are used to control and rectify relatively large power in vehicles such as railway vehicles, hybrid cars, and electric vehicles, home appliances, and industrial machines. Since the power semiconductor element generates heat during use, the power semiconductor device is required to have heat dissipation of the element. Further, since a high voltage of several hundred volts or more is applied, insulation from the outside of the apparatus is necessary.

ここでＩＰＭ（Intelligent Power Module）は電力用半導体素子と制御用半導体素子とが一体となったモジュールである。配線材料にリードフレームを用いる場合、電力用半導体素子と制御用半導体素子は物理的に切り離されたダイパッドに実装され、金属細線などで電気的に接続される。電力用半導体素子は大電流を通電することから、発熱が大きくモジュールとしての放熱性が求められる。放熱構造の一つとして高熱伝導の樹脂を用いて、モジュールの裏面に薄く充填することで放熱する構造がある。この際、電力用半導体素子を搭載するダイパッドの位置を制御用半導体素子を搭載するダイパッドよりも低くすることで熱抵抗を下げる。   Here, the IPM (Intelligent Power Module) is a module in which a power semiconductor element and a control semiconductor element are integrated. When a lead frame is used as the wiring material, the power semiconductor element and the control semiconductor element are mounted on a physically separated die pad and electrically connected by a thin metal wire or the like. Since a power semiconductor element energizes a large current, heat generation is large and heat dissipation as a module is required. As one of the heat dissipation structures, there is a structure that uses a highly heat conductive resin and radiates heat by thinly filling the back surface of the module. At this time, the thermal resistance is lowered by making the position of the die pad on which the power semiconductor element is mounted lower than the die pad on which the control semiconductor element is mounted.

高熱伝導の樹脂は放熱を担うフィラーが高充填され粘度が高い。高粘度樹脂は流動抵抗が高くなるため、たとえば金属細線などはその流動抵抗によって変形してしまうことが想定される。   Highly heat conductive resin is highly filled with fillers for heat dissipation and has high viscosity. Since the high-viscosity resin has a high flow resistance, it is assumed that, for example, a thin metal wire is deformed by the flow resistance.

制御用半導体素子に接続する金属細線の変形を抑えるため、一般的に電力用半導体素子側から制御用半導体素子側に向かって樹脂が流れるようにすることが多い（例えば、特許文献１参照）。樹脂は、電力用半導体素子の電力用ダイパッド上面から制御用半導体素子の制御用ダイパッドに流動する際に、制御用ダイパッド上面、下面両方向に向かって流動する。このとき制御用ダイパッドの下面に向かう樹脂の流れは下向きのベクトルを持つため、金属細線に対して押しつぶすような流動抵抗が働き、金属細線の変形が大きくなり、リードフレームや素子とショートすることで歩留まりが悪くなってしまう。   In order to suppress deformation of the fine metal wire connected to the control semiconductor element, generally, the resin often flows from the power semiconductor element side toward the control semiconductor element side (see, for example, Patent Document 1). When the resin flows from the upper surface of the power die pad of the power semiconductor element to the control die pad of the control semiconductor element, the resin flows in both the upper and lower surfaces of the control die pad. At this time, since the resin flow toward the lower surface of the control die pad has a downward vector, a flow resistance that crushes against the fine metal wire works, the deformation of the fine metal wire becomes large, and the lead frame and the element are short-circuited. Yield will be worse.

これに対して、樹脂注入口のリードフレームを曲げて樹脂の流動性を変えて、予め幾らかの樹脂量を電力用ダイパッド下を経由させて制御用ダイパッド下に充填させることが提案されている（例えば、特許文献１参照）。   On the other hand, it is proposed that the lead frame of the resin injection port is bent to change the fluidity of the resin so that a certain amount of resin is previously filled under the control die pad via the power die pad. (For example, refer to Patent Document 1).

特開２００４−１７２２３９号公報JP 2004-172239 A 特開平１−２６８１５９号公報JP-A-1-268159

しかし、電力用ダイパッドの上下面の流量断面積が異なるため、大部分は電力用ダイパッド上面に向かって流れてしまう。このため、金属細線に対して下向きの流動が発生し、変形量が大きくなってしまうという問題があった。   However, since the flow cross-sectional areas of the upper and lower surfaces of the power die pad are different, most of them flow toward the upper surface of the power die pad. For this reason, there is a problem in that downward flow occurs with respect to the fine metal wire, and the amount of deformation becomes large.

本発明は、上述のような課題を解決するためになされたもので、その目的は金属細線とリードフレームとの接触を起こり難くし、歩留まりを向上することができる電力用半導体装置の製造方法を得るものである。 The present invention has been made to solve the above problems, its object is less likely to occur with contact between the thin metal wire and the lead frame, a method of manufacturing the power semiconductor device capable of improving the yield To get.

本発明に係る電力用半導体装置の製造方法は、電力用ダイパッド上に電力用半導体素子を実装する工程と、前記電力用ダイパッドより高い位置に配置された制御用ダイパッド上に、前記電力用半導体素子を制御する制御用半導体素子を実装する工程と、前記電力用半導体素子と前記制御用半導体素子とを金属細線により電気的に接続する工程と、上金型と下金型により構成されるキャビティ内に、前記電力用ダイパッド、前記制御用ダイパッド、前記電力用半導体素子、前記制御用半導体素子、及び前記金属細線を入れて樹脂で封止する工程とを備え、前記電力用ダイパッドは、前記金属細線の下方に配置され、上方に曲げられた屈曲部を有し、前記電力用ダイパッド側から前記制御用ダイパッド側に向かって前記樹脂を注入し、前記キャビティの底面と前記屈曲部との間にスリーブを配置し、前記スリーブから可動ピンを前記屈曲部に向けて突き出して前記電力用ダイパッドを前記下金型から離して支持した状態で前記キャビティ内に前記樹脂を注入して、前記電力用ダイパッドと前記下金型との間に前記樹脂を充填することを特徴とする。
The method for manufacturing a power semiconductor device according to the present invention includes a step of mounting a power semiconductor element on a power die pad, and the power semiconductor element on a control die pad disposed at a position higher than the power die pad. A step of mounting a control semiconductor element for controlling the power, a step of electrically connecting the power semiconductor element and the control semiconductor element by a fine metal wire, and an inside of a cavity constituted by an upper mold and a lower mold The power die pad, the control die pad, the power semiconductor element, the control semiconductor element, and the step of inserting the metal fine wire and sealing with a resin, and the power die pad includes the metal fine wire. disposed in the lower, has a bent portion which is bent upward, the resin is injected from the power die pad side to said control die pad side, the cavity A sleeve is disposed between the bottom surface of the die and the bent portion, and a movable pin protrudes from the sleeve toward the bent portion so that the power die pad is supported away from the lower mold and is supported in the cavity. The resin is injected, and the resin is filled between the power die pad and the lower mold .

本発明では、電力用ダイパッドは、金属細線の下方に配置され、上方に曲げられた屈曲部を有する。モールド時に電力用ダイパッド側から制御用ダイパッド側に向かって注入した樹脂が屈曲部を通過すると、流れのベクトルが上方に向くことで、金属細線が下から上に向かって抗力を受ける。このため、金属細線とリードフレームとの接触が起こり難くなって歩留まりが向上する。   In the present invention, the power die pad is disposed below the fine metal wire and has a bent portion bent upward. When the resin injected from the power die pad side toward the control die pad side at the time of molding passes through the bent portion, the flow vector is directed upward, so that the fine metal wire receives a drag force from the bottom to the top. For this reason, the contact between the fine metal wire and the lead frame hardly occurs, and the yield is improved.

本発明の実施の形態１に係る電力用半導体装置を示す平面図である。1 is a plan view showing a power semiconductor device according to a first embodiment of the present invention. 図１のＩ−ＩＩに沿った断面図である。It is sectional drawing in alignment with I-II of FIG. 図１の装置内部を示す拡大平面図である。It is an enlarged plan view which shows the inside of the apparatus of FIG. 本発明の実施の形態１に係る電力用半導体装置の屈曲部の先端部と制御用ダイパッドを拡大した断面図である。It is sectional drawing to which the front-end | tip part of the bending part and control die pad of the power semiconductor device which concern on Embodiment 1 of this invention were expanded. 本発明の実施の形態１に係る電力用半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device for electric power which concerns on Embodiment 1 of this invention. 本発明の実施の形態１に係る電力用半導体装置の変形例を示す断面図である。It is sectional drawing which shows the modification of the power semiconductor device which concerns on Embodiment 1 of this invention. 本発明の実施の形態２に係る電力用半導体装置を示す平面図である。It is a top view which shows the semiconductor device for electric power which concerns on Embodiment 2 of this invention. 図７のＩ−ＩＩに沿った断面図である。It is sectional drawing along I-II of FIG. 本発明の実施の形態２に係る電力用半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the semiconductor device for electric power which concerns on Embodiment 2 of this invention. 図９の装置内部を示す拡大平面図である。FIG. 10 is an enlarged plan view showing the inside of the apparatus of FIG. 9. 可動ピンの動きを示す拡大断面図である。It is an expanded sectional view showing movement of a movable pin. 本発明の実施の形態３に係る電力用半導体装置の製造方法を示す断面図である。It is sectional drawing which shows the manufacturing method of the power semiconductor device which concerns on Embodiment 3 of this invention. 本発明の実施の形態４に係る電力用半導体装置の製造方法を示す拡大平面図である。It is an enlarged plan view which shows the manufacturing method of the power semiconductor device which concerns on Embodiment 4 of this invention. 本発明の実施の形態５に係る電力用半導体装置の製造方法を示す拡大平面図である。It is an enlarged plan view which shows the manufacturing method of the power semiconductor device which concerns on Embodiment 5 of this invention.

本発明の実施の形態に係る電力用半導体装置及びその製造方法について図面を参照して説明する。同じ又は対応する構成要素には同じ符号を付し、説明の繰り返しを省略する場合がある。   A power semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to the drawings. The same or corresponding components are denoted by the same reference numerals, and repeated description may be omitted.

実施の形態１．
図１は、本発明の実施の形態１に係る電力用半導体装置を示す平面図である。図２は、図１のＩ−ＩＩに沿った断面図である。図３は図１の装置内部を示す拡大平面図である。 Embodiment 1 FIG.
FIG. 1 is a plan view showing a power semiconductor device according to Embodiment 1 of the present invention. FIG. 2 is a cross-sectional view taken along the line I-II in FIG. FIG. 3 is an enlarged plan view showing the inside of the apparatus of FIG.

リードフレーム１はアウターリードとインナーリードを有し、インナーリードは、アウターリードに接続するリードと、電力用ダイパッド２と、電力用ダイパッド２より高い位置に配置された制御用ダイパッド３とを有する。ＲＣ−ＩＧＢＴ（Reverse Conducting-Insulated Gate Bipolar Transistor）などの電力用半導体素子４が電力用ダイパッド２上にＰｂフリーはんだにより実装されている。Ｐｂフリーはんだに限らず導電性接着剤でもよく、導電性を有した接合材を用いればよい。   The lead frame 1 has an outer lead and an inner lead, and the inner lead has a lead connected to the outer lead, a power die pad 2, and a control die pad 3 disposed at a position higher than the power die pad 2. A power semiconductor element 4 such as RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor) is mounted on the power die pad 2 by Pb-free solder. The adhesive is not limited to Pb-free solder, and a conductive bonding material may be used.

絶縁層と銅箔からなる絶縁シート５が電力用ダイパッド２の裏面に接着されている。電力用半導体素子４を制御する制御用半導体素子６が制御用ダイパッド３上に導電性接着剤により実装されている。   An insulating sheet 5 made of an insulating layer and copper foil is bonded to the back surface of the power die pad 2. A control semiconductor element 6 for controlling the power semiconductor element 4 is mounted on the control die pad 3 with a conductive adhesive.

金属細線７が電力用半導体素子４と制御用半導体素子６とを電気的に接続する。具体的には、電力用半導体素子４の表面にはソース電極とゲート電極が設けられ、ソース電極とリードがＡｌワイヤにより電気的に接続され、ゲート電極と制御用半導体素子６がＡｕワイヤにより電気的に接続され、制御用半導体素子６とリードは全てＡｕワイヤにより電気的に接続されている。なお、ＡｌワイヤはＣｕを含むワイヤでもよく、ＡｕワイヤはＣｕを含むワイヤでもよい。   A thin metal wire 7 electrically connects the power semiconductor element 4 and the control semiconductor element 6. Specifically, a source electrode and a gate electrode are provided on the surface of the power semiconductor element 4, the source electrode and the lead are electrically connected by an Al wire, and the gate electrode and the control semiconductor element 6 are electrically connected by an Au wire. The control semiconductor element 6 and the leads are all electrically connected by Au wires. The Al wire may be a wire containing Cu, and the Au wire may be a wire containing Cu.

樹脂８が電力用ダイパッド２、制御用ダイパッド３、電力用半導体素子４、制御用半導体素子６、及び金属細線７を封止する。樹脂８は、絶縁性と放熱性を両立させるため、エポキシなどの樹脂にＳｉＯ２やＢＮなどの熱伝導フィラーを含有したものである。樹脂８で封止された電力用半導体装置は、裏面では絶縁シート５の銅箔が露出し、両端部からリードフレーム１のアウターリードが突出し、それ以外は樹脂によって封止された構造のＤＩＰタイプのパッケージである。アウターリードのうち片側はパワーアウターリード、もう方側は制御アウターリードとなる。 Resin 8 seals power die pad 2, control die pad 3, power semiconductor element 4, control semiconductor element 6, and metal thin wire 7. The resin 8 contains a heat conductive filler such as SiO 2 or BN in a resin such as epoxy in order to achieve both insulation and heat dissipation. The power semiconductor device sealed with the resin 8 is a DIP type having a structure in which the copper foil of the insulating sheet 5 is exposed on the back surface, the outer leads of the lead frame 1 protrude from both ends, and the rest are sealed with resin. It is a package. One of the outer leads is a power outer lead, and the other is a control outer lead.

電力用半導体素子４と制御用半導体素子６の間において、電力用ダイパッド２は、金属細線７の下方に配置され、上方に曲げられた屈曲部９を有する。電力用ダイパッド２と屈曲部９は制御用ダイパッド３とは物理的に接触していない。   Between the power semiconductor element 4 and the control semiconductor element 6, the power die pad 2 is disposed below the metal thin wire 7 and has a bent portion 9 bent upward. The power die pad 2 and the bent portion 9 are not in physical contact with the control die pad 3.

図４は、本発明の実施の形態１に係る電力用半導体装置の屈曲部の先端部と制御用ダイパッドを拡大した断面図である。屈曲部９の先端部は制御用ダイパッド３の上面よりも低い位置にある。このため、金属細線７とリードフレーム１との接触が起こり難くい。   FIG. 4 is an enlarged cross-sectional view of the tip of the bent portion and the control die pad of the power semiconductor device according to the first embodiment of the present invention. The tip of the bent portion 9 is at a position lower than the upper surface of the control die pad 3. For this reason, the contact between the fine metal wire 7 and the lead frame 1 is unlikely to occur.

続いて、上記の電力用半導体装置の製造方法を説明する。図５は、本発明の実施の形態１に係る電力用半導体装置の製造方法を示す断面図である。まず、電力用ダイパッド２上に電力用半導体素子４をはんだにより実装する。電力用ダイパッド２の裏面に絶縁シート５を接着する。次に、電力用ダイパッド２より高い位置に配置された制御用ダイパッド３上に、電力用半導体素子４を制御する制御用半導体素子６を導電性接着剤により実装する。   Then, the manufacturing method of said power semiconductor device is demonstrated. FIG. 5 is a cross-sectional view showing the method for manufacturing the power semiconductor device according to the first embodiment of the present invention. First, the power semiconductor element 4 is mounted on the power die pad 2 with solder. An insulating sheet 5 is bonded to the back surface of the power die pad 2. Next, the control semiconductor element 6 for controlling the power semiconductor element 4 is mounted on the control die pad 3 disposed at a position higher than the power die pad 2 with a conductive adhesive.

次に、電力用半導体素子４と制御用半導体素子６とを金属細線７により電気的に接続する。具体的にはＡｌワイヤにより電力用半導体素子４とリードを接続し、Ａｕワイヤにより電力用半導体素子４と制御用半導体素子６を接続し、かつ制御用半導体素子６とリードを接続する。   Next, the power semiconductor element 4 and the control semiconductor element 6 are electrically connected by the thin metal wire 7. Specifically, the power semiconductor element 4 and the lead are connected by an Al wire, the power semiconductor element 4 and the control semiconductor element 6 are connected by an Au wire, and the control semiconductor element 6 and the lead are connected.

次に、上金型１０と下金型１１により構成されるキャビティ１２内に、電力用ダイパッド２、制御用ダイパッド３、電力用半導体素子４、制御用半導体素子６、及び金属細線７を入れて型締めする。その後、溶融した熱硬化性の樹脂８をキャビティ１２内に押し出し、熱硬化させて成型して封止する。このトランスファーモールド時に樹脂８によるＡｕワイヤの流れを抑制するため、電力用ダイパッド２側から制御用ダイパッド３側に向かって樹脂８を注入する。キャビティ１２内に樹脂８が行き渡ると溶融した樹脂８を介してキャビティ１２内に静水圧がかかる。静水圧がかかった後、樹脂８が硬化したタイミングで金型を開き成型品を取り出してトランスファーモールドが完了する。このトランスファーモールドによって絶縁シート５と電力用ダイパッド２を押し固めて封止体とする。その後、アウターリードを所定のサイズ、形状に加工して完成となる。   Next, the power die pad 2, the control die pad 3, the power semiconductor element 4, the control semiconductor element 6, and the metal thin wire 7 are placed in the cavity 12 constituted by the upper mold 10 and the lower mold 11. Clamp the mold. Thereafter, the molten thermosetting resin 8 is extruded into the cavity 12, thermoset, molded and sealed. In order to suppress the flow of the Au wire due to the resin 8 during the transfer molding, the resin 8 is injected from the power die pad 2 side toward the control die pad 3 side. When the resin 8 spreads in the cavity 12, a hydrostatic pressure is applied to the cavity 12 through the molten resin 8. After the hydrostatic pressure is applied, the mold is opened at the timing when the resin 8 is cured, and the molded product is taken out to complete the transfer molding. The insulating sheet 5 and the power die pad 2 are pressed and solidified by this transfer mold to form a sealed body. Thereafter, the outer lead is processed into a predetermined size and shape to complete.

本実施の形態では、電力用ダイパッド２は、金属細線７の下方に配置され、上方に曲げられた屈曲部９を有する。モールド時に電力用ダイパッド２側から制御用ダイパッド３側に向かって注入した樹脂８が屈曲部９を通過すると、流れのベクトルが上方に向くことで、金属細線７が下から上に向かって抗力を受ける。このため、樹脂８として高粘度の高熱伝導樹脂を使用しても、金属細線７とリードフレーム１との接触が起こり難くなって歩留まりが向上する。さらに、金属細線７が変形し難くなるので、樹脂８の流速を高めて生産性を高めることができる。また、高熱伝導で高粘度の樹脂８を用いると共に電力用半導体素子４を小型化することで、製品の小型化が可能となる。   In the present embodiment, the power die pad 2 is disposed below the thin metal wire 7 and has a bent portion 9 bent upward. When the resin 8 injected from the power die pad 2 side to the control die pad 3 side at the time of molding passes through the bent portion 9, the flow vector is directed upward, so that the metal thin wire 7 is dragged from bottom to top. receive. For this reason, even if a high-viscosity, high-viscosity resin is used as the resin 8, the contact between the fine metal wires 7 and the lead frame 1 hardly occurs and the yield is improved. Furthermore, since it becomes difficult for the metal fine wire 7 to deform | transform, the flow rate of the resin 8 can be raised and productivity can be improved. Further, by using the resin 8 having high thermal conductivity and high viscosity, and reducing the size of the power semiconductor element 4, it becomes possible to reduce the size of the product.

また、樹脂８で封止する際に、電力用ダイパッド２の裏面に絶縁シート５を接着する。そして、屈曲部９に樹脂８が衝突して電力用ダイパッド２に反作用が働くことで、電力用ダイパッド２と絶縁シート５との接着性が向上し、絶縁シート５を均一な厚みに押し固めることができるため、良好な絶縁性と放熱性が得られ、品質が安定する。   Further, when sealing with the resin 8, the insulating sheet 5 is bonded to the back surface of the power die pad 2. Then, the resin 8 collides with the bent portion 9 and the reaction acts on the power die pad 2, thereby improving the adhesion between the power die pad 2 and the insulating sheet 5 and pressing the insulating sheet 5 to a uniform thickness. Therefore, good insulation and heat dissipation are obtained, and the quality is stable.

図６は、本発明の実施の形態１に係る電力用半導体装置の変形例を示す断面図である。金属細線７により電力用半導体素子４の上面と制御用半導体素子６の上面とを直接接続する。そして、屈曲部９を電力用半導体素子４と制御用半導体素子６との間に配置する。これにより、金属細線７とリードフレーム１との接触が更に起こり難くなる。さらに細い金属細線７を使用することでコストが低減する。   FIG. 6 is a cross-sectional view showing a modification of the power semiconductor device according to the first embodiment of the present invention. The upper surface of the power semiconductor element 4 and the upper surface of the control semiconductor element 6 are directly connected by the metal thin wire 7. The bent portion 9 is disposed between the power semiconductor element 4 and the control semiconductor element 6. As a result, the contact between the fine metal wire 7 and the lead frame 1 is less likely to occur. Further, the cost is reduced by using the fine metal wire 7.

実施の形態２．
図７は、本発明の実施の形態２に係る電力用半導体装置を示す平面図である。図８は、図７のＩ−ＩＩに沿った断面図である。実施の形態１のような絶縁シート５が無く、代わりに電力用ダイパッド２の下方に樹脂８が充填されている。屈曲部９の下方において樹脂８の底面に窪み１３が設けられている。その他の構成は実施の形態１と同様である。 Embodiment 2. FIG.
FIG. 7 is a plan view showing a power semiconductor device according to the second embodiment of the present invention. FIG. 8 is a cross-sectional view taken along the line I-II in FIG. There is no insulating sheet 5 as in the first embodiment, and instead a resin 8 is filled below the power die pad 2. A depression 13 is provided on the bottom surface of the resin 8 below the bent portion 9. Other configurations are the same as those of the first embodiment.

続いて、上記の電力用半導体装置の製造方法を説明する。図９は、本発明の実施の形態２に係る電力用半導体装置の製造方法を示す断面図である。図１０は図９の装置内部を示す拡大平面図である。図１１は可動ピンの動きを示す拡大断面図である。   Then, the manufacturing method of said power semiconductor device is demonstrated. FIG. 9 is a cross-sectional view showing the method for manufacturing the power semiconductor device according to the second embodiment of the present invention. FIG. 10 is an enlarged plan view showing the inside of the apparatus of FIG. FIG. 11 is an enlarged cross-sectional view showing the movement of the movable pin.

キャビティ１２の底面と屈曲部９との間にスリーブ１４を配置する。このスリーブ１４から可動ピン１５を屈曲部９に向けて突き出して電力用ダイパッド２を下金型１１から離して支持した状態でキャビティ１２内に樹脂８を注入して、電力用ダイパッド２と下金型１１との間に樹脂８を充填する。   A sleeve 14 is disposed between the bottom surface of the cavity 12 and the bent portion 9. With the movable pin 15 projecting from the sleeve 14 toward the bent portion 9 and the power die pad 2 is supported away from the lower mold 11, the resin 8 is injected into the cavity 12, and the power die pad 2 and the lower metal plate are injected. Resin 8 is filled between mold 11.

また、屈曲部９の下方に配置したスリーブ１４から可動ピン１５を屈曲部９に向けて突き出す。これにより、モールド時に屈曲部９にぶつかった樹脂８によって電力用ダイパッド２が下に押し下げられても電力用ダイパッド２を下金型１１から離して支持することができる。従って、電力用ダイパッド２と下金型１１の間隔を維持できるため、樹脂８が電力用ダイパッド２の下方に十分に行き渡って絶縁性を確保することができる。   Further, the movable pin 15 protrudes toward the bent portion 9 from the sleeve 14 disposed below the bent portion 9. Thereby, even if the power die pad 2 is pushed down by the resin 8 hitting the bent portion 9 at the time of molding, the power die pad 2 can be supported away from the lower mold 11. Therefore, since the distance between the power die pad 2 and the lower mold 11 can be maintained, the resin 8 can sufficiently spread below the power die pad 2 to ensure insulation.

そして、樹脂８を電力用ダイパッド２の下方まで充填して静水圧がかかる直前に、可動ピン１５を下側に可動させて引き抜く。静水圧がかかった後、樹脂８が硬化したタイミングで金型を開き成型品を取り出してトランスファーモールドが完了する。この時に電力用半導体装置の裏面にスリーブ１４が転写されて窪み１３が残る。なお、スリーブ１４は可動ピン１５を引き抜く際に発生するバリを防ぐために設置している。   Then, immediately before the resin 8 is filled below the power die pad 2 and the hydrostatic pressure is applied, the movable pin 15 is moved downward and pulled out. After the hydrostatic pressure is applied, the mold is opened at the timing when the resin 8 is cured, and the molded product is taken out to complete the transfer molding. At this time, the sleeve 14 is transferred to the back surface of the power semiconductor device, and the recess 13 remains. The sleeve 14 is installed to prevent burrs that occur when the movable pin 15 is pulled out.

また、樹脂８を電力用ダイパッド２の下方に充填させる際に、電力用ダイパッド２が上方にずれることが想定される。これを防ぐために従来は上金型１０にも可動ピンを設けて電力用ダイパッド２を上からも押さえつけていた。これに対して本実施の形態では、屈曲部９に樹脂８が衝突すると電力用ダイパッド２は反作用により下方に力を受けるため、電力用ダイパッド２が上方にずれるのを防ぐことができる。従って、上金型１０に可動ピン等を設ける必要が無いため、上金型１０のメンテナンス性が向上し、コストを削減することができる。   Further, when the resin 8 is filled below the power die pad 2, it is assumed that the power die pad 2 is displaced upward. In order to prevent this, conventionally, the upper die 10 is also provided with a movable pin to press the power die pad 2 from above. On the other hand, in the present embodiment, when the resin 8 collides with the bent portion 9, the power die pad 2 receives a downward force due to the reaction, so that the power die pad 2 can be prevented from shifting upward. Accordingly, since there is no need to provide a movable pin or the like on the upper mold 10, the maintainability of the upper mold 10 is improved and the cost can be reduced.

また、屈曲部９が無い場合、電力用ダイパッド２と下金型１１との間に設けたスリーブ１４の高さが電力用ダイパッド２下の樹脂８の厚みの制約となる。しかし、屈曲部９の下方にスリーブ１４を配置することで、電力用ダイパッド２下の樹脂８を薄くして熱抵抗を低減することができる。スリーブ１４の高さは少なくとも０．１ｍｍ以上必要であるため、電力用ダイパッド２下の樹脂８の厚みを少なくとも０．１ｍｍ以上薄くすることができる。従って、放熱性が良好となるため、製品の寿命が向上し、電力用半導体素子４の小型化に伴う電力用半導体装置の小型化が可能となる。   Further, when there is no bent portion 9, the height of the sleeve 14 provided between the power die pad 2 and the lower mold 11 becomes a restriction on the thickness of the resin 8 below the power die pad 2. However, by disposing the sleeve 14 below the bent portion 9, the resin 8 under the power die pad 2 can be thinned to reduce the thermal resistance. Since the height of the sleeve 14 is required to be at least 0.1 mm or more, the thickness of the resin 8 under the power die pad 2 can be reduced by at least 0.1 mm or more. Accordingly, the heat dissipation is improved, the life of the product is improved, and the power semiconductor device can be downsized along with the downsizing of the power semiconductor element 4.

実施の形態３．
図１２は、本発明の実施の形態３に係る電力用半導体装置の製造方法を示す断面図である。屈曲部９は２個の曲げ部分を有し、屈曲部９の先端部がキャビティ１２の底面に平行である。この屈曲部９の先端部に可動ピン１５が接触する。これにより、可動ピン１５の屈曲部９に対する接触が点から面になるため、電力用ダイパッド２の固定位置の厚み方向のずれが生じ難くなるため、電力用ダイパッド２下の樹脂８の厚みばらつきを減らすことができる。 Embodiment 3 FIG.
FIG. 12 is a cross-sectional view illustrating the method for manufacturing the power semiconductor device according to the third embodiment of the present invention. The bent portion 9 has two bent portions, and the distal end portion of the bent portion 9 is parallel to the bottom surface of the cavity 12. The movable pin 15 comes into contact with the distal end portion of the bent portion 9. Accordingly, since the contact of the movable pin 15 with respect to the bent portion 9 is point-to-surface, the displacement of the fixing position of the power die pad 2 in the thickness direction is less likely to occur. Can be reduced.

実施の形態４．
図１３は、本発明の実施の形態４に係る電力用半導体装置の製造方法を示す拡大平面図である。２個の可動ピン１５により電力用ダイパッド２を支持する。このように電力用ダイパッド２を上金型１０と下金型１１を含めて３点で支持することにより、平面方向に安定して電力用ダイパッド２を固定できるため、電力用ダイパッド２下の樹脂８の厚みばらつきを減らすことができる。 Embodiment 4 FIG.
FIG. 13 is an enlarged plan view showing the method for manufacturing the power semiconductor device according to the fourth embodiment of the present invention. The power die pad 2 is supported by the two movable pins 15. Since the power die pad 2 is supported at three points including the upper die 10 and the lower die 11 in this manner, the power die pad 2 can be stably fixed in the plane direction. 8 thickness variation can be reduced.

実施の形態５．
図１４は、本発明の実施の形態５に係る電力用半導体装置の製造方法を示す拡大平面図である。可動ピン１５は、複数の電力用ダイパッド２の隣接する２つにまたがって支持する。これにより、少ない可動ピン１５で安定した固定が可能となり、金型のメンテナンス性が向上する。 Embodiment 5. FIG.
FIG. 14 is an enlarged plan view showing the method for manufacturing the power semiconductor device according to the fifth embodiment of the present invention. The movable pin 15 is supported across two adjacent power die pads 2. As a result, stable fixing with a small number of movable pins 15 is possible, and the maintainability of the mold is improved.

なお、電力用半導体素子４は、珪素によって形成されたものに限らず、珪素に比べてバンドギャップが大きいワイドバンドギャップ半導体によって形成されたものでもよい。ワイドバンドギャップ半導体は、例えば、炭化珪素、窒化ガリウム系材料、又はダイヤモンドである。このようなワイドバンドギャップ半導体によって形成された電力用半導体素子４は、耐電圧性や許容電流密度が高いため、小型化できる。この小型化された素子を用いることで、この素子を組み込んだ電力用半導体装置も小型化できる。また、素子の耐熱性が高いため、ヒートシンクの放熱フィンを小型化でき、水冷部を空冷化できるので、電力用半導体装置を更に小型化できる。また、素子の電力損失が低く高効率であるため、電力用半導体装置を高効率化できる。   The power semiconductor element 4 is not limited to being formed of silicon, but may be formed of a wide band gap semiconductor having a larger band gap than silicon. The wide band gap semiconductor is, for example, silicon carbide, a gallium nitride-based material, or diamond. Since the power semiconductor element 4 formed of such a wide band gap semiconductor has high voltage resistance and allowable current density, it can be miniaturized. By using this miniaturized element, the power semiconductor device incorporating this element can also be miniaturized. Further, since the heat resistance of the element is high, the heat dissipating fins of the heat sink can be miniaturized and the water cooling part can be air cooled, so that the power semiconductor device can be further miniaturized. In addition, since the power loss of the element is low and the efficiency is high, the power semiconductor device can be highly efficient.

１ リードフレーム、２ 電力用ダイパッド、３ 制御用ダイパッド、４ 電力用半導体素子、５ 絶縁シート、６ 制御用半導体素子、７ 金属細線、８ 樹脂、９ 屈曲部、１０ 上金型、１１ 下金型、１２ キャビティ、１４ スリーブ、１５ 可動ピン DESCRIPTION OF SYMBOLS 1 Lead frame, 2 Power die pad, 3 Control die pad, 4 Power semiconductor element, 5 Insulation sheet, 6 Control semiconductor element, 7 Metal thin wire, 8 Resin, 9 Bending part, 10 Upper mold, 11 Lower mold , 12 cavities, 14 sleeves, 15 movable pins

Claims (6)

電力用ダイパッド上に電力用半導体素子を実装する工程と、
前記電力用ダイパッドより高い位置に配置された制御用ダイパッド上に、前記電力用半導体素子を制御する制御用半導体素子を実装する工程と、
前記電力用半導体素子と前記制御用半導体素子とを金属細線により電気的に接続する工程と、
上金型と下金型により構成されるキャビティ内に、前記電力用ダイパッド、前記制御用ダイパッド、前記電力用半導体素子、前記制御用半導体素子、及び前記金属細線を入れて樹脂で封止する工程とを備え、
前記電力用ダイパッドは、前記金属細線の下方に配置され、上方に曲げられた屈曲部を有し、
前記電力用ダイパッド側から前記制御用ダイパッド側に向かって前記樹脂を注入し、
前記キャビティの底面と前記屈曲部との間にスリーブを配置し、
前記スリーブから可動ピンを前記屈曲部に向けて突き出して前記電力用ダイパッドを前記下金型から離して支持した状態で前記キャビティ内に前記樹脂を注入して、前記電力用ダイパッドと前記下金型との間に前記樹脂を充填することを特徴とする電力用半導体装置の製造方法。 Mounting a power semiconductor element on the power die pad;
Mounting a control semiconductor element for controlling the power semiconductor element on a control die pad disposed at a position higher than the power die pad;
Electrically connecting the power semiconductor element and the control semiconductor element with a thin metal wire;
A process of placing the power die pad, the control die pad, the power semiconductor element, the control semiconductor element, and the metal fine wire in a cavity constituted by an upper mold and a lower mold and sealing with resin And
The power die pad is disposed below the thin metal wire and has a bent portion bent upward,
Injecting the resin from the power die pad side toward the control die pad side ,
A sleeve is disposed between the bottom surface of the cavity and the bent portion;
The power die pad and the lower mold are injected by injecting the resin into the cavity with the movable pin protruding from the sleeve toward the bent portion and supporting the power die pad away from the lower mold. A method of manufacturing a power semiconductor device , wherein the resin is filled in between . 前記屈曲部は２個の曲げ部分を有し、前記屈曲部の先端部が前記キャビティの底面に平行であり、
前記屈曲部の前記先端部に前記可動ピンが接触することを特徴とする請求項１に記載の電力用半導体装置の製造方法。 The bent portion has two bent portions, and a tip portion of the bent portion is parallel to the bottom surface of the cavity,
Method of manufacturing a power semiconductor device according to claim 1, characterized in that said movable pin is in contact with the tip portion of the bent portion. ２個以上の前記可動ピンにより前記電力用ダイパッドを支持することを特徴とする請求項１又は２に記載の電力用半導体装置の製造方法。 Method of manufacturing a power semiconductor device according to claim 1 or 2 by two or more of said movable pin, characterized in that for supporting the die pad the power. 前記電力用ダイパッドは複数のダイパッドを有し、
前記可動ピンは、前記複数のダイパッドの隣接する２つにまたがって支持することを特徴とする請求項１〜３の何れか１項に記載の電力用半導体装置の製造方法。 The power die pad has a plurality of die pads,
The method of manufacturing a power semiconductor device according to any one of claims 1 to 3 , wherein the movable pin is supported across two adjacent die pads. 前記屈曲部の先端部は前記制御用ダイパッドの上面よりも低い位置にあることを特徴とする請求項１〜４の何れか１項に記載の電力用半導体装置の製造方法。 Method of manufacturing a power semiconductor device according to any one of claims 1-4 tip of the bent portion, characterized in that in a position lower than the upper surface of said control die pad. 前記金属細線により前記電力用半導体素子の上面と前記制御用半導体素子の上面とを直接接続し、
前記屈曲部を前記電力用半導体素子と前記制御用半導体素子との間に配置することを特徴とする請求項１〜５の何れか１項に記載の電力用半導体装置の製造方法。 The upper surface of the power semiconductor element and the upper surface of the control semiconductor element are directly connected by the metal thin wire,
Method of manufacturing a power semiconductor device according to any one of claim 1 to 5, characterized in that placing the bent portion between said power semiconductor element and the controlled semiconductor device.
JP2014006992A 2014-01-17 2014-01-17 Method for manufacturing power semiconductor device Active JP6183226B2 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2014006992A JP6183226B2 (en) 2014-01-17 2014-01-17 Method for manufacturing power semiconductor device
CN201510023708.3A CN104795337A (en) 2014-01-17 2015-01-16 Electric power semiconductor device and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2014006992A JP6183226B2 (en) 2014-01-17 2014-01-17 Method for manufacturing power semiconductor device

Publications (2)

Publication Number Publication Date
JP2015135907A JP2015135907A (en) 2015-07-27
JP6183226B2 true JP6183226B2 (en) 2017-08-23

Family

ID=53560054

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2014006992A Active JP6183226B2 (en) 2014-01-17 2014-01-17 Method for manufacturing power semiconductor device

Country Status (2)

Country Link
JP (1) JP6183226B2 (en)
CN (1) CN104795337A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6416055B2 (en) * 2015-08-24 2018-10-31 三菱電機株式会社 Semiconductor device
US11107746B2 (en) * 2016-02-09 2021-08-31 Mitsubishi Electric Corporation Power semiconductor apparatus and manufacturing method therefor
JP6598739B2 (en) 2016-07-14 2019-10-30 三菱電機株式会社 Semiconductor module
KR102303894B1 (en) * 2017-02-27 2021-09-17 미쓰비시덴키 가부시키가이샤 Semiconductor device, manufacturing method of semiconductor device
CN109473414B (en) * 2017-09-08 2022-11-11 万国半导体(开曼)股份有限公司 Molded smart power module and method of making the same
WO2019216160A1 (en) * 2018-05-09 2019-11-14 三菱電機株式会社 Power semiconductor device, method for manufacturing same, and power conversion device
CN115966542B (en) * 2023-01-31 2023-10-13 海信家电集团股份有限公司 Power module and electronic equipment with same
CN116666341B (en) * 2023-04-28 2024-02-20 海信家电集团股份有限公司 Intelligent power module and electronic equipment with same

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6466959A (en) * 1987-09-07 1989-03-13 Nec Corp Resin seal type semiconductor device
JPH05278077A (en) * 1992-04-02 1993-10-26 Fuji Electric Co Ltd Mold for transfer molding
JPH05299454A (en) * 1992-04-24 1993-11-12 Matsushita Electron Corp Semiconductor manufacture device
US5750423A (en) * 1995-08-25 1998-05-12 Dai-Ichi Seiko Co., Ltd. Method for encapsulation of semiconductor devices with resin and leadframe therefor
JP4073559B2 (en) * 1998-10-30 2008-04-09 三菱電機株式会社 Semiconductor device
JP2003142510A (en) * 2001-11-02 2003-05-16 Mitsubishi Electric Corp Method of manufacturing semiconductor device
JP4146785B2 (en) * 2003-11-19 2008-09-10 三菱電機株式会社 Power semiconductor device
JP4469654B2 (en) * 2004-05-13 2010-05-26 パナソニック株式会社 Semiconductor device and manufacturing method of semiconductor device
JP4422094B2 (en) * 2005-12-12 2010-02-24 三菱電機株式会社 Semiconductor device
JP5672456B2 (en) * 2011-04-27 2015-02-18 パナソニックＩｐマネジメント株式会社 Manufacturing method of resin-encapsulated molded product
JP5518000B2 (en) * 2011-06-10 2014-06-11 三菱電機株式会社 Power module and manufacturing method thereof

Also Published As

Publication number Publication date
JP2015135907A (en) 2015-07-27
CN104795337A (en) 2015-07-22

Similar Documents

Publication Publication Date Title
JP6183226B2 (en) Method for manufacturing power semiconductor device
JP6195019B2 (en) Power semiconductor device and manufacturing method thereof
JP6115738B2 (en) Semiconductor device and manufacturing method thereof
JP6619356B2 (en) Power semiconductor device and manufacturing method thereof
US10312178B2 (en) Semiconductor device
CN108604578B (en) Power semiconductor device and method for manufacturing the same
US10262912B2 (en) Semiconductor device
US10043680B2 (en) Method for manufacturing semiconductor device
JP4463146B2 (en) Manufacturing method of semiconductor device
JP4039298B2 (en) Resin-sealed semiconductor device, manufacturing method thereof, and mold
US11152275B2 (en) Semiconductor device and method for manufacturing semiconductor device
US20220293434A1 (en) Semiconductor manufacturing apparatus and method of manufacturing semiconductor device using the same, and semiconductor device
JP2018029149A (en) Power semiconductor device and manufacturing method thereof
JPWO2020049672A1 (en) Semiconductor device
JP2012174748A (en) Semiconductor module structure and manufacturing method of the same
JP2012174747A (en) Power semiconductor module structure and manufacturing method of the same
JP2014116366A (en) Semiconductor device and manufacturing method of the same

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20160426

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20170213

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20170228

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170314

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20170627

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20170710

R150 Certificate of patent or registration of utility model

Ref document number: 6183226

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250