JP2014041876A - Power semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device which reduces stress of a semiconductor element and inhibits the deterioration of heat radiation performance.SOLUTION: A power semiconductor device includes: an IGBT1A that is a semiconductor element; a circuit board 3 which faces a first main surface of the IGBT1A and is electrically connected with the first main surface of the IGBT1A; a low thermal expansion material 6A which is disposed at a region including a part of a space where the first main surface of the IGBT1A and a main surface of the circuit board 3 face each other, has a thermal expansion coefficient lower than that of the circuit board 3, and achieves high rigidity; and solder 4 which forms joining between the first main surface of the IGBT1A and the main surface of the circuit board 3, between the first main surface of the IGBT1A and a first main surface of the low thermal expansion material 6A, and between a second main surface of the low thermal expansion material 6A and the main surface of the circuit board 3 and is a joining material having heat conductivity higher than that of the low thermal expansion material 6A.

Description

  The present invention relates to a power semiconductor device that constitutes an inverter circuit or the like by combining semiconductor elements.

  In general, in a power semiconductor device, a semiconductor element is mounted on a metal-based circuit board such as aluminum, which has excellent heat dissipation, and is wired from above the semiconductor element with, for example, aluminum wire. Part. In recent years, SiC (silicon carbide) semiconductors and the like have been developed for power semiconductor devices, and there is an increasing demand for use in high-temperature environments and high-temperature operation. On the other hand, with regard to semiconductor elements, thinning for reduction of material costs and performance improvement and increase in area for handling large currents are progressing, but silicon (Si), which is a general material for semiconductor elements, is being used. Has a lower coefficient of thermal expansion than aluminum, which is a material for metal-based circuit boards. As a result, the stress applied to the semiconductor element increases due to the difference in thermal deformation between the semiconductor element and the circuit board after the semiconductor element is mounted or in operation, and problems such as deterioration of the characteristics of the semiconductor element and destruction of the element have become apparent. Yes. Therefore, in the conventional power semiconductor device, by providing a low thermal expansion material having a lower coefficient of thermal expansion than the circuit board as a stress buffering plate between the semiconductor element and the circuit board, and bonding with a bonding material such as solder, The stress due to the difference in thermal expansion applied to the semiconductor element is reduced, and the deterioration and destruction of the characteristics of the semiconductor element are suppressed (for example, Patent Document 1).

JP 2006-190850 A

  In such a power semiconductor device, it is common to use a member such as Invar or Kovar that has a lower coefficient of thermal expansion than a circuit board and is relatively inexpensive as a low thermal expansion material. However, since the heat generated in the semiconductor element is radiated from the circuit board side with excellent heat dissipation, heat is radiated through the low thermal expansion material, but the thermal conductivity of Invar, Kovar, etc. is higher than that of the circuit board. Since it is low, there was a problem that heat dissipation was reduced. In addition, it is conceivable to maintain heat dissipation by using molybdenum (Mo) or tungsten (W) having a low coefficient of thermal expansion and high thermal conductivity as a low thermal expansion material. A new problem of increasing the cost of the semiconductor device for use occurs.

  The present invention has been made to solve the above-described problems, and provides a power semiconductor device capable of reducing the stress of a semiconductor element and suppressing a decrease in heat dissipation while suppressing an increase in cost. The purpose is to provide.

  A power semiconductor device according to the present invention includes a semiconductor element, a circuit board facing the first main surface of the semiconductor element and electrically connected to the first main surface of the semiconductor element, and a first of the semiconductor element A low thermal expansion material which is disposed in a region including a part of a space where the main surface and the main surface of the circuit board face each other and has a lower coefficient of thermal expansion and higher rigidity than the circuit board; and a first main surface of the semiconductor element; The main surface of the circuit board, the first main surface of the semiconductor element and the first main surface of the low thermal expansion material, and the second main surface of the low thermal expansion material and the main surface of the circuit board are each in at least a part of the region. And a bonding material having a thermal conductivity higher than that of the low thermal expansion material.

  According to the power semiconductor device of the present invention, the low thermal expansion material constrains thermal deformation of the circuit board to reduce the stress applied to the semiconductor element, and the low thermal expansion material is placed between the semiconductor element and the circuit board. Since it is provided only at the portion, it is possible to suppress a decrease in heat dissipation. Moreover, since a heat dissipation fall can be suppressed without using Mo and W with a low thermal expansion coefficient and high thermal conductivity, the increase in cost can be suppressed.

1 is a perspective view of a power semiconductor device according to a first embodiment of the present invention. It is a partial top view of the semiconductor element junction part concerning Embodiment 1 of this invention. It is sectional drawing of the semiconductor element junction part concerning Embodiment 1 of this invention. It is a top view of the low thermal expansion frame concerning Embodiment 1 of this invention. It is a partial top view of the semiconductor element junction part concerning Embodiment 2 of this invention. It is sectional drawing of the semiconductor element junction part concerning Embodiment 2 of this invention. It is a top view of the low thermal expansion frame concerning Embodiment 2 of this invention. It is a partial top view of the semiconductor element junction part concerning Embodiment 3 of this invention. It is a partial top view of the semiconductor element concerning Embodiment 3 of this invention. It is a partial top view of the low thermal expansion material concerning Embodiment 3 of this invention. It is a partial top view of the low thermal expansion material concerning Embodiment 3 of this invention. It is a partial top view of the semiconductor element concerning Embodiment 3 of this invention. It is a partial top view of the low thermal expansion material concerning Embodiment 3 of this invention.

Embodiment 1 FIG.
First, the configuration of the power semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. In the drawings, the same or corresponding parts will be described with the same reference numerals.

  FIG. 1 is a perspective view showing a portion for mounting a semiconductor element of the power semiconductor device 100 according to the first embodiment. FIG. 2 is a partial top view of the power semiconductor device 100 according to the first embodiment. 3 is a cross-sectional view taken along the line AA in FIG. 1, and FIG. 4 is a top view of the low thermal expansion material 6A according to the first embodiment. In addition, the broken line shown in FIG. 2 has illustrated the low thermal expansion material 6A which exists in the back side of IGBT1A.

  In FIG. 1, two sets of IGBTs (Insulated Gate Bipolar Transistors) 1 </ b> A and FWDs (Free Wheeling Diodes) 2 connected in parallel are mounted on the power semiconductor device 100. Although a total of four semiconductor elements are mounted in FIG. 1, it goes without saying that even if the number is three or less or five or more, the same effect can be obtained if one or more semiconductor elements are provided. . Hereinafter, a portion where IGBT 1A is mounted as a semiconductor element in power semiconductor device 100 will be described. In this embodiment, IGBT 1A and FWD 2 made of Si are used as semiconductor elements, but the present invention is not limited to this, and other semiconductor elements such as MOSFET (Metal Oxide Field Field Transistor), silicon car A semiconductor element made of another material such as a bite (SiC) may be used.

  1 and 2, IGBT 1A is a semiconductor element with □ 15 mm and a thickness of 60 μm, and the back surface, which is the first main surface of IGBT 1A, is conductive tin (Sn) -silver (Ag) -copper (Cu). It is mounted on the circuit board 3 through a part of the low thermal expansion material 6A arranged at the position shown by the broken line by the solder 4 of the system, and the aluminum wire 5 is arranged on the surface which is the second main surface of the IGBT 1A Is done. Here, the IGBT 1A which is a semiconductor element is a vertical semiconductor, and an emitter electrode and a collector electrode (not shown) are provided on the front surface and the back surface, respectively, the front electrode is an aluminum wire 5, and the back electrode is a circuit of the circuit board 3. Each is electrically connected to the pattern 3C. In addition to the emitter electrode, a gate electrode 8 is provided on the surface of the IGBT 1A, and is connected to a control circuit (not shown) via a gate wiring 9. The other end of the circuit pattern 3C and the aluminum wire 5 is connected to an external terminal (not shown) or the like. When the IGBT 1A is energized in the thickness direction of the chip, the power semiconductor device 100 is a part of an inverter circuit or the like. Configure. The aluminum wire 5 is made of Al having a diameter of 400 μm and is connected to an electrode formed on the surface of the IGBT 1A by ultrasonic bonding, for example.

  In FIG. 3, the circuit board 3 is composed of a base 3A, an insulating layer 3B, and a circuit pattern 3C, and a circuit pattern 3C is provided on the surface that is the main surface of the circuit board 3 via the insulating layer 3B. It is a substrate. The base 3A is made of 2 mmt of aluminum (Al), the insulating layer 3B is made of a 150 μm thick cured epoxy resin filled with a high thermal conductive filler such as alumina (Al 2 O 3), and the circuit pattern 3C is made of 105 μm thick Cu. And the back surface of the circuit board 3 is attached to the heat sink which is not shown in figure through thermal radiation grease or a thermal radiation sheet.

  Here, in FIG. 3, the low thermal expansion material 6A is installed between the IGBT 1A and the circuit pattern 3C. The low thermal expansion material 6A is made of an invar that is an iron (Fe) -nickel (Ni) alloy, has a frame shape with an outer circumference □ 15 mm, an inner circumference □ 13 mm, and a thickness 0.3 mm, and a width of 2 mm from the outer periphery of the IGBT 1A. It is installed along. The low thermal expansion material 6A is Ni-plated on the entire surface for soldering, and is simultaneously joined to the circuit pattern 3C by the conductive solder 4 together with the IGBT 1A. More specifically, a part of the back surface of the IGBT 1A and the main surface of the circuit board, a remaining portion of the back surface of the IGBT 1A (a portion other than a part of the back surface), the surface that is the first main surface of the low thermal expansion material 6A, and the circuit The main surface of the substrate and the back surface, which is the second main surface of the low thermal expansion material 6 </ b> A, are joined together by the solder 4. At that time, the thickness of the solder 4 between the IGBT 1A and the low thermal expansion frame 6A and the thickness of the solder 4 between the circuit pattern 3C and the low thermal expansion frame 6A are about 50 μm, respectively.

  In the present embodiment, the low thermal expansion material 6A having a square shape is used. However, as shown in FIG. 4A and FIG. 4B, the outer periphery is taken into consideration in consideration of workability and solderability. Low thermal expansion material 6B or 6C having chamfered or rounded corners or inner peripheral angles may be used. In order to improve the effect of reducing stress, it is effective to make the frame of the low thermal expansion material 6A thick and wide. However, it is possible to make a selection in consideration of element characteristics and assembling property. is there.

  Next, the operation and effect of the power semiconductor device 100 according to the first embodiment of the present invention will be described in comparison with a conventional power semiconductor device.

  First, as a conventional power semiconductor device, a case where IGBTs and FWDs which are semiconductor elements are joined by solder without using a low thermal expansion material will be described. When a semiconductor element and a circuit board are soldered, the semiconductor element and the circuit board are joined at the melting point of the solder. Therefore, in a state below the melting point of the solder, the semiconductor element and the circuit board are compressed and thermally deformed based on the melting point of the solder. To do. Here, the coefficient of thermal expansion (2.5 ppm / K) of Si, which is the main material of semiconductor elements such as IGBT and FWD, is the coefficient of thermal expansion (22 ppm / K) of the solder directly bonded to the semiconductor element. It is smaller than the thermal expansion coefficient (23 ppm / K) of Al, which is the main material. Therefore, in a state below the melting point of the solder, a compressive stress is generated in the semiconductor element due to a thermal deformation difference between the semiconductor element and the circuit board. In particular, as shown in this embodiment, when the thickness of the semiconductor element is reduced and the rigidity is lowered, the compressive stress applied to the semiconductor element is increased, and the in-plane stress difference is increased, thereby increasing the switching loss and the breakdown voltage of the element. There has been a problem that the electrical characteristics of the element, such as a decrease, are deteriorated, and the characteristics inherent to the semiconductor element cannot be fully exhibited.

  Next, the power semiconductor device 100 according to the present embodiment will be described. In the present embodiment, the semiconductor elements IGBT1A and FWD2 are joined to the circuit board 3 through a part of the frame-shaped low thermal expansion material 6A. Here, the thermal expansion coefficient of the low thermal expansion material 6A, that is, the thermal expansion coefficient of Invar (1.2 ppm / K) is smaller than the thermal expansion coefficient (23 ppm / K) of Al, which is the main material of the circuit board 3, and The rigidity of the low thermal expansion material 6A made of Invar is higher than the rigidity of the circuit board 3 made mainly of Al. As a result, since the low thermal expansion material 6A restrains thermal deformation of the circuit board 3 after soldering, the compressive stress applied to the IGBTs 1A and FWD2 which are semiconductor elements is reduced, so that the electrical characteristics of the semiconductor elements deteriorate. Is suppressed.

  In the present embodiment, the low thermal expansion material 6A is interposed between a part of the semiconductor element and the circuit board 3, but the amount of heat generated in the semiconductor element is dissipated through the circuit board 3 on the back side. The thermal conductivity (13 W / mK) of the invar which is the low thermal expansion material 6A is the thermal conductivity of the solder 4 (60 W / mK) or the thermal conductivity of Cu which is the material of the circuit board (398 W / mK) or Al. Since it is low compared with the thermal conductivity (237 W / mK), there is a concern about a decrease in heat dissipation. However, in this embodiment, since the low thermal expansion material 6A is provided only on a part of the back surface side of the semiconductor element, a decrease in heat dissipation due to the provision of the low thermal expansion material 6A is suppressed. Therefore, it is possible to suppress a decrease in heat dissipation without using an expensive material such as Mo or W having a low coefficient of thermal expansion and a high thermal conductivity.

  In particular, the outer peripheral portion having a width of 0.5 mm to 1.0 mm from the outer periphery of the IGBT 1A is a portion of the termination structure provided to ensure the withstand voltage of the upper and lower electrodes of the IGBT 1A, and is terminated on the front surface or the back surface of the IGBT 1A. The region of the structure portion has a smaller amount of heat generation per unit area (hereinafter simply referred to as “heat generation amount”) than other regions. Therefore, the first region where the surface of the low thermal expansion material 6A is joined to the back surface of the IGBT 1A in correspondence with the heat generation distribution on the back surface of the IGBT 1A by arranging the low thermal expansion material 6A along the termination structure with a small amount of heat generation. Since the main surface of the low thermal expansion material 6A can be bonded to the back surface of the IGBT 1A so that the amount of generated heat is smaller than the heat generation amount of the second region to which the main surface of the circuit board 3 is bonded, the power semiconductor It is possible to more effectively suppress a decrease in heat dissipation of the device 100 as a whole.

  In the present embodiment, Al is often used for the metal base substrate for the base 3A. However, Al2O3 or aluminum nitride (AlN) generally used for power modules is used, and a ceramic substrate is used instead of the metal base substrate. It is good also as doing. Furthermore, in the present embodiment, Cu is used for the circuit pattern 3C, but it is also possible to apply a Cu alloy-based lead frame or a Cu block as an electrode.

  Moreover, in this Embodiment, although the outer periphery of semiconductor element and the low thermal expansion material 6A is made into the same dimension as □ 15 mm, the outer periphery dimension of a semiconductor element and the low thermal expansion material 6A may be made into a different value, for example, the low thermal expansion material 6A Even if the outer peripheral dimension is made larger than that of the semiconductor element so as to protrude from the semiconductor element, it is possible to obtain the effect of suppressing the heat dissipation and reducing the compressive stress applied to the semiconductor element. Furthermore, lead frame materials such as super invar, 42 alloy, and kovar can be applied to the low thermal expansion material 6A in addition to invar.

Embodiment 2. FIG.
In Embodiment 1 described above, the low thermal expansion material 6A is composed of a single member and the single solder 4 is used. However, the present invention is not limited to this, and is composed of a plurality of members. The low thermal expansion material 6B may be used, and a plurality of types of solders 4A and 4B may be used. Therefore, as a second embodiment, a case where a low thermal expansion material 6D composed of a plurality of members and a plurality of types of solders 4A and 4B are used will be described below.

  FIG. 5 is a partial top view of the power semiconductor device according to the second embodiment, and FIG. 6 is a cross-sectional view of the power semiconductor device according to the second embodiment corresponding to the cross-sectional view between AA in FIG. FIG. 7 is a top view of the low thermal expansion material 6D according to the second embodiment. 5 to 7, the same reference numerals as those in FIGS. 1 to 4 denote the same or corresponding components, and the description thereof will be omitted below. Since the second embodiment is different from the first embodiment in that the low thermal expansion material 6D is used and the high liquid phase solder 4A and the low liquid phase solder 4B are used. The description of the same or corresponding parts will be omitted. 5 indicates the low thermal expansion material 6D existing on the back side of the IGBT 1A, and the broken line illustrated in FIG. 7 illustrates the planar position of the IGBT 1A.

  5 to 7, the low thermal expansion material 6D made of invar is composed of four parts divided for each side of the frame shape, and the main surface of the circuit board 3 and the back surface of the Ni-plated low thermal expansion frame 6D. Are joined by a highly liquid phase solder 4A having a conductive Sn—Cu liquidus temperature of 350 ° C. or higher. On the other hand, the back surface of the IGBT 1A and the surface of the low thermal expansion frame 6D, and the back surface of the IGBT 1A and the surface of the circuit pattern 3C are Sn—Ag—Cu based low liquid phase solder 4B having a conductivity of about 220 ° C. It is joined.

  With this configuration, in the present embodiment, by making the four sides of the frame-shaped low thermal expansion material 6D as separate parts, the material yield is improved in the manufacturing process of the low thermal expansion material 6D, and the cost is reduced. realizable. Further, in the present embodiment, after the back surface of the low thermal expansion material 6D is joined to the main surface of the circuit board 3 using the high liquid phase wire solder 4A having a high melting point, the low liquid phase wire solder 4B having a lower melting point is used. Since the back surface of the IGBT 1A can be bonded to the main surface of the circuit board 3 and the surface of the low thermal expansion material 6D, the IGBT 1A can be bonded with the low thermal expansion material 6D fixed to the circuit board 3. Therefore, compared with the case where it joins using the single solder 4, IGBT1A, the circuit board 3, and the low thermal expansion material 6D can be joined easily, and the productivity of the semiconductor device for electric power improves.

  The high liquidus solder 4A used for attaching the low thermal expansion material frame 6D to the circuit board 3 is Sn-Cu based solder having a high liquidus temperature. It is also possible to use gold (Au) -Sn based solder in consideration of the joining by Ag sintering adopted and the joining property.

Embodiment 3 FIG.
In Embodiment 1 or 2 described above, the frame-shaped low thermal expansion material 6A or 6D is used. However, the present invention is not limited to this, and other shapes of low thermal expansion material can also be used. In particular, in an IGBT or the like in which the gate electrode is arranged at the center of the element, the heat generation distribution on the back surface of the IGBT becomes a donut-shaped heat generation distribution with a small amount of heat generation at the center of the element, so that it corresponds to the heat generation distribution on the back surface of the IGBT. Alternatively, the low thermal expansion material 6E or 6F may be disposed in the center of the element. Therefore, the case where the low thermal expansion material 6E or 6F is used as Embodiment 3 will be described below.

  8 is a partial top view of the power semiconductor device according to the third embodiment, FIG. 9 is a partial top view of the IGBT 1B used as a semiconductor element in the third embodiment, and FIG. 10 is a diagram of the low thermal expansion material 6E. FIG. 11 is a partial top view, and FIG. 11 is a partial top view of the low thermal expansion material 6D. Here, the broken line shown in FIG. 8 shows the low thermal expansion material 6E existing on the back side of the IGBT 1B, and the broken line in FIGS. 10 and 11 shows the planar position of the IGBT 1B. 8 to 11, the same reference numerals as those in FIGS. 1 to 7 denote the same or corresponding components, and the description thereof will be omitted below. Note that the third embodiment is different from the first embodiment in that the IGBT 1B is used as a semiconductor element and the low thermal expansion material 6E or 6F is used. The description about the part is omitted.

  In FIG. 8, a low thermal expansion material 6E made of Invar is an X-shaped member plated with Ni having a width of 1 mm and a thickness of 200 μm, and is disposed along the diagonal 2 direction of the IGBT 1B. The low thermal expansion material 6 </ b> E is soldered to the back surface of the IGBT 1 </ b> B with the Sn—Ag—Cu-based solder 4 and to the main surface of the circuit board 3. The aluminum wire 5 is joined to an electrode provided on the surface of the IGBT 1B at a position excluding the region where the low thermal expansion material 6E is installed.

In FIG. 9, a termination structure 7 is provided on the outer periphery of the IGBT 1B.
A gate electrode 8 and a gate wiring 9 are provided at the center of the surface. For this reason, the heat generation amount of the main surface of the IGBT 1B is reduced in the region immediately below the gate electrode 8 and the gate wiring 9 in addition to the region of the termination structure 7, so that the heat generation distribution on the main surface of the IGBT 1B has a donut shape.

  10 shows the shape of the low thermal expansion material 6E, but instead of the low thermal expansion material 6E, the low thermal expansion material 6F shown in FIG. 11 corresponds to the positions of the gate electrode 8 and the gate wiring 9 of the IGBT 1B. May be used. That is, the low thermal expansion material 6 </ b> F has a shape along the two opposing sides of the IGBT 1 </ b> B and the gate wiring 9. Further, similarly to the first or second embodiment, a frame-shaped low thermal expansion material along the termination structure 7 of the IGBT 1B may be combined.

  With such a configuration, the stress applied to the IGBT 1B caused by the difference in thermal expansion is the highest in the center of the element. By arranging the low thermal expansion material 6E or 6F in the diagonal direction where the distance from the center of the element is long, the solder layer Since the thermal deformation toward the center of the element can be restrained, the stress of the IGBT 1B can be reduced. In addition, the area immediately below the gate electrode 8 and the gate wiring 9 on the back surface of the IGBT 1B generates less heat than the other areas. Therefore, the low thermal expansion material 6E or 6F having a low thermal conductivity is arranged so as to correspond to the position of the gate electrode 8 and the gate wiring 9, thereby corresponding to the heat generation distribution on the back surface of the IGBT 1B and the low thermal expansion of the IGBT 1B. Since the surfaces of the materials 6E or 6F can be bonded, it is possible to more effectively suppress a decrease in heat dissipation as the entire power semiconductor device.

  In addition, when a large solder void exists directly under the semiconductor element, particularly when the semiconductor element is thin, there is a concern about an increase in product defect rate due to damage when joining the aluminum wire 5 on the solder void. When energizing current, the temperature rises rapidly on the solder void and the element does not operate in the worst case. Therefore, the presence or absence of the solder void directly under the semiconductor element, particularly directly under the aluminum wire 5 is inspected by X-ray inspection or the like. There is a need. Here, when there are multiple solder layers, it may be difficult to determine which layer has a solder void, or there may be a case where X-ray permeability is deteriorated and solder void is difficult to recognize.

  However, in the present embodiment, by joining the aluminum wire 5 at a position excluding the region where the low thermal expansion material 6E is disposed, the solder layer directly below the aluminum wire 5 does not become multi-layered. Compared to the case of multiple layers, the inspection of solder voids by X-ray inspection or the like is facilitated, and the occurrence of damage when the aluminum wire 5 is joined can be suppressed. Further, regarding the temperature change generated by intermittently energizing the IGBT 1B, the region where the low thermal expansion material 6E with low thermal conductivity is arranged is the largest, but the joint portion of the aluminum wire 5 is the low thermal expansion material 6E. Therefore, it is possible to improve the reliability of the joint portion of the aluminum wire 5 against a temperature change caused by energization of the IGBT 1B.

  Further, some semiconductor elements having the gate electrode 9 at the center of the element include a plurality of gate wirings 9 as in the IGBT 1C shown in FIG. When such a semiconductor element is used, a low thermal expansion material 6G shown in FIG. 13 can be used. In FIG. 13, the broken line indicates the planar position of the IGBT 1C. The low thermal expansion material 6G has a shape along the two opposing sides of the IGBT 1C and the plurality of gate wirings 9. Thereby, since the back surface of IGBT1C and the surface of the low thermal expansion material 6E can be joined so as to correspond to the heat generation distribution on the back surface of IGBT1C, it is possible to effectively suppress a decrease in heat dissipation of the power semiconductor device. Can do.

  Note that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be modified or omitted as appropriate.

1A, 1B, 1C IGBT
2 FWD
3 Circuit board 3A Base 3B Insulating layer 3C Circuit pattern 4 Solder 4A High liquid phase solder 4B Low liquid phase solder 5 Aluminum wire 6A, 6B, 6C, 6D, 6E, 6F, 6G Low thermal expansion material 7 Termination structure 8 Gate electrode 9 Gate wiring 100 Power semiconductor device

Claims (8)

A semiconductor element;
A circuit board facing the first main surface of the semiconductor element and electrically connected to the first main surface of the semiconductor element;
A low thermal expansion material disposed in a region including a part of a space where the first main surface of the semiconductor element and the main surface of the circuit board are opposed to each other, having a lower coefficient of thermal expansion and higher rigidity than the circuit board; ,
A first main surface of the semiconductor element and a main surface of the circuit board; a first main surface of the semiconductor element; a first main surface of the low thermal expansion material; and a second main surface of the low thermal expansion material. Bonding the main surface of the circuit board in each of at least a part of the region, a bonding material having a higher thermal conductivity than the low thermal expansion material,
A power semiconductor device comprising: The bonding material bonds the first main surface of the semiconductor element and the first main surface of the low thermal expansion material corresponding to the heat generation distribution on the first main surface of the semiconductor element,
The power semiconductor device according to claim 1. The amount of heat generated per unit area in the first region where the first main surface of the low thermal expansion material is joined to the first main surface of the semiconductor element is the circuit in the first main surface of the semiconductor element. Less than the calorific value per unit area in the second region where the main surface of the substrate is joined,
The power semiconductor device according to claim 2. The low thermal expansion material is arranged in a frame shape along the outer periphery of the first main surface of the semiconductor element.
The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device. The low thermal expansion material intersects at the center of the first main surface of the semiconductor element;
The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device. The low thermal expansion material is arranged along two opposing sides of the first main surface of the semiconductor element and a straight line drawn perpendicular to the opposing two sides. The power semiconductor device according to claim 1. The bonding material is
A first bonding material for bonding the first main surface of the semiconductor element and the main surface of the circuit board, and the first main surface of the semiconductor element and the first main surface of the low thermal expansion material;
The main surface of the circuit board and the second main surface of the low thermal expansion material are bonded, and configured by a second bonding material having a higher liquidus temperature than the first bonding material,
The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device. The semiconductor element includes an electrode on a second main surface which is a surface opposite to the first main surface,
The electrode is joined to a metal wire on a region where the low thermal expansion material is not disposed.
The power semiconductor device according to claim 1, wherein the power semiconductor device is a power semiconductor device.

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