JP3705779B2 - Power device, manufacturing method thereof, and tin-based solder material - Google Patents

Power device, manufacturing method thereof, and tin-based solder material Download PDF

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JP3705779B2
JP3705779B2 JP2002084921A JP2002084921A JP3705779B2 JP 3705779 B2 JP3705779 B2 JP 3705779B2 JP 2002084921 A JP2002084921 A JP 2002084921A JP 2002084921 A JP2002084921 A JP 2002084921A JP 3705779 B2 JP3705779 B2 JP 3705779B2
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copper
tin
lead
semiconductor element
based solder
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JP2003282604A (en
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和樹 舘山
康成 浮田
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Die Bonding (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は、鉛を含まないはんだを用いたダイマウントに関するものであり、特にパワーデバイスに適用されるはんだと製造方法に関わる。
【０００２】
【従来の技術】
近年、環境への配慮から、電気部品の接合に用いられるはんだの材料から、環境有害物質とされている鉛の成分が除かれてきている。このような鉛を含まないはんだをPbフリーはんだと呼んでいる。
電気部品と配線基板との接合は、そのほとんどがPbフリーはんだによって行われてきているものの、半導体チップをリードフレームに対して接合するダイマウントに用いられるはんだとしては、そのプロセス上の問題から、鉛を含むはんだ材料が用いられている。
【０００３】
【発明が解決しようとする課題】
環境に対する配慮から、ダイマウントに係るはんだ材料に対してもPbフリー化したいという要望がある。
しかしながら、上記した半導体装置の製造方法において示されているように、半導体素子とインナーリードを結線するワイヤボンディング工程においては２８０℃以上と、一般に使用可能なPbフリーはんだの融点を越える温度にまで接合ポイントを熱する必要が生じるため、これによってはんだ材料が再溶融してしまい、安定したワイヤボンディングを行うことができなくなってしまうという問題があった。
【０００４】
一方、ワイヤボンディングのプロセス温度を下げるためにワイヤの接合ポイントにＡｇめっきを施す方法もあるが、めっきを施すため工数や材料が余計に必要になるため、現実的な方法ではなかった。
【０００５】
また、ワイヤボンディングがうまくできても、半導体装置を配線基板にはんだ付けする際に、再度昇温させる必要があるため、結局内部で再溶融が起こり、信頼性を下げる要因となってしまっていた。
【０００６】
他の手段として、リードフレームに半導体チップをダイマウントする際に用いられる材料としては、はんだのほかＡｇペーストが知られているが、Ａｇペーストは熱伝導性が劣る。そのため、熱の発生が著しい半導体素子を用いた半導体装置である場合に、ダイマウントに用いた材料が放熱パスとして機能しにくい問題があるため、パワーデバイスに用いられる半導体素子のダイマウントには、はんだ材料を用いなければならない。
【０００７】
本発明は、半導体素子のダイマウントに用いるはんだ材料をPbフリー化したパワーデバイスを提供することを目的とする。
【０００８】
【課題を解決するための手段】
上記した課題を解決するために、本発明は、表面に電極を有する半導体素子と、前記半導体素子を支持するダイ部と、表面が少なくとも銅もしくは銅合金であるインナーリード部を有するリードと、前記インナーリード部と前記電極とを電気的に接続するワイヤと、前記ダイ部と前記半導体素子とを接合する接合部材とを有し、前記接合部材は、前記半導体素子及び前記ダイ部それぞれとの接合界面に銅と錫との合金による反応層を有するとともに、前記一対の反応層の間に、アンチモンを組成に含む錫基合金であって銅もしくは銅合金の粒を含有した接合部材を有するパワーデバイスを提供する。
【０００９】
また、本発明は、アンチモンが組成に含まれる鉛フリー錫基はんだと、前記鉛フリー錫基はんだに対して混練されている銅もしくは銅合金の粒とを具備するダイマウント用の錫基はんだ材料を提供する。
【００１０】
また、本発明は、半導体素子を、少なくとも表面が銅もしくは銅合金によって形成されているリードフレームに対して、銅もしくは銅合金の粒ならびにアンチモンを組成に含む鉛フリー錫系はんだの粒を有するソルダペーストを介してマウントする工程と、前記半導体素子が前記リードフレームにマウントされた状態でさらに所定の温度で加熱しつづけ、前記ダイ部及び前記半導体素子のそれぞれのソルダペーストとの接合界面に銅と錫の合金層を成長させる熱処理工程と、前記半導体素子表面に形成された電極と前記リードのインナーリード部とを導電性のワイヤによって結線し電気的に接続するワイヤボンディング工程と、すくなくとも前記半導体素子と前記ワイヤとを封止する工程とを具備するパワーデバイスの製造方法を提供する。
【００１１】
【発明の実施の形態】
以下、本発明の半導体装置の製造方法の実施形態について図面を参照して詳細に説明する。
図１に、本発明の実施形態のパワーデバイスの断面の模式図を示す。Ｃｕ製のリードフレーム１は１ｍｍほどの厚さであり、ダイ部１ａとリードの一部としてインナーリード部１ｂを有している。ダイ部１ａには半導体素子２が接合部材３を介して接合されている。リードフレーム１は、放熱性を高めるために、無酸素銅などのＣｕ系材料が用いられている。ダイ部１ａは３ｍｍ２程度の正方形である。
【００１２】
接合部材３は、Ｓｎ基はんだとＣｕ粉末とが混練されたはんだ材料が溶融されて固化されたことにより形成された４０μmの部材であり、１０μｍの第１のCu-Sn反応層３ａと２０μｍのＳｎ基はんだ部３ｂと１０μｍの第２のCu-Sn反応層３ｃとを有している。Ｓｎ基はんだ部３ｂは、内部に第３のCu-Sn反応層３ｄにより被覆されたＣｕ粉末３ｅを有している。半導体素子２は２００μｍほどの厚さであり、表面に電極２ａが形成されており、電極２ａとインナーリード部１ｂのＣｕ表面とは、ボンディングワイヤ４で結線されている。電極２ａは、350×500μｍ２程度の大きさである。
【００１３】
上記したリードフレームのダイ部１ａ及びインナーリード部１ｂ，半導体素子２，接合部材３，ボンディングワイヤ４は、封止材料５によって封止されている。放熱性を高めるため、ダイ部１ａの半導体素子２が接続されていない方の面は封止材料によって覆われておらず、露出している。
【００１４】
図２に、図１のパワーデバイスの製造工程のフロー図を示す。なお、パワーデバイスの各構成については、図１を参照して説明する。
はんだ材料供給工程１０１は、無酸素銅から構成されるリードフレーム１のダイ部１ａ上にソルダペーストを供給する工程である。ソルダペーストは、粉末状のＳｎ基はんだとＣｕ粉末とフラックスとが混練されて構成されたペースト状のはんだ材料である。本実施形態のソルダペーストは直径が３０μｍ以下でSn-30wt%Sbの組成を有するＳｎ基はんだ粒からなるＳｎ基はんだ粉末と、直径が１０μｍ以下のＣｕ粒からなるＣｕ粉末とを、９対１の体積比で混合し、これに液状のフラックスを混ぜて均一に混練して作成した。
【００１５】
Ｓｎ基を有するはんだ材料は上記したSn-Sb系のほか、Sn-Ag系、Sn-Cu系がよく用いられている。このなかでもとくにSn-Sb系のはんだ材料を選択した理由は、溶融開始温度がSn-8.5wt%Sbで２４５℃前後と、常用されるＳｎ系はんだのなかで最も高く、本発明のプロセスに最も適していると判断されるからである。
【００１６】
Ｓｎ基はんだ材料であるSn-Sbはんだは、Ｓｂの濃度が35wt%を超えるようになると溶けにくくなり、濡れ性が低下してくる場合がある。濡れ性が極端に低下しているはんだを用いた場合は、このはんだによる接合部にボイドや未接合部による隙間が発生する場合があるため、Ｓｎ基はんだ材料に用いるSbの濃度は３５％以下とすることが好ましい。本実施形態では、上記したように３０ｗｔ％の組成比としている。
【００１７】
半導体素子接合工程１０２は、チップ状部品である半導体素子２を、ダイ部１ａ上に盛られたソルダペースト上にマウントして、３２０℃還元雰囲気に曝して加熱させてソルダペーストを溶融し、これを還元雰囲気から取り出して放熱させて冷却することにより固化させ、ソルダペーストを接合部材３として接合させる工程である。
【００１８】
半導体素子２には一方の主面に電極２ａが形成されている。他方の主面ははんだの濡れをよくするために、Ti，Ni，Agの順にスパッタを施してメタライズしており、このメタライズ面をはんだペーストに接触させるようマウントしている。
【００１９】
雰囲気は非酸化雰囲気であればよいが、ソルダペースト表面の酸化層を幾ばくかでも還元可能なように還元雰囲気を用いた。還元雰囲気としては、窒素９０％と水素１０％の体積比の気体を用いた。
【００２０】
熱処理工程１０３は、半導体素子２とリードフレーム１とを接合している接合部材３のCu-Sn反応層を成長させる工程である。具体的には、温度３２０℃、窒素１００％の非酸化雰囲気中に１時間おくことにより、熱処理した。
【００２１】
熱処理により、ソルダペースト内のCuあるいはリードフレーム表面のCuが、ソルダペースト内のSnと反応してCuとSnとによる合金を形成する。この合金を熱処理して成長させることによりＳｎ基はんだ材料のＳｎの濃度が低下し、相対的にＳｂの濃度が上昇する。Sn-Sbはんだは、Ｓｂの濃度が４０％、好ましくは４３％を超えると溶融温度域が高温側に遷移していく。したがって、半導体素子２を確実に接合させたあとで熱処理を加えることにより、実質的には、溶融温度の高いはんだ材料によってダイマウントを施した場合と同じように扱うことができるようになる。
【００２２】
この熱処理工程１０３により、接合部材３とダイ部１ａとの界面と、Ｓｎ基はんだ３ｂ内のＣｕ粉末３ｅの各粒子の周囲のみならず、半導体素子２と接合部材３との界面に、ＣｕとＳｎとによる合金によって構成されるCu-Sn反応層３ａ，３ｃ，３ｄがそれぞれ形成され成長する。熱処理を続けることによりCu-Sn反応層３ａ，３ｃ，３ｄはそれぞれ成長して厚みを増す。また、Cu-Sn反応層３ａ，３ｃ，３ｄが成長するにつれてＳｎ基はんだ部３ｂに占めるＳｎの組成比は、相対的に低下していく。
【００２３】
熱処理の処理条件は、ダイサイズやダイ部上に供給されるソルダペーストの体積やダイ部及び半導体素子との接触面積に依存するが、そのソルダペーストのはんだ組成物の平衡状態図において、ワイヤボンディング時のプロセス温度である２８０℃で、用いたはんだ材料がβ’相に変化している濃度となるように合金層を成長させる条件を選び、熱処理を施す。
表１にSn-30wt%Sbの組成比の粉末を用いて作製したはんだ材料について、図１のパワーデバイスでの比較実験例を示す。
【００２４】
【表１】

Figure 0003705779
サンプル番号１のはんだ材料はＣｕ粉末を有さず、熱処理も施されていないはんだ材料により構成された接合部材である。また、サンプル番号２のはんだ材料はＣｕ粉末は混練されたが熱処理工程を経ていない接合部材である。サンプル番号３は、Ｃｕ粉末を有し熱処理工程を経たあとの接合部材３である。
【００２５】
これらのサンプルについてそれぞれ示差走査熱量計により接合部材３の溶融開始温度を測定したところ、表１に示されるように、サンプル番号３の接合部材３については２５０℃近傍あるいはそれ以下の温度帯に、溶融開始温度が見受けられないことが確認された。サンプル番号１と２については、この温度域で比較的溶融しやすいことが分かる。
【００２６】
なお、表１の実験例は本実施形態のパワーデバイスの構成における結果であり、たとえば、接合部材の厚さが３０μｍに設定されれば、サンプル番号２の接合部材であっても２５０℃近傍に溶融温度域が現れないことを確認した。
【００２７】
ワイヤボンディング工程１０４は、インナーリード部１ｂと電極２ａとをボンディングワイヤ４によって結線し、電気的に接続する工程である。具体的には、２８０℃に熱せられた体積比で窒素９０％、水素１０％の還元雰囲気中にて接続ポイントを熱し、Ａｕの細線をキャピラリから繰り出してワイヤボンディングを行う。ここにおいて通常溶け出す接合部材はＣｕ粉末を含みかつ熱処理されているため、固化したままである。
【００２８】
封止工程１０５は、ダイ部１ａ、インナーリード部１ｂ、半導体素子２、接合部材３、ボンディングワイヤ４を外囲器５で被覆する工程である。外囲器５は黒色に着色されたエポキシ樹脂組成物が固化したものであり、低圧トランスファモールド法により成形される。金型にてモールディングを行った後、樹脂材料を完全に固化させるために、１７５℃のもとで８時間の熱処理を行う。
【００２９】
このようにして得られたパワーデバイスはさらに他の配線基板などに対してアウターリードにおいてはんだ付けされる。このはんだ付けの際もSn-Sbはんだ材料の溶融温度域である２４５℃以上のはんだ付けプロセス温度にさらされる場合が多いが、そのような実装工程においても、接合部材３が溶融して信頼性が低下するという事態は発生しない。
【００３０】
上記したように本実施形態においては、Ｃｕ粉末を混練させたＳｎ系はんだ材料を用いてダイボンディングを行った。これによりCu-Sn反応層の生成を促すことができ、半導体装置の信頼性の向上に寄与することができた。
また、本実施形態では、ダイボンディングのあと、ワイヤボンディング工程の前にCu-Sn反応層を成長させるための熱処理工程を導入した。これによりSn基はんだ部の相対的なSn濃度を下げることができ、接合部材３の溶融温度を高めることができた。
また、ソルダペーストのはんだ材料としてSn-Sb系はんだを用いたことにより、熱処理工程に係る作業時間を短縮することができた。
【００３１】
なお、上記実施形態において接合部材３の厚さは４０μｍに設定したが、２０μｍから４０μｍの間で設定することが好ましい。２０μｍ以下であると熱による部材の膨張を接合部材３が吸収できずに、接合部材３にクラックが生じる場合がある。また、４０μｍよりも厚くなると熱処理に係るタクトタイムが膨大になるため、現実的な時間内で半導体装置を製造することが困難になってしまう。
その他、構造やプロセス条件は本発明の主旨の範囲で種々の変更が可能であることは言うまでもない。
【００３２】
【発明の効果】
本発明の半導体装置及びその製造方法によれば、環境影響度の少ない半導体装置を提供することを可能とする。
【図面の簡単な説明】
【図１】 本発明の実施形態のパワーモジュールの断面の模式図。
【図２】 本発明の実施形態のパワーモジュールの製造工程のフロー図。
【符号の説明】
１…リードフレーム、２…半導体素子、３…接合部材、
４…ボンディングワイヤ、５…外囲器、
１ａ…ダイ部、１ｂ…インナーリード部、２ａ…電極、
３ａ，３ｃ，３ｄ…Ｃｕ−Ｓｎ反応層[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a die mount using a lead-free solder, and particularly relates to a solder applied to a power device and a manufacturing method.
[0002]
[Prior art]
In recent years, lead components, which are regarded as environmentally hazardous substances, have been removed from solder materials used for joining electrical components in consideration of the environment. Such lead-free solder is called Pb-free solder.
Most of the bonding between electrical components and wiring boards has been done with Pb-free solder, but as a solder used for die mounting to bond a semiconductor chip to a lead frame, due to its process problems, A solder material containing lead is used.
[0003]
[Problems to be solved by the invention]
Due to environmental considerations, there is a desire to make Pb-free solder materials for die mounts.
However, as shown in the semiconductor device manufacturing method described above, in the wire bonding process for connecting the semiconductor element and the inner lead, the bonding is performed at a temperature exceeding 280 ° C. and exceeding the melting point of generally usable Pb-free solder. Since it is necessary to heat the point, the solder material is remelted by this, and there is a problem that stable wire bonding cannot be performed.
[0004]
On the other hand, there is a method in which Ag plating is performed on the bonding point of the wire in order to lower the wire bonding process temperature. However, since man-hours and materials are necessary for performing the plating, this is not a practical method.
[0005]
Even if wire bonding can be performed successfully, it is necessary to raise the temperature again when soldering the semiconductor device to the wiring board, which eventually causes remelting inside, resulting in reduced reliability. .
[0006]
As other means, Ag paste is known in addition to solder as a material used when die-mounting a semiconductor chip on a lead frame. However, Ag paste has poor thermal conductivity. Therefore, in the case of a semiconductor device using a semiconductor element that generates significant heat, the material used for the die mount has a problem that it is difficult to function as a heat dissipation path. Solder material must be used.
[0007]
An object of this invention is to provide the power device which made Pb free the solder material used for the die mount of a semiconductor element.
[0008]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention provides a semiconductor element having an electrode on its surface, a die part that supports the semiconductor element, a lead having an inner lead part whose surface is at least copper or a copper alloy, a wire for connecting the inner lead portion electrode electrically, and a joining member for joining the said die portion and the semiconductor element, the bonding member, the bonding between the semiconductor element and the die unit, respectively A power device having a reaction layer made of an alloy of copper and tin at the interface, and having a bonding member between the pair of reaction layers, a tin-based alloy containing antimony in its composition and containing copper or copper alloy particles I will provide a.
[0009]
Further, the present invention provides a tin-based solder material for die mounting comprising a lead-free tin-based solder containing antimony in its composition and copper or copper alloy particles kneaded with the lead-free tin-based solder I will provide a.
[0010]
The present invention also provides a semiconductor element having a solder having lead-free tin-based solder grains containing copper or copper alloy grains and antimony in a lead frame having at least a surface formed of copper or a copper alloy. A step of mounting via a paste, and further heating at a predetermined temperature in a state where the semiconductor element is mounted on the lead frame, and copper at the bonding interface with each solder paste of the die part and the semiconductor element. A heat treatment step for growing an alloy layer of tin, a wire bonding step for connecting and electrically connecting an electrode formed on the surface of the semiconductor element and an inner lead portion of the lead by a conductive wire, and at least the semiconductor element And a method of manufacturing a power device comprising the step of sealing the wire .
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of a method for manufacturing a semiconductor device of the present invention will be described below in detail with reference to the drawings.
In FIG. 1, the schematic diagram of the cross section of the power device of embodiment of this invention is shown. The lead frame 1 made of Cu has a thickness of about 1 mm, and has a die portion 1a and an inner lead portion 1b as a part of the lead. A semiconductor element 2 is bonded to the die portion 1 a via a bonding member 3. The lead frame 1 uses a Cu-based material such as oxygen-free copper in order to improve heat dissipation. The die part 1a is a square of about 3 mm 2 .
[0012]
The joining member 3 is a 40 μm member formed by melting and solidifying a solder material in which Sn-based solder and Cu powder are kneaded, and the 10 μm first Cu—Sn reaction layer 3a and 20 μm It has a Sn-based solder part 3b and a 10 μm second Cu—Sn reaction layer 3c. The Sn-based solder portion 3b has Cu powder 3e covered with a third Cu—Sn reaction layer 3d inside. The semiconductor element 2 has a thickness of about 200 μm, and an electrode 2 a is formed on the surface. The electrode 2 a and the Cu surface of the inner lead portion 1 b are connected by a bonding wire 4. The electrode 2a is about 350 × 500 μm 2 in size.
[0013]
The die part 1 a and inner lead part 1 b of the lead frame, the semiconductor element 2, the bonding member 3, and the bonding wire 4 are sealed with a sealing material 5. In order to improve heat dissipation, the surface of the die portion 1a to which the semiconductor element 2 is not connected is not covered with the sealing material and is exposed.
[0014]
FIG. 2 shows a flowchart of the manufacturing process of the power device of FIG. In addition, each structure of a power device is demonstrated with reference to FIG.
The solder material supply step 101 is a step of supplying solder paste onto the die portion 1a of the lead frame 1 made of oxygen-free copper. The solder paste is a paste-like solder material configured by kneading powdered Sn-based solder, Cu powder, and flux. The solder paste of the present embodiment has a 9: 1 ratio of Sn-based solder powder composed of Sn-based solder grains having a diameter of 30 μm or less and Sn-30 wt% Sb and Cu powder composed of Cu grains having a diameter of 10 μm or less. The mixture was mixed at a volume ratio of, and a liquid flux was mixed with the mixture and uniformly kneaded.
[0015]
In addition to the Sn—Sb system described above, Sn—Ag system and Sn—Cu system are often used as solder materials having an Sn group. Among these, the reason for selecting the Sn-Sb solder material is that the melting start temperature is Sn-8.5wt% Sb, around 245 ° C, which is the highest among the commonly used Sn solders. This is because it is judged to be most suitable.
[0016]
Sn—Sb solder, which is a Sn-based solder material, becomes difficult to melt when the Sb concentration exceeds 35 wt%, and the wettability may decrease. If solder with extremely low wettability is used, voids or unjoined gaps may occur at the joints with this solder, so the concentration of Sb used in the Sn-based solder material is 35% or less. It is preferable that In the present embodiment, the composition ratio is 30 wt% as described above.
[0017]
In the semiconductor element bonding step 102, the semiconductor element 2 which is a chip-like component is mounted on a solder paste built up on the die portion 1a, and is heated by exposure to a reducing atmosphere at 320 ° C. to melt the solder paste. In this step, the solder paste is solidified by taking it out from the reducing atmosphere, dissipating heat and cooling it, and joining the solder paste as the joining member 3.
[0018]
The semiconductor element 2 has an electrode 2a formed on one main surface. The other main surface is metallized by sputtering in the order of Ti, Ni, and Ag in order to improve solder wettability, and the metallized surface is mounted so as to contact the solder paste.
[0019]
The atmosphere may be a non-oxidizing atmosphere, but a reducing atmosphere was used so that the oxide layer on the surface of the solder paste could be reduced as much as possible. As the reducing atmosphere, a gas having a volume ratio of 90% nitrogen and 10% hydrogen was used.
[0020]
The heat treatment step 103 is a step of growing a Cu—Sn reaction layer of the joining member 3 joining the semiconductor element 2 and the lead frame 1. Specifically, heat treatment was performed by placing in a non-oxidizing atmosphere at a temperature of 320 ° C. and nitrogen of 100% for 1 hour.
[0021]
By heat treatment, Cu in the solder paste or Cu on the lead frame surface reacts with Sn in the solder paste to form an alloy of Cu and Sn. By growing this alloy by heat treatment, the Sn concentration of the Sn-based solder material is decreased, and the Sb concentration is relatively increased. When the Sb concentration exceeds 40%, and preferably exceeds 43%, the melting temperature region of the Sn—Sb solder transitions to the high temperature side. Therefore, by applying heat treatment after the semiconductor element 2 is securely bonded, it can be handled in the same manner as when die mounting is performed with a solder material having a high melting temperature.
[0022]
By this heat treatment step 103, not only the interface between the bonding member 3 and the die part 1a and the periphery of each particle of the Cu powder 3e in the Sn-based solder 3b but also the interface between the semiconductor element 2 and the bonding member 3 Cu-Sn reaction layers 3a, 3c, 3d composed of an alloy with Sn are formed and grown. By continuing the heat treatment, the Cu—Sn reaction layers 3a, 3c, and 3d grow and increase in thickness. Further, as the Cu—Sn reaction layers 3a, 3c, and 3d grow, the composition ratio of Sn in the Sn-based solder portion 3b relatively decreases.
[0023]
The processing conditions of the heat treatment depend on the die size, the volume of the solder paste supplied onto the die part , and the contact area between the die part and the semiconductor element, but in the equilibrium diagram of the solder composition of the solder paste, wire bonding At the process temperature of 280 ° C., the conditions for growing the alloy layer are selected so that the solder material used has a concentration changing to the β ′ phase, and heat treatment is performed.
Table 1 shows a comparative experimental example using the power device shown in FIG. 1 for a solder material manufactured using a powder having a composition ratio of Sn-30 wt% Sb.
[0024]
[Table 1]
Figure 0003705779
The solder material of sample number 1 is a joining member made of a solder material that does not have Cu powder and is not subjected to heat treatment. The solder material of sample number 2 is a joining member in which Cu powder is kneaded but not subjected to a heat treatment step. Sample number 3 is the bonding member 3 having Cu powder and having undergone a heat treatment process.
[0025]
When the melting start temperature of the joining member 3 was measured with a differential scanning calorimeter for each of these samples, as shown in Table 1, the joining member 3 of sample number 3 was in a temperature range around 250 ° C. or lower, It was confirmed that the melting start temperature was not observed. It can be seen that sample numbers 1 and 2 are relatively easy to melt in this temperature range.
[0026]
In addition, the experimental example of Table 1 is a result in the structure of the power device of this embodiment. For example, if the thickness of the joining member is set to 30 μm, even the joining member of sample number 2 is close to 250 ° C. It was confirmed that no melting temperature range appeared.
[0027]
The wire bonding step 104 is a step of connecting the inner lead portion 1b and the electrode 2a by the bonding wire 4 and electrically connecting them. Specifically, the connection point is heated in a reducing atmosphere of 90% nitrogen and 10% hydrogen at a volume ratio heated to 280 ° C., and a fine wire of Au is drawn out from the capillary to perform wire bonding. Here, the joining member that normally melts out contains Cu powder and is heat-treated, so it remains solidified.
[0028]
The sealing step 105 is a step of covering the die portion 1 a, the inner lead portion 1 b, the semiconductor element 2, the bonding member 3, and the bonding wire 4 with the envelope 5. The envelope 5 is a solidified epoxy resin composition colored in black, and is molded by a low-pressure transfer molding method. After molding with a mold, heat treatment is performed for 8 hours at 175 ° C. in order to completely solidify the resin material.
[0029]
The power device thus obtained is soldered to the other wiring board or the like with the outer leads. Even during this soldering, the soldering process temperature of 245 ° C. or more, which is the melting temperature range of the Sn—Sb solder material, is often exposed. There will be no decline.
[0030]
As described above, in this embodiment, die bonding is performed using an Sn-based solder material in which Cu powder is kneaded. As a result, the formation of the Cu—Sn reaction layer can be promoted, which contributes to the improvement of the reliability of the semiconductor device.
In this embodiment, a heat treatment step for growing the Cu—Sn reaction layer is introduced after the die bonding and before the wire bonding step. As a result, the relative Sn concentration of the Sn-based solder portion could be reduced, and the melting temperature of the joining member 3 could be increased.
In addition, by using Sn—Sb solder as the solder paste solder material, the working time for the heat treatment process could be shortened.
[0031]
In addition, in the said embodiment, although the thickness of the joining member 3 was set to 40 micrometers, it is preferable to set between 20 micrometers and 40 micrometers. If the thickness is 20 μm or less, the joining member 3 may not absorb the expansion of the member due to heat, and a crack may occur in the joining member 3. On the other hand, if the thickness is larger than 40 μm, the tact time for heat treatment becomes enormous, and it becomes difficult to manufacture the semiconductor device within a realistic time.
In addition, it goes without saying that the structure and process conditions can be variously changed within the scope of the present invention.
[0032]
【The invention's effect】
According to the semiconductor device and the manufacturing method thereof of the present invention, it is possible to provide a semiconductor device having a low environmental impact.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of a power module according to an embodiment of the present invention.
FIG. 2 is a flowchart of a manufacturing process of the power module according to the embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Lead frame, 2 ... Semiconductor element, 3 ... Joining member,
4 ... bonding wire, 5 ... envelope,
1a ... Die part, 1b ... Inner lead part, 2a ... Electrode,
3a, 3c, 3d ... Cu-Sn reaction layer

Claims (8)

表面に電極を有する半導体素子と、
前記半導体素子を支持するダイ部と、
表面が少なくとも銅もしくは銅合金であるインナーリード部を有するリードと、
前記インナーリード部と前記電極とを電気的に接続するワイヤと、
前記ダイ部と前記半導体素子とを接合する接合部材とを有し、
前記接合部材は、前記半導体素子及び前記ダイ部それぞれとの接合界面に銅と錫との合金による反応層を有するとともに、前記一対の反応層の間に、アンチモンを組成に含む錫基合金であって銅もしくは銅合金の粒を含有した接合部材を有することを特徴とするパワーデバイス。A semiconductor element having an electrode on the surface;
A die portion for supporting the semiconductor element;
A lead having an inner lead portion whose surface is at least copper or a copper alloy;
A wire for electrically connecting the inner lead portion and the electrode;
A bonding member for bonding the die portion and the semiconductor element;
The bonding member is a tin-based alloy having a reaction layer made of an alloy of copper and tin at the bonding interface between the semiconductor element and the die part, and containing antimony in the composition between the pair of reaction layers. A power device comprising a bonding member containing copper or copper alloy particles. 表面に電極を有する半導体素子と、
前記半導体素子を支持するダイ部と、
表面が少なくとも銅もしくは銅合金であるインナーリード部を有するリードと、
前記インナーリード部と前記電極とを電気的に接続するワイヤと、
前記ダイ部と前記半導体素子とを接合する接合部材とを有し、
前記接合部材は、前記半導体素子及び前記ダイ部それぞれとの接合界面に銅と錫との合金による反応層を有するとともに、前記一対の反応層の間に、４０ｗｔ％以上のアンチモンを組成に含む錫基合金であって銅もしくは銅合金の粒を含有した接合部材を有することを特徴とするパワーデバイス。A semiconductor element having an electrode on the surface;
A die portion for supporting the semiconductor element;
A lead having an inner lead portion whose surface is at least copper or a copper alloy;
A wire for electrically connecting the inner lead portion and the electrode;
A bonding member for bonding the die portion and the semiconductor element;
The bonding member includes a reaction layer made of an alloy of copper and tin at a bonding interface between the semiconductor element and the die part, and includes 40 wt% or more of antimony in the composition between the pair of reaction layers. A power device comprising a joining member which is a tin-based alloy and contains copper or copper alloy particles. アンチモンが組成に含まれる鉛フリー錫基はんだと、前記鉛フリー錫基はんだに対して混練されている銅もしくは銅合金の粒と、を具備することを特徴とするダイマウント用の錫基はんだ材料。  A tin-based solder material for die mounting, comprising: a lead-free tin-based solder containing antimony in its composition; and copper or copper alloy grains kneaded with the lead-free tin-based solder . アンチモンが３５ｗｔ％未満で組成に含まれる鉛フリー錫基はんだと、前記鉛フリー錫基はんだに対して混練されている複数の銅もしくは銅合金の粒と、を具備することを特徴とするダイマウント用の錫基はんだ材料。  A die mount comprising: a lead-free tin-based solder containing antimony in an amount of less than 35 wt%; and a plurality of copper or copper alloy grains kneaded with the lead-free tin-based solder Tin-based solder material. アンチモンが３０ｗｔ％以上３５ｗｔ％未満で組成に含まれる鉛フリー錫基はんだと、前記鉛フリー錫基はんだに対して混練されている複数の銅もしくは銅合金の粒と、を具備することを特徴とするダイマウント用の錫基はんだ材料。  A lead-free tin-based solder containing antimony in an amount of 30 wt% or more and less than 35 wt%, and a plurality of copper or copper alloy grains kneaded with the lead-free tin-based solder, Tin-based solder material for die mounting. 請求項３乃至５のいずれかに記載の錫基はんだ材料と、フラックスと、を具備することを特徴とするペースト状の錫基はんだ材料。  A paste-based tin-based solder material comprising the tin-based solder material according to any one of claims 3 to 5 and a flux. 銅もしくは銅合金の粒を含有するアンチモンの組成比が３５ｗｔ％未満の鉛フリー錫基はんだ材料によって半導体素子とリードフレームとを接合し、銅もしくは銅合金の粒子を含有するアンチモン濃度４０ｗｔ％以上の鉛フリー錫基はんだの接合部材を形成する工程を有することを特徴とするパワーデバイスの製造方法。A semiconductor element and a lead frame are joined by a lead-free tin-based solder material having a composition ratio of antimony containing copper or copper alloy grains of less than 35 wt%, and the concentration of antimony containing copper or copper alloy particles is 40 wt % or more. A method for producing a power device, comprising the step of forming a lead-free tin-based solder joint member. 半導体素子を、少なくとも表面が銅もしくは銅合金によって形成されているリードフレームに対して、銅もしくは銅合金の粒ならびにアンチモンを組成に含む鉛フリー錫系はんだの粒を有するソルダペーストを介してマウントする工程と、
前記半導体素子が前記リードフレームにマウントされた状態でさらに所定の温度で加熱しつづけ、前記ダイ部及び前記半導体素子のそれぞれのソルダペーストとの接合界面に銅と錫の合金層を成長させる熱処理工程と、
前記半導体素子表面に形成された電極と前記リードのインナーリード部とを導電性のワイヤによって結線し電気的に接続するワイヤボンディング工程と、
すくなくとも前記半導体素子と前記ワイヤとを封止する工程と、
を具備することを特徴とするパワーデバイスの製造方法。A semiconductor element is mounted on a lead frame whose surface is formed of at least copper or a copper alloy via a solder paste having copper or copper alloy grains and lead-free tin-based solder grains containing antimony. Process,
A heat treatment step in which the semiconductor element is mounted on the lead frame and is further heated at a predetermined temperature to grow an alloy layer of copper and tin at the bonding interface between the die portion and each solder paste of the semiconductor element. When,
A wire bonding step of electrically connecting the electrode formed on the surface of the semiconductor element and the inner lead portion of the lead by a conductive wire; and
Sealing at least the semiconductor element and the wire;
A method for manufacturing a power device, comprising:
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