JPWO2017037837A1 - Semiconductor device and power electronics device - Google Patents

Semiconductor device and power electronics device Download PDF

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JPWO2017037837A1
JPWO2017037837A1 JP2016563150A JP2016563150A JPWO2017037837A1 JP WO2017037837 A1 JPWO2017037837 A1 JP WO2017037837A1 JP 2016563150 A JP2016563150 A JP 2016563150A JP 2016563150 A JP2016563150 A JP 2016563150A JP WO2017037837 A1 JPWO2017037837 A1 JP WO2017037837A1
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metal plate
semiconductor device
wiring board
ceramic substrate
outer peripheral
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高彰 宮崎
高彰 宮崎
靖 池田
靖 池田
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Hitachi Ltd
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Hitachi Ltd
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Abstract

半導体チップと、半導体チップを支持し、半導体チップに電気的に接続された配線基板と、配線基板を支持する第１金属板と、配線基板と第１金属板との間に配置された第２金属板と、配線基板および第２金属板を接合する第１接合部と、第１金属板および第２金属板を接合する第２接合部とを有し、第２金属板の中央部の厚みよりも、第２金属板の外周部の厚みが大きい、半導体装置を提供する。A semiconductor chip, a wiring board supporting the semiconductor chip and electrically connected to the semiconductor chip, a first metal plate supporting the wiring board, and a second disposed between the wiring board and the first metal plate The thickness of the center part of a 2nd metal plate which has a 1st junction part which joins a metal plate, a wiring board, and a 2nd metal plate, and a 2nd junction part which joins a 1st metal plate and a 2nd metal plate A semiconductor device in which the thickness of the outer peripheral portion of the second metal plate is larger than that is provided.

Description

本発明は、半導体装置、鉄道車両および自動車に関し、特にインバータに使用されるパワー系の半導体装置の構造に関する。   The present invention relates to a semiconductor device, a railway vehicle, and an automobile, and more particularly to a structure of a power semiconductor device used for an inverter.

パワー系の半導体装置（パワーモジュール）の構造としては、半導体素子（以下、半導体チップまたは単にチップとも言う）と絶縁基板とをはんだ等で接合した構造、または絶縁基板と放熱用金属板とをはんだ等で接合した構造が知られている。   The structure of a power semiconductor device (power module) is a structure in which a semiconductor element (hereinafter also referred to as a semiconductor chip or simply a chip) and an insulating substrate are joined with solder or the like, or the insulating substrate and a metal plate for heat dissipation are soldered. The structure joined by such as is known.

近年、高温動作が可能で、かつ機器の小型軽量化が可能なＳｉＣ（炭化シリコン）またはＧａＮ（窒化ガリウム）等のワイドギャップ半導体を用いた半導体装置の開発が推し進められている。一般的にＳｉ（シリコン）の半導体素子は動作温度の上限が１５０〜１７５℃であるのに対し、ＳｉＣの半導体素子は１７５℃以上での使用が可能である。   In recent years, development of semiconductor devices using wide gap semiconductors such as SiC (silicon carbide) or GaN (gallium nitride) that can operate at high temperature and can be reduced in size and weight has been promoted. In general, the upper limit of the operating temperature of Si (silicon) semiconductor elements is 150 to 175 ° C., whereas SiC semiconductor elements can be used at 175 ° C. or higher.

また、電機・電子機器の部品の電気的接続に使用されている接続部材であるはんだには、一般的に鉛（Ｐｂ）が含まれていたが、近年、環境への意識が高まる中、鉛の規制が始まっている。例えば、欧州では自動車中の鉛使用を制限するＥＬＶ指令（End of Life Vehicles directive、廃自動車に関する指令）が施行されている。また、欧州では、電機・電子機器中の鉛使用を禁止するＲｏＨＳ（Restriction of the use of certain Hazardous Substances in electrical and electronic equipment)指令が施行されている。   In addition, solder, which is a connecting member used for electrical connection of parts of electric and electronic equipment, generally contains lead (Pb). However, in recent years, as environmental awareness has increased, lead Regulation has begun. For example, in Europe, the ELV directive (End of Life Vehicles directive) that restricts the use of lead in automobiles is in effect. In Europe, the RoHS (Restriction of the use of certain Hazardous Substances in electrical and electronic equipment) directive has been enforced, which prohibits the use of lead in electrical and electronic equipment.

これまで、高耐熱性が要求される半導体装置、特に自動車または建機、鉄道、情報機器分野等に用いられる半導体装置の接続部材としては鉛入りはんだが使用されてきたが、環境負荷低減のため、鉛フリーの接続部材を使用することが強く要求されている。   Up to now, lead-containing solder has been used as a connecting member for semiconductor devices that require high heat resistance, especially semiconductor devices used in the fields of automobiles, construction equipment, railways, information equipment, etc. There is a strong demand to use lead-free connecting members.

特許文献１（特表平０８−５０９８４４号公報）には、「本出願の目的は、電力半導体素子に関し、その際、セラミック基板（ＳＵＢ）及び金属底板（ＢＰ）は、順番に、接合層（２）、低い降伏点及び高い熱伝導率を有する材料からなる緩衝層（ＤＰ）並びにもう１つの接合層（３）を介して接合されており、その際、セラミック基板と底板間の機械的接合は、高い剪断強さを有し、かつセラミック基板と底板との異なる熱膨張による早期の物質疲労及び亀裂形成は、緩衝層の塑性変形により回避される。接合層は、例えば、低温接合技術において、電力半導体素子の際に有利に使用されるような、焼結された銀粉層である。」ことが記載されている（要約参照）。   Patent Document 1 (Japanese Patent Publication No. 08-509844) states that “the object of the present application relates to a power semiconductor element, and in this case, a ceramic substrate (SUB) and a metal bottom plate (BP) are joined in order to a bonding layer ( 2) Bonded via a buffer layer (DP) made of a material having a low yield point and high thermal conductivity and another bonding layer (3), in which case the mechanical bonding between the ceramic substrate and the bottom plate Has a high shear strength and premature material fatigue and crack formation due to different thermal expansions of the ceramic substrate and the bottom plate are avoided by plastic deformation of the buffer layer. , A sintered silver powder layer as used advantageously in power semiconductor devices ”(see summary).

また、特許文献２（特開２０１２−２８６７４号公報）には、「半導体素子３と、半導体素子３の電極に、接合材６ａを介して、一方の面が接合された第１の緩衝板７Ａと、第１の緩衝板７Ａの他方の面に、接合材６ｂを介して、一方の面が接合された第２の緩衝板７Ｂと、第２の緩衝板７Ｂの他方の面に接合された配線部材４と、を備え、第１の緩衝板７Ａは、半導体素子の線膨張係数αＣと配線部材４の線膨張係数αＷの間であって、半導体素子３の線膨張係数αＣとの差が第１の所定値より小さい線膨張係数αＢＡを有し、第２の緩衝板７Ｂは、第１の緩衝板７Ａの線膨張係数αＢＡと配線部材４の線膨張係数αＷの間であって、配線部材４の線膨張係数αＷとの差が第１の所定値より大きな第２の所定値より小さい線膨張係数αＢＢを有する、ように構成した。」ことが記載されている（要約参照）。   Patent Document 2 (Japanese Patent Application Laid-Open No. 2012-28674) states that “a first buffer plate 7A in which one surface is bonded to the electrodes of the semiconductor element 3 and the semiconductor element 3 via a bonding material 6a. And the second buffer plate 7B having one surface bonded to the other surface of the first buffer plate 7A via the bonding material 6b and the other surface of the second buffer plate 7B. The first buffer plate 7A is between the linear expansion coefficient αC of the semiconductor element and the linear expansion coefficient αW of the wiring member 4, and the difference between the linear expansion coefficient αC of the semiconductor element 3 is The second buffer plate 7B has a linear expansion coefficient αBA smaller than the first predetermined value, and the second buffer plate 7B is between the linear expansion coefficient αBA of the first buffer plate 7A and the linear expansion coefficient αW of the wiring member 4, The difference from the linear expansion coefficient αW of the member 4 has a linear expansion coefficient αBB that is larger than the first predetermined value and smaller than the second predetermined value. It is configured as follows ”(see summary).

特表平０８−５０９８４４号公報Japanese National Patent Publication No. 08-509844 特開２０１２−２８６７４号公報JP 2012-28684 A

パワーモジュールにおいて絶縁基板と放熱ベース板間のはんだ接合部（基板下接合部）の信頼性確保が課題となっている。パワーモジュールでは、通電によってチップが発熱する。そのため、ＯＮ／ＯＦＦが繰り返されることではんだ接合部に繰り返し温度変化が生じ、部材間の線膨張係数差によってはんだ接合部に繰り返しひずみが生じる。これにより、当該はんだ接合部の端部から破壊が生じる。接合部に破壊が生じると接合面積が減少し、放熱性が劣化するため、接合部温度が上昇して加速的に破壊が進行し、最終的にはパワーモジュールが破壊される。   In the power module, ensuring the reliability of the solder joint between the insulating substrate and the heat radiating base plate (joint under the substrate) is an issue. In the power module, the chip generates heat when energized. Therefore, when the ON / OFF is repeated, the temperature change is repeatedly generated in the solder joint portion, and the strain is repeatedly generated in the solder joint portion due to the difference in linear expansion coefficient between the members. Thereby, destruction arises from the edge part of the said solder joint part. When the joint portion is broken, the joint area is reduced and the heat dissipation is deteriorated. Therefore, the joint temperature rises and the breakage progresses at an accelerated speed, and finally the power module is broken.

一般的にチップおよび基板間の接合部と比較して、基板下接合部の方が部材間の線膨張係数差は小さい。しかし、上記のような接合部の破壊は、基板下接合部においても進展しやすい。その理由は、チップおよび基板間の接合部に比べて基板下接合部の接合面積が大きいため、基板下接合部の端部に生じるひずみ量は小さくないということにある。   In general, the difference in linear expansion coefficient between members is smaller in the lower substrate bonding portion than in the bonding portion between the chip and the substrate. However, the destruction of the joint portion as described above easily progresses even in the lower joint portion of the substrate. The reason is that since the bonding area of the lower substrate bonding portion is larger than the bonding portion between the chip and the substrate, the amount of strain generated at the end of the lower substrate bonding portion is not small.

特許文献１は、基板下接合部に低い降伏点を持つ金属の平板を挿入し、金属層が塑性変形することで高信頼化を実現しようとするものであるが、当該金属層が塑性変形すると接合部が大きく変形するため、より破壊が加速される可能性が考慮されていない。また、特許文献２は、チップ上のＡｌ（アルミニウム）配線接合部の信頼性を向上させるために、チップとＡｌ配線との間に線膨張係数を調整した金属板を挿入するものであるが、チップ接合部に比べて接合面積が著しく大きい基板下接合部に適用することが考慮されていない。   Patent Document 1 is intended to achieve high reliability by inserting a metal flat plate having a low yield point into the lower joint portion of the substrate and plastically deforming the metal layer, but when the metal layer is plastically deformed. Since the joint is greatly deformed, the possibility that the fracture is accelerated is not considered. In addition, Patent Document 2 is to insert a metal plate with a linear expansion coefficient adjusted between the chip and the Al wiring in order to improve the reliability of the Al (aluminum) wiring joint on the chip. It is not considered to be applied to a lower substrate bonding portion that has a significantly larger bonding area than the chip bonding portion.

また、薄い金属平板を基板下接合部に挿入した場合、片面を接合した段階で金属平板が大きく反り、その後の工程を行うことが困難になるとともに、金属平板が反ることによってはんだに生じるひずみが増えるため、半導体装置の信頼性が低下することも考慮されていない。   In addition, when a thin metal flat plate is inserted into the lower joint of the substrate, the metal flat plate warps greatly at the stage where one side is bonded, and it becomes difficult to perform the subsequent process. Therefore, it is not considered that the reliability of the semiconductor device is lowered.

本発明の上記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、以下のとおりである。   Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

代表的な実施の形態による半導体装置は、半導体チップを支持する配線基板と、配線基板を支持する金属板と、配線基板と金属板との間に配置されたひずみ低減用の金属板と、配線基板およびひずみ低減用金属板を接合する第１接合部と、金属板およびひずみ低減用金属板を接合する第２接合部とを有し、第２金属板の厚さは、その中央部よりも外周部の方が大きいものである。   A semiconductor device according to a typical embodiment includes a wiring board that supports a semiconductor chip, a metal plate that supports the wiring board, a metal plate for strain reduction that is disposed between the wiring board and the metal plate, and a wiring It has the 1st junction part which joins a board | substrate and the metal plate for distortion reduction, and the 2nd junction part which joins a metal plate and the metal plate for distortion reduction, The thickness of a 2nd metal plate is rather than the center part. The outer periphery is larger.

代表的な実施の形態によれば、半導体装置における信頼性を向上させることができる。   According to the representative embodiment, the reliability of the semiconductor device can be improved.

本発明の実施の形態１である半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device which is Embodiment 1 of this invention. 比較例の解析モデルを示す断面図である。It is sectional drawing which shows the analysis model of a comparative example. 比較例の解析モデルを示す平面図である。It is a top view which shows the analysis model of a comparative example. 図３のＡ−Ａ線における断面図である。It is sectional drawing in the AA of FIG. 比較例の解析モデルを示す断面図である。It is sectional drawing which shows the analysis model of a comparative example. 比較例の解析モデルを示す斜視図である。It is a perspective view which shows the analysis model of a comparative example. 本発明の実施の形態１の半導体装置に対応する解析モデルの断面図である。It is sectional drawing of the analysis model corresponding to the semiconductor device of Embodiment 1 of this invention. 本発明の実施の形態１の半導体装置に対応する解析モデルの平面図である。It is a top view of the analysis model corresponding to the semiconductor device of Embodiment 1 of this invention. 本発明の実施の形態１の半導体装置に対応する解析モデルの斜視図である。It is a perspective view of the analysis model corresponding to the semiconductor device of Embodiment 1 of this invention. 図９のＢ−Ｂ線における断面図である。It is sectional drawing in the BB line of FIG. 本発明の実施の形態１の変形例の半導体装置に対応する解析モデルの断面図である。It is sectional drawing of the analysis model corresponding to the semiconductor device of the modification of Embodiment 1 of this invention. 本発明の実施の形態１の変形例の半導体装置に対応する解析モデルの平面図である。It is a top view of the analysis model corresponding to the semiconductor device of the modification of Embodiment 1 of this invention. 本発明の実施の形態１の変形例の半導体装置に対応する解析モデルの斜視図である。It is a perspective view of the analysis model corresponding to the semiconductor device of the modification of Embodiment 1 of this invention. 図２のＣ−Ｃ線における断面図である。It is sectional drawing in the CC line of FIG. 接合部端部に生じるひずみ量の解析結果を示すグラフである。It is a graph which shows the analysis result of the distortion amount which arises in a junction part edge part. 接合部端部に生じるひずみ量の解析結果を示すグラフである。It is a graph which shows the analysis result of the distortion amount which arises in a junction part edge part. 接合部端部に生じるひずみ量の解析結果を示すグラフである。It is a graph which shows the analysis result of the distortion amount which arises in a junction part edge part. 本発明の実施の形態２である鉄道車両を示す側面図である。It is a side view which shows the rail vehicle which is Embodiment 2 of this invention. 本発明の実施の形態２である鉄道車両に設置されたインバータの内部構造を示す平面図である。It is a top view which shows the internal structure of the inverter installed in the rail vehicle which is Embodiment 2 of this invention. 本発明の実施の形態３である自動車を示す斜視図である。It is a perspective view which shows the motor vehicle which is Embodiment 3 of this invention. 比較例の半導体装置を示す断面図である。It is sectional drawing which shows the semiconductor device of a comparative example.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の機能を有する部材には同一の符号を付し、その繰り返しの説明は省略する。
（実施の形態１）Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.
(Embodiment 1)

図１は本発明の実施の形態の半導体装置（パワーモジュール）の構造の一例を示す断面図である。   FIG. 1 is a cross-sectional view showing an example of the structure of a semiconductor device (power module) according to an embodiment of the present invention.

本実施の形態の半導体装置は、例えば、鉄道の車両または自動車の車体等に搭載される半導体モジュール（パワーモジュール）である。つまり、当該パワーモジュールは、複数のパワー系の半導体チップ（半導体素子）１を備えており、放熱対策が必要な半導体装置である。半導体チップ１は、例えばＩＧＢＴ（Insulated Gate Bipolar Transistor）またはＭＯＳＦＥＴ（Metal Oxide Semiconductor Field Effect Transistor）等を搭載したものであるが、これに限定されるものではない。本願でいうパワー系の半導体チップ（半導体素子）とは、例えば電力用に用いられる素子であって、比較的大きい電圧および大きい電流を扱うことが可能な半導体素子を指す。また、そのような素子を含む装置をパワーモジュールと呼ぶ。   The semiconductor device according to the present embodiment is, for example, a semiconductor module (power module) mounted on a railway vehicle or an automobile body. In other words, the power module is a semiconductor device that includes a plurality of power semiconductor chips (semiconductor elements) 1 and requires heat dissipation measures. The semiconductor chip 1 is mounted with, for example, an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), but is not limited thereto. The power semiconductor chip (semiconductor element) in the present application refers to a semiconductor element that is used for power, for example, and can handle a relatively large voltage and large current. A device including such an element is called a power module.

図１に示すパワーモジュール２０の構成について説明する。パワーモジュール２０は、半導体チップ１と、半導体チップ１を支持するセラミック基板（配線基板）３とを有している。また、パワーモジュール２０は、半導体チップ１の上面（主面）の電極１ｃとセラミック基板３の上面の電極３ｃｂとを電気的に接続する導電性のワイヤ６を有し、また、セラミック基板３の電極３ｃｂに電気的に接続され、外部に引き出された端子（リード）７を有している。なお、図では半導体チップ１を１つのみ示しているが、セラミック基板３上には複数の半導体チップ１が配置されている。   A configuration of the power module 20 shown in FIG. 1 will be described. The power module 20 includes a semiconductor chip 1 and a ceramic substrate (wiring substrate) 3 that supports the semiconductor chip 1. The power module 20 includes a conductive wire 6 that electrically connects the electrode 1 c on the upper surface (main surface) of the semiconductor chip 1 and the electrode 3 cb on the upper surface of the ceramic substrate 3. It has a terminal (lead) 7 electrically connected to the electrode 3cb and drawn to the outside. Although only one semiconductor chip 1 is shown in the figure, a plurality of semiconductor chips 1 are arranged on the ceramic substrate 3.

複数の半導体チップ１および複数の端子７が搭載されたセラミック基板３は、はんだ（接合材、接合部、はんだ合金）５を介してベース板（金属板）４上に搭載されている。すなわち、ベース板４は、はんだ５を介して、ベース板４上のセラミック基板３を支持している。ここで、セラミック基板３の上面に接して、複数の電極３ｃａおよび複数の電極３ｃｂが形成されており、セラミック基板３の下面に接して、電極３ｃｃが形成されている。半導体チップ１は、はんだ２を介して電極３ｃａの上面に接着されている。セラミック基板３の材料には、熱伝導性の高いＡｌ（アルミニウム）、Ｃｕ（銅）、ＡｌＮ（窒化アルミニウム）またはＳｉ３Ｎ４（窒化シリコン）等の材料が使用されている。A ceramic substrate 3 on which a plurality of semiconductor chips 1 and a plurality of terminals 7 are mounted is mounted on a base plate (metal plate) 4 via solder (bonding material, bonding portion, solder alloy) 5. That is, the base plate 4 supports the ceramic substrate 3 on the base plate 4 via the solder 5. Here, a plurality of electrodes 3ca and a plurality of electrodes 3cb are formed in contact with the upper surface of the ceramic substrate 3, and an electrode 3cc is formed in contact with the lower surface of the ceramic substrate 3. The semiconductor chip 1 is bonded to the upper surface of the electrode 3ca through the solder 2. As the material of the ceramic substrate 3, a material such as Al (aluminum), Cu (copper), AlN (aluminum nitride) or Si 3 N 4 (silicon nitride) having high thermal conductivity is used.

これらの電極３ｃａ、３ｃｂおよび、３ｃｃは、例えば、ニッケル（Ｎｉ）メタライズからなる。すなわち、電極３ｃａ、３ｃｂおよび３ｃｃは、例えばＣｕまたはＡｌからなる電極をめっき処理することでニッケル膜により覆った構造を有している。そして、セラミック基板３の下面側に形成された電極３ｃｃは、はんだ５を介してベース板４に電気的に接続されている。   These electrodes 3ca, 3cb, and 3cc are made of, for example, nickel (Ni) metallization. That is, the electrodes 3ca, 3cb, and 3cc have a structure in which, for example, an electrode made of Cu or Al is covered with a nickel film by plating. The electrode 3 cc formed on the lower surface side of the ceramic substrate 3 is electrically connected to the base plate 4 via the solder 5.

平面視において、半導体チップ１よりもセラミック基板３の方が面積が大きく、セラミック基板３よりもベース板４の方が面積が大きい。よって、半導体チップ１とセラミック基板３とを接合するはんだ２よりも、セラミック基板３とベース板４とを接合するはんだ５の方が、平面視における面積が大きい。   In plan view, the ceramic substrate 3 has a larger area than the semiconductor chip 1, and the base plate 4 has a larger area than the ceramic substrate 3. Therefore, the solder 5 for joining the ceramic substrate 3 and the base plate 4 has a larger area in plan view than the solder 2 for joining the semiconductor chip 1 and the ceramic substrate 3.

すなわち、本実施の形態のパワーモジュール２０は、半導体チップ１が、はんだ２を介してセラミック基板（配線基板、絶縁性基板、被接続部材）３に接続されたものであり、さらに、半導体チップ１の動作時の熱を逃がす役割を果たす放熱用のベース板（金属板）４とセラミック基板３とが、はんだ５を介して接続されている。つまり、セラミック基板３とベース板４との間に配置されたはんだ５によってセラミック基板３とベース板４とが接合されている。ベース板４は放熱板としての役割を有するため、熱伝導性の高い金属板により構成されている。   That is, in the power module 20 of the present embodiment, the semiconductor chip 1 is connected to the ceramic substrate (wiring substrate, insulating substrate, connected member) 3 via the solder 2, and further, the semiconductor chip 1 A base plate (metal plate) 4 for heat release that plays a role of releasing heat during the operation of the ceramic substrate 3 and the ceramic substrate 3 are connected via a solder 5. That is, the ceramic substrate 3 and the base plate 4 are joined by the solder 5 disposed between the ceramic substrate 3 and the base plate 4. Since the base plate 4 has a role as a heat radiating plate, it is composed of a metal plate having high thermal conductivity.

パワーモジュール２０の具体的構造について説明すると、パワーモジュール２０は、半導体チップ１と、半導体チップ１に対してはんだ（接合材）２介して接続されたチップ支持部材であるセラミック基板３と、半導体チップ１と電気的に接続された複数のワイヤ６とを有している。セラミック基板３の基材の上面には、配線パターン等の一部である電極（導体部、配線部）３ｃａが形成され、この電極３ｃａ上にはんだ２を介して半導体チップ１が搭載されている。   The specific structure of the power module 20 will be described. The power module 20 includes a semiconductor chip 1, a ceramic substrate 3 that is a chip support member connected to the semiconductor chip 1 via a solder (joining material) 2, and a semiconductor chip. 1 and a plurality of wires 6 electrically connected. An electrode (conductor portion, wiring portion) 3ca that is a part of a wiring pattern or the like is formed on the upper surface of the base material of the ceramic substrate 3, and the semiconductor chip 1 is mounted on the electrode 3ca via the solder 2. .

また、放熱板でもあるベース板４、複数の半導体チップ１、複数のワイヤ６およびセラミック基板３は、ケース８により囲まれており、そのケース８内には図示しない封止用の樹脂が充填されている。すなわち、ベース板４の側壁に接して、平面視において矩形の環状構造を有する壁状のケース８が設けられており、半導体チップ１、複数のワイヤ６およびセラミック基板３等と、ケース８とは互いに離間している。複数の半導体チップ１、複数のワイヤ６およびセラミック基板３は、上記封止用の樹脂によって封止されている。上記樹脂は、例えばゲル状の樹脂材を用いることが好ましい。   The base plate 4, which is also a heat sink, the plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3 are surrounded by a case 8, and the case 8 is filled with a sealing resin (not shown). ing. That is, a wall-shaped case 8 having a rectangular annular structure in plan view is provided in contact with the side wall of the base plate 4. The semiconductor chip 1, the plurality of wires 6, the ceramic substrate 3, and the like, They are separated from each other. The plurality of semiconductor chips 1, the plurality of wires 6, and the ceramic substrate 3 are sealed with the sealing resin. For example, a gel-like resin material is preferably used as the resin.

また、半導体チップ１は、セラミック基板３の上面の電極３ｃａ上にはんだ２を介して接合されている。つまり、半導体チップ１の下面とセラミック基板３の上面とが対向しており、半導体チップ１の裏面電極とセラミック基板３の電極３ｃａとがはんだ２を介して電気的に接続されている。   The semiconductor chip 1 is bonded to the electrode 3ca on the upper surface of the ceramic substrate 3 via the solder 2. That is, the lower surface of the semiconductor chip 1 and the upper surface of the ceramic substrate 3 face each other, and the back electrode of the semiconductor chip 1 and the electrode 3 ca of the ceramic substrate 3 are electrically connected via the solder 2.

また、半導体チップ１の上面には、例えばゲート用の電極１ｃが形成されており、セラミック基板３の電極３ｃｂとワイヤ６を介して電気的に接続されている。端子７は、その一端が、セラミック基板３の上面側の電極３ｃｂに接合されており、さらに他端がケース８の外部に引き出されている。複数のワイヤ６のそれぞれは、例えばＡｌ線または銅線等からなる。   Also, for example, a gate electrode 1 c is formed on the upper surface of the semiconductor chip 1, and is electrically connected to the electrode 3 cb of the ceramic substrate 3 via a wire 6. One end of the terminal 7 is joined to the electrode 3 cb on the upper surface side of the ceramic substrate 3, and the other end is drawn out of the case 8. Each of the plurality of wires 6 is made of, for example, Al wire or copper wire.

そして、本実施の形態のパワーモジュール２０では、セラミック基板３の下面に配線部である電極３ｃｃが形成され、この電極３ｃｃの下面に接合材（接合部）であるはんだ５aを介してひずみ低減板である金属板９が接合されている。金属板９の下面には、接合材（接合部）であるはんだ５ｂを介して放熱用のベース板（金属板、放熱部材）４が接合されている。   In the power module 20 of the present embodiment, the electrode 3cc as a wiring portion is formed on the lower surface of the ceramic substrate 3, and the strain reduction plate is formed on the lower surface of the electrode 3cc via the solder 5a as a bonding material (bonding portion). A metal plate 9 is joined. A heat radiating base plate (metal plate, heat radiating member) 4 is joined to the lower surface of the metal plate 9 via solder 5b which is a joining material (joining portion).

すなわち、セラミック基板３とベース板４との間のはんだ５中に金属板９が挿入されており、はんだ５は、金属板９上のはんだ５ａと、金属板９の下のはんだ５ｂとを含んでいる。言い換えれば、ベース板４の上面は、ベース板４上に順に形成されたはんだ５ｂ、金属板９およびはんだ５ａを介してセラミック基板３の下面に接合されている。平面視において、はんだ５ａ、５ｂのそれぞれは、はんだ２よりも大きい面積を有している。   That is, the metal plate 9 is inserted into the solder 5 between the ceramic substrate 3 and the base plate 4, and the solder 5 includes a solder 5 a on the metal plate 9 and a solder 5 b under the metal plate 9. It is out. In other words, the upper surface of the base plate 4 is joined to the lower surface of the ceramic substrate 3 via the solder 5b, the metal plate 9, and the solder 5a that are sequentially formed on the base plate 4. In plan view, each of the solders 5 a and 5 b has a larger area than the solder 2.

上方から眺めた平面視における金属板９の大きさは、セラミック基板３の平面視における大きさと同じであるか、またはセラミック基板３の平面視における大きさより大きい。言い換えると、ひずみ低減材からなる金属板９の平面視での大きさは、セラミック基板３の平面視の大きさ以上であればよい。   The size of the metal plate 9 in plan view as viewed from above is the same as the size of the ceramic substrate 3 in plan view or larger than the size of the ceramic substrate 3 in plan view. In other words, the size of the metal plate 9 made of the strain reducing material in plan view may be larger than the size of the ceramic substrate 3 in plan view.

ここでは、ベース板４の上面に沿う方向におけるはんだ５ａ、５ｂのそれぞれの幅は、図１に示すように、当該方向におけるセラミック基板３の幅および金属板９の幅よりも小さい。ただし、はんだ５ｂの当該方向における幅は、当該方向のセラミック基板３の幅より大きくてもよく、当該方向の金属板９の幅より大きくてもよい。また、はんだ５ａの当該方向における幅は、当該方向のセラミック基板３の幅より大きくてもよい。   Here, the respective widths of the solders 5a and 5b in the direction along the upper surface of the base plate 4 are smaller than the width of the ceramic substrate 3 and the width of the metal plate 9 in the direction as shown in FIG. However, the width of the solder 5b in the direction may be larger than the width of the ceramic substrate 3 in the direction, or may be larger than the width of the metal plate 9 in the direction. Further, the width of the solder 5a in the direction may be larger than the width of the ceramic substrate 3 in the direction.

ここで、金属板９の外周部９ａの厚さは、金属板９の外周部９ａの内側の部分である内部（中央部）９ｂの厚さより大きい。ここでいう外周部９ａおよび内部９ｂは、それぞれ金属板９の一部である。外周部９ａとは、金属板９の上面または下面に沿う方向における端部、つまり、平面視における金属板９の端部を意味する。したがって、外周部９ａは平面視において金属板９の周縁に沿う環状構造を有し、平面視において内部９ｂは外周部９ａに囲まれている。本願でいう厚さとは、ベース板４の上面に対して垂直な方向における各物体の長さを指す。   Here, the thickness of the outer peripheral portion 9 a of the metal plate 9 is larger than the thickness of the inner (center portion) 9 b that is the inner portion of the outer peripheral portion 9 a of the metal plate 9. The outer peripheral portion 9a and the inner portion 9b here are a part of the metal plate 9, respectively. The outer peripheral portion 9a means an end portion in a direction along the upper surface or the lower surface of the metal plate 9, that is, an end portion of the metal plate 9 in a plan view. Therefore, the outer peripheral portion 9a has an annular structure along the periphery of the metal plate 9 in plan view, and the inner portion 9b is surrounded by the outer peripheral portion 9a in plan view. The thickness referred to in this application refers to the length of each object in the direction perpendicular to the upper surface of the base plate 4.

金属板９は厚さが均一な単なる平板ではなく、その外周部９ａの厚さが他の部分（内部９ｂ）の厚さよりも大きい形状を有している。ここでは、金属板９の底面の高さの位置は外周部９ａおよび内部９ｂのどちらにおいても同じであるが、外周部９ａの金属板９の上面は、内部９ｂの金属板９の上面よりも上に位置する。すなわち、金属板９の外周部９ａは、金属板９の内部９ｂに比べて上方に突出している。なお、本願でいう上方（上）とは、ベース板４の上面に対して垂直な方向における方向であって、ベース板４側からセラミック基板３側に向かう方向であり、本願でいう下方（下）は、当該上方とは反対側に向かう方向である。   The metal plate 9 is not a simple flat plate having a uniform thickness, but has a shape in which the thickness of the outer peripheral portion 9a is larger than the thickness of the other portion (inner portion 9b). Here, the height position of the bottom surface of the metal plate 9 is the same in both the outer peripheral portion 9a and the inner portion 9b, but the upper surface of the metal plate 9 in the outer peripheral portion 9a is higher than the upper surface of the metal plate 9 in the inner portion 9b. Located on the top. That is, the outer peripheral portion 9 a of the metal plate 9 protrudes upward as compared with the inner portion 9 b of the metal plate 9. The upper direction (upper) in the present application is a direction in a direction perpendicular to the upper surface of the base plate 4 and is a direction from the base plate 4 side to the ceramic substrate 3 side. ) Is a direction toward the opposite side to the upper side.

はんだ５ａの厚さが小さい場合に、上方に突出する外周部９ａとセラミック基板３とが接触すると、はんだ５ａにより電極３ｃｃと金属板９とを適切に接合することができなくなる虞がある。よって、金属板９の平面視における幅は、セラミック基板３の平面視における幅よりも大きいことが望ましい。言い換えれば、平面視においてセラミック基板３と重ならない位置、つまりセラミック基板３の外側に金属板９の外周部９ａが位置すれば、凸形状の外周部９ａとセラミック基板３とが接触することを防ぐことができる。   When the thickness of the solder 5a is small and the outer peripheral portion 9a protruding upward and the ceramic substrate 3 come into contact with each other, there is a possibility that the electrode 3cc and the metal plate 9 cannot be properly joined by the solder 5a. Therefore, the width of the metal plate 9 in plan view is desirably larger than the width of the ceramic substrate 3 in plan view. In other words, if the outer peripheral portion 9a of the metal plate 9 is positioned so as not to overlap the ceramic substrate 3 in plan view, that is, outside the ceramic substrate 3, the convex outer peripheral portion 9a and the ceramic substrate 3 are prevented from contacting each other. be able to.

すなわち、金属板９の内部９ｂの上面に対して外周部９ａがセラミック基板３側に突出した長さが、はんだ５ａの厚さよりも大きくても、外周部９ａとセラミック基板３とが接触することを防ぐことができる。言い換えれば、ベース板４の上面に対して垂直な方向において、金属板９の内部９ｂの上面から金属板９の外周部９ａの上面までの間の距離が、金属板９の内部９ｂの上面からセラミック基板３の下面までの間の距離より大きくても、外周部９ａとセラミック基板３とが接触することを防ぐことができる。   That is, the outer peripheral portion 9a and the ceramic substrate 3 are in contact with each other even if the length of the outer peripheral portion 9a protruding toward the ceramic substrate 3 with respect to the upper surface of the inner portion 9b of the metal plate 9 is larger than the thickness of the solder 5a. Can be prevented. In other words, in the direction perpendicular to the upper surface of the base plate 4, the distance from the upper surface of the inner portion 9 b of the metal plate 9 to the upper surface of the outer peripheral portion 9 a of the metal plate 9 is from the upper surface of the inner portion 9 b of the metal plate 9. Even if it is larger than the distance to the lower surface of the ceramic substrate 3, it can prevent that the outer peripheral part 9a and the ceramic substrate 3 contact.

また、金属板９の線膨張係数は、ベースベース板４の線膨張係数と回路付き絶縁基板であるセラミック基板３、の線膨張係数との間の値である。金属板９の材料には、例えばＣｕ（銅）およびＭｏ（モリブデン）の合金、またはＣｕおよびＭｏの積層膜などを用いることができる。また、金属板９の材料には、ＣＩＣ（銅／インバー／銅）を用いることもできる。金属板９の線膨張係数は、例えば上記ＣｕおよびＭｏの混合比を変更することで調整することが可能である。   The linear expansion coefficient of the metal plate 9 is a value between the linear expansion coefficient of the base base plate 4 and the linear expansion coefficient of the ceramic substrate 3 that is an insulating substrate with circuit. As the material of the metal plate 9, for example, an alloy of Cu (copper) and Mo (molybdenum), a laminated film of Cu and Mo, or the like can be used. Moreover, CIC (copper / invar / copper) can also be used for the material of the metal plate 9. The linear expansion coefficient of the metal plate 9 can be adjusted, for example, by changing the mixing ratio of Cu and Mo.

はんだ５ａ、５ｂは、好ましくは、Ｓｎ（錫）系はんだ合金からなり、例えば、Ｓｎ−Ｃｕ、Ｓｎ−Ｃｕ−Ｓｎ、Ｓｎ−Ｓｂ、または、Ｓｎ−Ａｇ−Ｃｕ等のＳｎ系はんだ合金からなる。さらに、はんだ５ａ、５ｂは、Ａｕ、Ａｇ、Ｃｕ若しくはＮｉ等の金属粒子による焼結接合、または、Ｚｎ−Ａｌ、Ａｕ−Ｇｅ若しくはＡｕ−Ｓｉ等の接合材により構成されていてもよい。また、はんだ５ａ、５ｂはそれぞれ異なる接合材により構成されていてもよい。   The solders 5a and 5b are preferably made of a Sn (tin) solder alloy, for example, a Sn solder alloy such as Sn—Cu, Sn—Cu—Sn, Sn—Sb, or Sn—Ag—Cu. . Furthermore, the solders 5a and 5b may be configured by sintered bonding using metal particles such as Au, Ag, Cu, or Ni, or a bonding material such as Zn—Al, Au—Ge, or Au—Si. The solders 5a and 5b may be composed of different bonding materials.

ここで、図２１を用いて比較例のモジュール構造を説明し、本実施の形態のパワーモジュール２０（図１参照）と上記比較例との違いを説明する。図２１は本発明者らが比較検討を行った比較例の半導体装置の構造を示す断面図である。   Here, the module structure of the comparative example will be described with reference to FIG. 21, and the difference between the power module 20 of the present embodiment (see FIG. 1) and the comparative example will be described. FIG. 21 is a cross-sectional view showing the structure of a semiconductor device of a comparative example that the present inventors have conducted a comparative study.

図２１に示す比較例の半導体装置であるモジュール（パワーモジュール５０）の構造は、セラミック基板３の下面側の電極３ｃｃとベース板４とがはんだ５ｃにより接合されている点、および、金属板９（図１参照）が設けられていない点を除いて、図１に示すパワーモジュール２０の構造と同様である。   The structure of the module (power module 50) which is the semiconductor device of the comparative example shown in FIG. 21 is that the electrode 3cc on the lower surface side of the ceramic substrate 3 and the base plate 4 are joined by the solder 5c, and the metal plate 9 The structure is the same as that of the power module 20 shown in FIG. 1 except that (see FIG. 1) is not provided.

高い電圧を扱うパワー系デバイスでは、当該デバイスが有する半導体素子のＯＮ状態およびＯＦＦ状態が繰り返し切り替わる際に、はんだ接合部に繰り返し温度変化が生じる。このとき、部材間の線膨張係数差に起因して、はんだ接合部に繰り返しひずみが生じることで、接合部に破壊が生じる問題がある。接合部に破壊が生じると接合面積が減少し、放熱性が劣化する。このため、接合部温度が上昇して加速的に破壊が進行し、最終的にはパワーモジュールが破壊される。特に、使用環境温度が高温になると、半導体装置（パワーモジュール）の半導体素子において電流の通電と遮断とが繰り返された際に、接合部に生じる熱応力が大きくなる。したがって、パワーモジュールでは、耐通電熱疲労性および環境温度の変化に対する耐亀裂進展性が要求される。   In a power device that handles a high voltage, when the ON state and the OFF state of a semiconductor element included in the device are repeatedly switched, a temperature change is repeatedly generated in the solder joint. At this time, due to the difference in linear expansion coefficient between the members, there is a problem in that the joint is broken due to repeated strain occurring in the solder joint. When breakage occurs in the joint, the joint area decreases and the heat dissipation deteriorates. For this reason, junction temperature rises and destruction progresses at an accelerated speed, and finally the power module is destroyed. In particular, when the use environment temperature is high, the thermal stress generated in the joint portion increases when current is repeatedly applied and interrupted in the semiconductor element of the semiconductor device (power module). Therefore, the power module is required to have resistance to energization thermal fatigue and resistance to crack propagation against changes in environmental temperature.

図２１に示すようなパワーモジュール５０では、発熱部である半導体チップ１に近い接合部、つまり、半導体チップ１とセラミック基板３とを接合するはんだ２のみならず、セラミック基板３の下の接合部においても破壊が生じ得る。つまり、セラミック基板３と放熱用のベース板４との接合部であるはんだ５ｃにおいても、半導体チップ１の動作に伴う半導体チップ１の発熱によって、温度上昇が起こる。   In the power module 50 as shown in FIG. 21, not only the joint portion close to the semiconductor chip 1 that is the heat generating portion, that is, the joint portion under the ceramic substrate 3 as well as the solder 2 that joins the semiconductor chip 1 and the ceramic substrate 3. Can also be destroyed. That is, even in the solder 5 c that is a joint portion between the ceramic substrate 3 and the heat radiating base plate 4, the temperature rises due to heat generation of the semiconductor chip 1 accompanying the operation of the semiconductor chip 1.

また、はんだ５ｃは、平面視において、はんだ２に比べて数倍以上の面積を有することが考えられる。この場合、温度の上昇とはんだ５ｃが大面積であることとに起因して、接合部であるはんだ５ｃの端部のひずみ量が著しく増加し、はんだ５ｃの当該端部から破壊が進展する。   Further, it is conceivable that the solder 5c has an area several times larger than that of the solder 2 in a plan view. In this case, due to the rise in temperature and the large area of the solder 5c, the amount of strain at the end of the solder 5c, which is a joint, increases significantly, and breakage progresses from the end of the solder 5c.

パワーモジュール５０ではその動作時に、半導体チップ１が発熱する。その際、セラミック基板３とベース板４の接合部であるはんだ５ｃにおいては、特に半導体チップ１の直下の部分において半導体チップ１とほぼ同等程度まで温度が上昇する。これは、セラミック基板３に熱伝導性の高いＡｌ、Ｃｕ、ＡｌＮまたはＳｉ３Ｎ４等の材料が使用されているためである。放熱経路であるはんだ５ｃにおいて破壊が進展すると放熱性が低下し、チップの温度が上昇してさらに破壊が加速する。このため、最終的にはパワーモジュール５０の破壊に至る。In the power module 50, the semiconductor chip 1 generates heat during its operation. At that time, the temperature of the solder 5c, which is a joint portion between the ceramic substrate 3 and the base plate 4, rises to a level substantially equal to that of the semiconductor chip 1 particularly in a portion immediately below the semiconductor chip 1. This is because the ceramic substrate 3 is made of a material having high thermal conductivity such as Al, Cu, AlN, or Si 3 N 4 . When breakage progresses in the solder 5c, which is a heat dissipation path, the heat dissipation is reduced, the chip temperature rises, and the breakage is further accelerated. For this reason, the power module 50 is eventually destroyed.

セラミック基板の下のはんだの端部からの破壊を抑制可能な接合方法として、接合後に高い機械的強度を有する焼結金属接合、または、Ａｕ（金）系はんだによる接合等が候補として想定される。ここで、焼結金属接合は、数ｎｍ〜数１００μｍの微細な金属粒子をアルコール等の溶剤でペースト状にしたものを用い、接合の際には加熱によって溶剤の除去を行い、また、加圧を行うことが必要である。   As a joining method capable of suppressing the breakage from the solder end portion under the ceramic substrate, a sintered metal joining having high mechanical strength after joining or joining with Au (gold) solder is assumed as a candidate. . Here, the sintered metal joint is made by pasting fine metal particles of several nm to several hundred μm in a paste form with a solvent such as alcohol, and the solvent is removed by heating at the time of joining. It is necessary to do.

しかしながら、セラミック基板３およびベース板４との間を接合する場合のように、大面積の接合を行う際には、接合部の面積が大きいため、接合部の中心部まで溶剤を除去することが難しく、適用が難しい。さらに、大きな加圧力が必要となり大規模な設備が必要となるため、大面積の接合部への適用は困難である。また、Ａｕ系はんだを適用した場合、Ａｕは高コストなため大面積の接合部に適用した場合コストが高くなるといった懸念がある。   However, when bonding a large area as in the case of bonding between the ceramic substrate 3 and the base plate 4, the area of the bonding portion is large, so that the solvent can be removed up to the center of the bonding portion. Difficult to apply. Furthermore, since a large pressing force is required and a large-scale facility is required, it is difficult to apply to a large-area joint. In addition, when Au-based solder is applied, there is a concern that Au is expensive, so that the cost increases when applied to a large-area joint.

これに対し、図１に示す本実施の形態のパワーモジュール２０では、セラミック基板（絶縁基板）３とベース板（放熱用金属板）４との間の大面積の接合部において、金属板９を挟み込むことで、はんだ ５ａ、５ｂの材質に関わらず、はんだ端部に発生するひずみを低減し、高信頼化を実現することができる。これは、セラミック基板３の線膨張係数と、ベース板４の線膨張係数との間の値の線膨張係数を有する材料からなる金属板９をセラミック基板３およびベース板４の間に挿入することで、セラミック基板３およびベース板４の間に生じるひずみを低減することができるためである。   On the other hand, in the power module 20 of the present embodiment shown in FIG. 1, the metal plate 9 is provided at the large-area joint between the ceramic substrate (insulating substrate) 3 and the base plate (heat radiating metal plate) 4. By sandwiching, regardless of the material of the solders 5a and 5b, distortion generated at the solder end can be reduced, and high reliability can be realized. This is because a metal plate 9 made of a material having a linear expansion coefficient between the linear expansion coefficient of the ceramic substrate 3 and the linear expansion coefficient of the base plate 4 is inserted between the ceramic substrate 3 and the base plate 4. This is because the strain generated between the ceramic substrate 3 and the base plate 4 can be reduced.

次に、図２〜図１７を用いて、本実施の形態における金属板９（図１参照）の外周部９ａが内部（内周部、中央部）９ｂよりも大きい厚さを有することの効果を、所定のモデルを用いて解析的に求めた結果に基づいて説明する。なお、本解析では、コンピュータでのシミュレーションソフトウェアを用い、公知の熱応力解析手法によりひずみの解析を行った。また、以下に示すモジュールは解析モデルであるため、実際に製品として用いられるパワーモジュールに比べ、セラミック基板上の電極のレイアウト等が異なる。図１５〜図１７は、接合部端部に生じるひずみ量の解析結果を示すグラフである。   Next, referring to FIGS. 2 to 17, the effect that the outer peripheral portion 9 a of the metal plate 9 (see FIG. 1) in the present embodiment has a larger thickness than the inner portion (inner peripheral portion, central portion) 9 b. Will be described based on analytical results obtained using a predetermined model. In this analysis, strain was analyzed by a known thermal stress analysis method using computer simulation software. Further, since the module shown below is an analysis model, the layout of electrodes on the ceramic substrate is different from that of a power module actually used as a product. 15-17 is a graph which shows the analysis result of the distortion amount which arises in a junction part edge part.

図２に比較例の解析モデルの端部の断面図を示す。図２に示す比較例の解析モデルのモジュールは、図２１を用いて説明した比較例と同様に、セラミック基板３の下面側の電極３ｃｃと、ベース板４との間にひずみ低減用の金属板を設けずに、電極３ｃｃおよびベース板４をはんだ５ｃにより接合させた構造を有している。図２において、ベース板４の厚さは５ｍｍ、はんだ５ｃの厚さは０．２ｍｍ、電極３ｃｃの厚さは０．３ｍｍ、セラミック基板３の厚さは０．６ｍｍ、セラミック基板３上の電極３ｃｂの厚さは０．２ｍｍである。   FIG. 2 shows a cross-sectional view of the end portion of the comparative analysis model. The analysis model module of the comparative example shown in FIG. 2 is a metal plate for strain reduction between the electrode 3cc on the lower surface side of the ceramic substrate 3 and the base plate 4 as in the comparative example described with reference to FIG. The electrode 3cc and the base plate 4 are joined by the solder 5c without providing the above. In FIG. 2, the thickness of the base plate 4 is 5 mm, the thickness of the solder 5c is 0.2 mm, the thickness of the electrode 3cc is 0.3 mm, the thickness of the ceramic substrate 3 is 0.6 mm, and the electrodes on the ceramic substrate 3 The thickness of 3cb is 0.2 mm.

また、もう一つの比較例の解析モデルを、図３〜図６に示す。図３は、比較例の解析モデルの平面図である。図４は、比較例の解析モデルの断面図である。図４は、図３のＡ−Ａ線における断面図である。図５は、比較例の解析モデルの端部を拡大して示す断面図である。図６は、比較例の解析モデルにおいてひずみ低減用に用いられる金属板１０の斜視図である。なお、図４の断面図では、ハッチングの図示を省略している。   Moreover, the analysis model of another comparative example is shown in FIGS. FIG. 3 is a plan view of an analysis model of a comparative example. FIG. 4 is a cross-sectional view of an analysis model of a comparative example. 4 is a cross-sectional view taken along line AA in FIG. FIG. 5 is an enlarged cross-sectional view of an end portion of the comparative analysis model. FIG. 6 is a perspective view of the metal plate 10 used for strain reduction in the analysis model of the comparative example. Note that hatching is not shown in the cross-sectional view of FIG.

平面視において、図３に示す電極３ｃｂの縦および横の寸法は、４４ｍｍ×５４ｍｍである。セラミック基板３の縦および横の寸法は、４８ｍｍ×５８ｍｍである。ベース板４の縦および横の寸法は、５２ｍｍ×６２ｍｍである。つまり、電極３ｃｂの平面視における面積よりも、セラミック基板３の平面視における面積の方が大きく、セラミック基板３の平面視における面積よりも、ベース板４の平面視における面積の方が大きい。このような電極３ｃｂ、セラミック基板３およびベース板４の面積の大小関係は、図２および図７〜図１４に示す解析モデルにおいても同様である。   In plan view, the vertical and horizontal dimensions of the electrode 3cb shown in FIG. 3 are 44 mm × 54 mm. The vertical and horizontal dimensions of the ceramic substrate 3 are 48 mm × 58 mm. The vertical and horizontal dimensions of the base plate 4 are 52 mm × 62 mm. That is, the area of the ceramic substrate 3 in plan view is larger than the area of the electrode 3cb in plan view, and the area of the base plate 4 in plan view is larger than the area of the ceramic substrate 3 in plan view. The magnitude relationship among the areas of the electrode 3cb, the ceramic substrate 3 and the base plate 4 is the same in the analysis models shown in FIG. 2 and FIGS.

また、図５に示す電極３ｃｂ、３ｃｃ、セラミック基板３およびベース板４のそれぞれの厚さは、図２を用いて説明したものと同様である。図２を用いて説明した解析モデルに対し、図５に示す解析モデルでは、セラミック基板３とベース板４との間に、ひずみ低減用の金属板１０を設けている。つまり、ベース板４上には、はんだ５ｂ、金属板１０、はんだ５ａ、電極３ｃｃおよびセラミック基板３が順に設けられている。平面視において、金属板１０の幅はセラミック基板３の幅よりも小さい。図５に示すはんだ５ａ、５ｃのそれぞれの厚さは０．１ｍｍであり、金属板１０の厚さは１ｍｍである。   The thicknesses of the electrodes 3cb and 3cc, the ceramic substrate 3 and the base plate 4 shown in FIG. 5 are the same as those described with reference to FIG. In contrast to the analysis model described with reference to FIG. 2, in the analysis model shown in FIG. 5, a metal plate 10 for strain reduction is provided between the ceramic substrate 3 and the base plate 4. That is, on the base plate 4, the solder 5b, the metal plate 10, the solder 5a, the electrode 3cc, and the ceramic substrate 3 are provided in this order. In plan view, the width of the metal plate 10 is smaller than the width of the ceramic substrate 3. The thickness of each of the solders 5a and 5c shown in FIG. 5 is 0.1 mm, and the thickness of the metal plate 10 is 1 mm.

図５および図６に示すように、金属板１０の厚さは、金属板１０の外周部から中央部に亘って均一である。つまり、金属板１０は、上面および下面が平坦な平板である。図６に示す金属板１０の縦および横の寸法は、４７ｍｍ×５７ｍｍである。   As shown in FIGS. 5 and 6, the thickness of the metal plate 10 is uniform from the outer periphery to the center of the metal plate 10. That is, the metal plate 10 is a flat plate whose upper surface and lower surface are flat. The vertical and horizontal dimensions of the metal plate 10 shown in FIG. 6 are 47 mm × 57 mm.

図７〜図１０には、本実施の形態の半導体装置に対応する解析モデルを示す。当該解析モデルは、図１に示す構造と同様に、外周部９ａが内部９ｂより厚い金属板９を含むものである。図７は、当該解析モデルの端部を拡大して示す断面図である。図８は、当該解析モデルを示す平面図である。図９は、当該解析モデルを示す斜視図である。図１０は、当該解析モデルが有する金属板９の端部を示す断面図である。図１０は、図８のＢ−Ｂ線における断面図である。   7 to 10 show analysis models corresponding to the semiconductor device of this embodiment. Similar to the structure shown in FIG. 1, the analysis model includes a metal plate 9 in which the outer peripheral portion 9a is thicker than the inner portion 9b. FIG. 7 is an enlarged cross-sectional view showing an end portion of the analysis model. FIG. 8 is a plan view showing the analysis model. FIG. 9 is a perspective view showing the analysis model. FIG. 10 is a cross-sectional view showing an end portion of the metal plate 9 included in the analysis model. 10 is a cross-sectional view taken along line BB in FIG.

図７に示す電極３ｃｂ、３ｃｃ、セラミック基板３およびベース板４のそれぞれの厚さは、図２を用いて説明したものと同様である。また、はんだ５ａ、５ｂのそれぞれの厚さは０．１ｍｍである。図８〜図１０に示す金属板９の平面視における縦および横の寸法は、５１ｍｍ×６１ｍｍである。金属板９の外周部９ａの幅は、１．２５ｍｍである。よって、金属板９の内部（中央部）９ｂの平面視における縦および横の寸法は、４８．５ｍｍ×５８．５ｍｍである。図１０に示す金属板９の内部９ｂの厚さは１ｍｍであり、外周部９ａの厚さは１．５ｍｍである。ここでいう外周部９ａの幅とは、金属板９の４辺のそれぞれに沿う外周部９ａの延在方向に対して直交する方向における外周部９ａの長さを指す。   The thicknesses of the electrodes 3cb and 3cc, the ceramic substrate 3 and the base plate 4 shown in FIG. 7 are the same as those described with reference to FIG. The thickness of each of the solders 5a and 5b is 0.1 mm. The vertical and horizontal dimensions in plan view of the metal plate 9 shown in FIGS. 8 to 10 are 51 mm × 61 mm. The width of the outer peripheral portion 9a of the metal plate 9 is 1.25 mm. Therefore, the vertical and horizontal dimensions in plan view of the inside (center portion) 9b of the metal plate 9 are 48.5 mm × 58.5 mm. The thickness of the inner part 9b of the metal plate 9 shown in FIG. 10 is 1 mm, and the thickness of the outer peripheral part 9a is 1.5 mm. The width | variety of the outer peripheral part 9a here refers to the length of the outer peripheral part 9a in the direction orthogonal to the extension direction of the outer peripheral part 9a along each of 4 sides of the metal plate 9. As shown in FIG.

図１１〜図１４に、図７〜図１０を用いて説明した解析モデルの変形例の解析モデルを示す。つまり、図１１〜図１４には、本実施の形態の半導体装置の変形例に対応する解析モデルを示す。図１１は、当該解析モデルの端部を拡大して示す断面図である。図１２は、当該解析モデルを示す平面図である。図１３は、当該解析モデルを示す斜視図である。図１４は、当該解析モデルが有する金属板１３の端部を示す断面図である。図１４は、図１２のＣ−Ｃ線における断面図である。   FIGS. 11 to 14 show analysis models of modifications of the analysis model described with reference to FIGS. 7 to 10. In other words, FIGS. 11 to 14 show analysis models corresponding to modifications of the semiconductor device of the present embodiment. FIG. 11 is an enlarged cross-sectional view showing an end portion of the analysis model. FIG. 12 is a plan view showing the analysis model. FIG. 13 is a perspective view showing the analysis model. FIG. 14 is a cross-sectional view showing an end portion of the metal plate 13 included in the analysis model. 14 is a cross-sectional view taken along the line CC of FIG.

当該解析モデルの構造および寸法は、図７〜図１０を用いて説明した解析モデルとほぼ同様であるが、図１１および図１４に示すように、金属板１３の外周部１３ａの底部が、金属板１３の内部１３ｂの底部に比べて下方に突出している点が、図７〜図１０を用いて説明した解析モデルと異なる。つまり、金属板１３の外周部１３ａは、１ｍｍの厚さを有する内部１３ｂに比べ、上方に０．５ｍｍ突出し、かつ、下方に０．０５ｍｍ突出している。よって、外周部１３ａの厚さは１．５５ｍｍである。   The structure and dimensions of the analysis model are substantially the same as those of the analysis model described with reference to FIGS. 7 to 10. However, as shown in FIGS. 11 and 14, the bottom of the outer peripheral portion 13 a of the metal plate 13 is made of metal. The point which protrudes below compared with the bottom part of the inside 13b of the board 13 differs from the analysis model demonstrated using FIGS. That is, the outer peripheral portion 13a of the metal plate 13 protrudes upward by 0.5 mm and protrudes downward by 0.05 mm compared to the inner portion 13b having a thickness of 1 mm. Therefore, the thickness of the outer peripheral portion 13a is 1.55 mm.

解析条件として、半導体モジュールに生じる温度変化を再現するため、モジュール全体を２５℃から１７５℃まで昇温させた。その際の各部材の線膨張係数などの機械的強度の違いによってはんだ５、５ａ、５ｂまたは５ｃに生じる最大のひずみ量を計算し、図２〜図１４の解析モデルを比較した。なお、配線でもある電極３ｃｂ、３ｃｃは、密度８９２０ｋｇ／ｍ３、線膨張係数１．７×１０−５、ヤング率１３０ＧＰａ、ポアソン比０．３とした。セラミック基板３は、密度３３００ｋｇ／ｍ３、線膨張係数４．５×１０−６、ヤング率３２０ＧＰａ、ポアソン比０．２４とした。ベースベース板４は、密度２９００ｋｇ／ｍ３、線膨張係数７．８×１０−６、ヤング率１５０ＧＰａ、ポアソン比０．３とした。はんだ５、５ａ〜５ｃは、密度７３００ｋｇ／ｍ３、線膨張係数２．２×１０−５、ヤング率４０、ポアソン比０．３とした。As an analysis condition, the temperature of the entire module was raised from 25 ° C. to 175 ° C. in order to reproduce the temperature change occurring in the semiconductor module. The maximum amount of strain generated in the solder 5, 5 a, 5 b, or 5 c due to the difference in mechanical strength such as the linear expansion coefficient of each member at that time was calculated, and the analysis models of FIGS. 2 to 14 were compared. The electrodes 3cb and 3cc, which are also wirings, had a density of 8920 kg / m 3 , a linear expansion coefficient of 1.7 × 10 −5 , a Young's modulus of 130 GPa, and a Poisson's ratio of 0.3. The ceramic substrate 3 had a density of 3300 kg / m 3 , a linear expansion coefficient of 4.5 × 10 −6 , a Young's modulus of 320 GPa, and a Poisson's ratio of 0.24. The base base plate 4 had a density of 2900 kg / m 3 , a linear expansion coefficient of 7.8 × 10 −6 , a Young's modulus of 150 GPa, and a Poisson's ratio of 0.3. The solders 5, 5a to 5c had a density of 7300 kg / m 3 , a linear expansion coefficient of 2.2 × 10 −5 , a Young's modulus of 40, and a Poisson's ratio of 0.3.

また、金属板９、１０および１３は、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数と、ベース板４の線膨張係数との間の値の線膨張係数を有する。すなわち、金属板９、１０および１３には、密度９０５７ｋｇ／ｍ３、線膨張係数８．５×１０−６、ヤング率２２５ＧＰａ、ポアソン比０．３の材料を用いて解析を行った。なお、ここでいうセラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数とは、セラミック基板３、電極３ｃｂおよび３ｃｃを含む構造体の全体の線膨張係数を指す。Further, the metal plates 9, 10 and 13 have a linear expansion coefficient which is a value between the linear expansion coefficient of the ceramic substrate 3 and the electrodes 3 cb and 3 cc and the linear expansion coefficient of the base plate 4. That is, the metal plates 9, 10 and 13 were analyzed using materials having a density of 9057 kg / m 3 , a linear expansion coefficient of 8.5 × 10 −6 , a Young's modulus of 225 GPa, and a Poisson's ratio of 0.3. The linear expansion coefficient of the ceramic substrate 3 and the electrodes 3cb and 3cc here refers to the overall linear expansion coefficient of the structure including the ceramic substrate 3, the electrodes 3cb and 3cc.

また、金属板９、１０および１３が、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数と、ベース板４の線膨張係数との間の値以外の値の線膨張係数を有する場合についても解析を行った。つまり、金属板９、１０および１３が、ベース板４密度８９２０ｋｇ／ｍ３、線膨張係数１．７×１０−５、ヤング率１３０ＧＰａ、ポアソン比０．３の材料からなる場合についても解析を行った。金属板９、１０および１３の線膨張係数の値が、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数と、ベース板４の線膨張係数との間の値である場合とそうでない場合との２種類の材料を用いた比較結果は、図１６を用いて後述する。Further, analysis is also performed in the case where the metal plates 9, 10 and 13 have a linear expansion coefficient other than the value between the linear expansion coefficient of the ceramic substrate 3, the electrodes 3 cb and 3 cc and the linear expansion coefficient of the base plate 4. Went. That is, the analysis is also performed when the metal plates 9, 10 and 13 are made of a material having a base plate 4 density of 8920 kg / m 3 , a linear expansion coefficient of 1.7 × 10 −5 , a Young's modulus of 130 GPa, and a Poisson's ratio of 0.3. It was. When the value of the linear expansion coefficient of the metal plates 9, 10 and 13 is a value between the linear expansion coefficient of the ceramic substrate 3, the electrodes 3cb and 3cc and the linear expansion coefficient of the base plate 4, or not Comparison results using the two types of materials will be described later with reference to FIG.

図１５にひずみ低減用の金属板の有無および内部より外周部が厚い金属板を適用した場合の解析結果を示す。図１５は、縦軸に、セラミック基板およびベース板間の接合部の端部における最大ひずみ量の比を表わした棒グラフである。図１５では、左から順に、金属板が無い場合（図２参照）の解析結果のグラフＸ１、厚さが均一な金属板を有する場合（図３〜図６参照）の解析結果のグラフＸ２、外周部が上方に突出している金属板を有する場合（図７〜図１０参照）の解析結果のグラフＹ１、および、外周部が上方および下方に突出している金属板を有する場合（図１１〜図１４参照）の解析結果のグラフＹ２を示している。   FIG. 15 shows the result of analysis in the case where the presence or absence of a metal plate for strain reduction and a metal plate having a thicker outer periphery than the inside are applied. FIG. 15 is a bar graph showing the ratio of the maximum strain amount at the end of the joint between the ceramic substrate and the base plate on the vertical axis. In FIG. 15, in order from the left, a graph X1 of the analysis result when there is no metal plate (see FIG. 2), a graph X2 of the analysis result when there is a metal plate having a uniform thickness (see FIGS. 3 to 6), Graph Y1 of the analysis result when the outer peripheral portion has a metal plate protruding upward (see FIGS. 7 to 10), and the case where the outer peripheral portion has a metal plate protruding upward and downward (FIGS. 11 to 11) 14) is a graph Y2 of the analysis result.

すなわち、図１５の左側の２つのグラフＸ１、Ｘ２は、比較例の解析モデルを用いたひずみ量の比を示すものであり、右側の２つのグラフＹ１、Ｙ２は、本実施の形態の半導体装置の構造に対応する解析モデルを用いたひずみ量の比を示すものである。ここでは、図１５の一番左側のグラフＸ１のひずみ量、つまり金属板が無い場合（図２参照）のひずみ量を基準として、他の解析結果のひずみ量の比を示している。つまり、金属板が無い場合（図２参照）のひずみ量の比を、グラフＸ１に表わされているように、１００％に設定している。   That is, the two graphs X1 and X2 on the left side of FIG. 15 show the ratio of strain amounts using the analysis model of the comparative example, and the two graphs Y1 and Y2 on the right side show the semiconductor device of the present embodiment. The ratio of the strain amount using the analysis model corresponding to the structure of is shown. Here, the distortion amount ratio of other analysis results is shown based on the strain amount of the leftmost graph X1 in FIG. 15, that is, the strain amount when there is no metal plate (see FIG. 2). That is, when there is no metal plate (see FIG. 2), the strain ratio is set to 100% as shown in the graph X1.

これに対し、他の比較例の解析結果であるグラフＸ２では、図５に示す金属板１０をセラミック基板３の下の接合部に挿入しているにもかかわらず、殆どひずみ量が低減されていない。これは、金属板１０の機械的強度が低いことに起因して、金属板１０が塑性変形することに原因がある。このように金属板１０が変形すると、接合部が大きく変形するため、接合部を構成するはんだ５ａ、５ｂの破壊がより加速されることが懸念される。   On the other hand, in the graph X2 which is an analysis result of another comparative example, the strain amount is almost reduced despite the metal plate 10 shown in FIG. Absent. This is because the metal plate 10 is plastically deformed due to the low mechanical strength of the metal plate 10. When the metal plate 10 is deformed in this manner, the joint portion is greatly deformed, and there is a concern that the destruction of the solders 5a and 5b constituting the joint portion may be further accelerated.

また、金属板１０の上記のような変形は、半導体装置の製造工程において、金属板１０をセラミック基板３側またはベース板４側のどちらかに接合した段階で、金属板１０が大きく反ることで起こる。その場合、その後の工程で金属板１０に他方の部材（セラミック基板３またはベース板４）を接合することが困難になるとともに、金属板１０が反ることによってはんだ５ａ、５ｂに生じるひずみが増える。このため、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数と、ベース板４の線膨張係数との間の値の線膨張係数を有する金属板１０を設けても、図１５のグラフＸ２に示すように、殆どひずみ量を低減することができない。   In addition, the deformation of the metal plate 10 greatly warps the metal plate 10 when the metal plate 10 is bonded to either the ceramic substrate 3 side or the base plate 4 side in the manufacturing process of the semiconductor device. Happens at. In that case, it becomes difficult to join the other member (the ceramic substrate 3 or the base plate 4) to the metal plate 10 in the subsequent process, and the distortion generated in the solders 5a and 5b due to warpage of the metal plate 10 increases. . For this reason, even if the metal plate 10 having a linear expansion coefficient between the linear expansion coefficient of the ceramic substrate 3, the electrodes 3cb and 3cc and the linear expansion coefficient of the base plate 4 is provided, it is shown in the graph X2 of FIG. As described above, the amount of strain can hardly be reduced.

これに対し、本実施の形態の半導体装置（図１参照）に対応する解析モデル（図７〜図１０参照）のひずみ量は、グラフＹ１に示すように、グラフＸ１、Ｘ２に比べて大きく低減されている。これは、図１および図７〜図１０に示すように、セラミック基板３およびベース板４間に挿入する金属板９の構造を、図３〜図６を用いて説明した比較例の金属板１０のように平坦な構造とするのではなく、外周部９ａを内部（中央部）９ｂよりも厚い構造としているためである。   On the other hand, the strain amount of the analysis model (see FIGS. 7 to 10) corresponding to the semiconductor device of the present embodiment (see FIG. 1) is greatly reduced as compared to the graphs X1 and X2, as shown in the graph Y1. Has been. As shown in FIGS. 1 and 7 to 10, the structure of the metal plate 9 inserted between the ceramic substrate 3 and the base plate 4 is compared with the metal plate 10 of the comparative example described with reference to FIGS. This is because the outer peripheral portion 9a is thicker than the inner portion (center portion) 9b.

すなわち、本実施の形態では、金属板９の外周部９ａに枠状の厚い部分を設けることで、金属板９の機械的強度を高めている。このため、半導体装置の製造工程において、薄い金属板９に塑性変形が生じることを防ぐことができ、さらに、パワーモジュール２０（図１参照）の使用により、セラミック基板３およびベース板４間に繰り返し熱応力が加わっても、金属板９、はんだ５ａおよび５ｂを含む接合部が変形することを防ぐことができる。   That is, in this embodiment, the mechanical strength of the metal plate 9 is increased by providing a thick frame-like portion on the outer peripheral portion 9 a of the metal plate 9. For this reason, it is possible to prevent the thin metal plate 9 from being plastically deformed in the manufacturing process of the semiconductor device. Further, by using the power module 20 (see FIG. 1), it is repeated between the ceramic substrate 3 and the base plate 4. Even if thermal stress is applied, it is possible to prevent the joint portion including the metal plate 9 and the solders 5a and 5b from being deformed.

したがって、セラミック基板３の下の接合部にひずみが生じることを防ぐことができるため、接合部の端部がひずみにより破壊されて放熱の効率が低下し、パワーモジュール２０がさらに加熱されやすくなることに起因して、パワーモジュール２０が破壊されることを防ぐことができる。よって、半導体装置の信頼性を向上させることができる。   Therefore, since it can prevent that a distortion | strain arises in the junction part under the ceramic substrate 3, the edge part of a junction part is destroyed by a distortion, the efficiency of heat dissipation falls, and the power module 20 becomes further easy to heat. Due to this, it is possible to prevent the power module 20 from being destroyed. Thus, the reliability of the semiconductor device can be improved.

なお、半導体チップ１（図１参照）の放熱を効率的に行う観点から、はんだ５ａ、５ｂおよび金属板９のそれぞれの厚さは極力小さいことが望ましい。また、セラミック基板３とベース板４との接合強度を高めるため、はんだ５ａ、５ｂのそれぞれの厚さは小さい方が望ましい。したがって、単に金属板１０（図５参照）の厚さを増大することで金属板１０の強度を高めることは困難である。これに対し本実施の形態では、セラミック基板３とは重ならない領域（外周部９ａ）において金属板９の厚さを大きくし、これにより金属板９の強度を高めることを可能としている。   From the viewpoint of efficiently radiating heat from the semiconductor chip 1 (see FIG. 1), it is desirable that the thicknesses of the solders 5a and 5b and the metal plate 9 are as small as possible. Further, in order to increase the bonding strength between the ceramic substrate 3 and the base plate 4, it is desirable that the thickness of each of the solders 5a and 5b is small. Therefore, it is difficult to increase the strength of the metal plate 10 simply by increasing the thickness of the metal plate 10 (see FIG. 5). On the other hand, in the present embodiment, the thickness of the metal plate 9 is increased in a region that does not overlap with the ceramic substrate 3 (outer peripheral portion 9a), thereby increasing the strength of the metal plate 9.

また、金属板９の内部９ｂの厚さの増大を抑えつつ、金属板９の強度を高める構造としては、金属板９の外周部９ａを下方に大きく突出させることが考えられる。しかし、はんだ５ｂの厚さは０．１ｍｍまたは０．２ｍｍ程度であるため、金属板９の外周部９ａが下方に大きく突出していると、金属板９とベース板４とを接合することが困難となる。したがって、金属板９の外周部９ａを下方のみに突出させて金属板９の強度を高めることはできない。   Further, as a structure for increasing the strength of the metal plate 9 while suppressing an increase in the thickness of the inside 9b of the metal plate 9, it is conceivable that the outer peripheral portion 9a of the metal plate 9 is greatly protruded downward. However, since the thickness of the solder 5b is about 0.1 mm or 0.2 mm, it is difficult to join the metal plate 9 and the base plate 4 if the outer peripheral portion 9a of the metal plate 9 protrudes greatly downward. It becomes. Therefore, the strength of the metal plate 9 cannot be increased by causing the outer peripheral portion 9a of the metal plate 9 to protrude only downward.

これに対し本実施の形態では、厚くした金属板９の一部がベース板４に接触しないように、上方に外周部９ａを突出させているため、金属板９とベース板４とを接合することが困難となることを防ぐことができる。   On the other hand, in this embodiment, since the outer peripheral portion 9a protrudes upward so that a part of the thickened metal plate 9 does not contact the base plate 4, the metal plate 9 and the base plate 4 are joined. Can be prevented from becoming difficult.

ここで、本実施の形態の半導体装置の変形例に対応する解析モデル（図１１〜図１４参照）のひずみ量は、グラフＹ２に示すように、グラフＸ１、Ｘ２に比べて大きく低減されている。当該変形例は、図１１〜図１４に示すように、金属板１３の一部をベース板４側、つまり下方にも突出させるものであるが、外周部１３ａが下方へ突出する長さが、はんだ５ｂの厚さよりも小さい大きさであれば、金属板１３とベース板４とを接合することが困難となることを防ぎつつ、金属板１３の機械的強度を高めることができる。言い換えれば、金属板１３の内部１３ｂの底面に対して外周部１３ａがベース板４側に突出した長さは、はんだ５ｂの厚さよりも小さい。   Here, as shown in the graph Y2, the strain amount of the analysis model (see FIGS. 11 to 14) corresponding to the modification of the semiconductor device of the present embodiment is greatly reduced compared to the graphs X1 and X2. . As shown in FIGS. 11 to 14, the modified example is such that a part of the metal plate 13 protrudes to the base plate 4 side, that is, the lower side, but the length of the outer peripheral portion 13 a protruding downward is as follows. If the size is smaller than the thickness of the solder 5b, the mechanical strength of the metal plate 13 can be increased while preventing the metal plate 13 and the base plate 4 from being difficult to join. In other words, the length that the outer peripheral portion 13a protrudes toward the base plate 4 with respect to the bottom surface of the inside 13b of the metal plate 13 is smaller than the thickness of the solder 5b.

なお、図７に示す金属板９の線膨張係数の値が、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数と、ベース板４の線膨張係数との間の値でない場合であっても、図１５のグラフＹ１に示すように、金属板９の外周部９ａの厚さを大きくして金属板９の機械的強度を高めることで、セラミック基板３の下の接合部の端部においてひずみが生じることを防ぐことができる。図１１〜図１４を用いて説明した変形例についても同様である。   Even if the value of the linear expansion coefficient of the metal plate 9 shown in FIG. 7 is not a value between the linear expansion coefficient of the ceramic substrate 3, the electrodes 3cb and 3cc, and the linear expansion coefficient of the base plate 4, As shown in the graph Y1 of FIG. 15, by increasing the thickness of the outer peripheral portion 9a of the metal plate 9 and increasing the mechanical strength of the metal plate 9, distortion is caused at the end of the joint portion under the ceramic substrate 3. It can be prevented from occurring. The same applies to the modification described with reference to FIGS.

つまり、平面視において、はんだ５ａ、５ｂを含む接合部（図１に示すはんだ５）は、はんだ２よりも大きい面積を有しており、大きな面積に起因して熱応力が増大しやすい箇所であるが、上記のような金属板９を設けることにより、鉛フリーで、かつ、高い耐熱性を有し、高信頼の接合部を有する半導体装置を実現することができる。   That is, in a plan view, the joint portion (solder 5 shown in FIG. 1) including the solders 5a and 5b has a larger area than the solder 2, and is a place where thermal stress is likely to increase due to the large area. However, by providing the metal plate 9 as described above, it is possible to realize a semiconductor device having a lead-free, high heat resistance, and highly reliable joint.

図１６に、金属板９（図７参照）の材料に、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数とベース板４の間の線膨張係数を持つ金属を用いない場合の解析結果のグラフＡ１と、金属板９の材料に、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数とベース板４の間の線膨張係数を持つ金属を用いた場合の解析結果のグラフＢ１とを示す。図１６は、縦軸に、セラミック基板およびベース板間の接合部の端部における最大ひずみ量の比を表わした棒グラフである。   FIG. 16 is a graph of analysis results in the case where a metal having a linear expansion coefficient between the ceramic substrate 3, the electrodes 3cb and 3cc and the linear expansion coefficient between the base plate 4 is not used as the material of the metal plate 9 (see FIG. 7). A1 and a graph B1 of an analysis result in the case where a metal having a linear expansion coefficient between the ceramic substrate 3, the electrodes 3cb and 3cc and the linear expansion coefficient between the base plate 4 are used as the material of the metal plate 9 are shown. FIG. 16 is a bar graph showing the ratio of the maximum strain amount at the end of the joint between the ceramic substrate and the base plate on the vertical axis.

図１６のグラフＢ１に示すように、金属板９（図７参照）の部材に、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数とベース板４の線膨張係数との間の線膨張係数を持つ金属を用いることで、グラフＡ１の場合に比べて、ひずみを大きく低減することができる。金属板９の材料に、セラミック基板３、電極３ｃｂおよび３ｃｃの線膨張係数とベース板４の線膨張係数との間の線膨張係数を持つ金属を用いることで、図７に示す金属板９が、セラミック基板３とベース板４との間の線膨張係数の差に起因して生じる応力の緩衝層として働くためである。   As shown in the graph B1 of FIG. 16, the member of the metal plate 9 (see FIG. 7) has a linear expansion coefficient between the linear expansion coefficient of the ceramic substrate 3, the electrodes 3 cb and 3 cc and the linear expansion coefficient of the base plate 4. By using the metal which has, compared with the case of graph A1, distortion can be reduced significantly. By using a metal having a linear expansion coefficient between the linear expansion coefficient of the ceramic substrate 3, the electrodes 3cb and 3cc and the linear expansion coefficient of the base plate 4 as the material of the metal plate 9, the metal plate 9 shown in FIG. This is because it acts as a buffer layer for the stress caused by the difference in linear expansion coefficient between the ceramic substrate 3 and the base plate 4.

また、図１７に、図７に示す接合部であるはんだ５ａ、５ｂのそれぞれの厚さが同じ場合と異なる場合との解析結果を示す。図１７は、縦軸に、セラミック基板およびベース板間の接合部の端部における最大ひずみ量の比を表わした棒グラフである。図１７では、左から順に、はんだ５ａ、５ｂのそれぞれの厚さが同じ場合におけるグラフＣ１、はんだ５ａの厚さがはんだ５ｂの厚さより大きい場合のグラフＤ１、および、はんだ５ａの厚さがはんだ５ｂの厚さより小さい場合のグラフＥ１を示している。   FIG. 17 shows analysis results when the thicknesses of the solders 5a and 5b, which are the joints shown in FIG. 7, are the same and different. FIG. 17 is a bar graph showing the ratio of the maximum strain amount at the end of the joint between the ceramic substrate and the base plate on the vertical axis. In FIG. 17, in order from the left, graph C1 when the thickness of each of the solders 5a and 5b is the same, graph D1 when the thickness of the solder 5a is larger than the thickness of the solder 5b, and the thickness of the solder 5a is the solder The graph E1 in the case where the thickness is smaller than 5b is shown.

図１７に示すように、本発明者らは解析により、はんだ５ａ、５ｂの厚さが互いに同じ場合（グラフＣ１参照）に比べはんだ５ａ、５ｂの厚さが異なっている場合（グラフＤ１参照）でもひずみは増大しないこと、および、はんだ５ａの厚さがはんだ５ｂの厚さより小さい場合においてひずみが低減されることを確認した。したがって、はんだ５ｂの厚さをはんだ５ａの厚さより大きくすることで、ひずみの発生を防ぎ、これにより半導体装置の信頼性を向上させることができる。
（実施の形態２）As shown in FIG. 17, the present inventors have analyzed that when the thicknesses of the solders 5a and 5b are the same (see graph C1), the thicknesses of the solders 5a and 5b are different (see graph D1). However, it was confirmed that the strain does not increase and that the strain is reduced when the thickness of the solder 5a is smaller than the thickness of the solder 5b. Therefore, by making the thickness of the solder 5b larger than the thickness of the solder 5a, the occurrence of distortion can be prevented, thereby improving the reliability of the semiconductor device.
(Embodiment 2)

図１８は、図１に示す半導体装置（図１参照）が搭載された鉄道車両を部分的に示す側面図であり、図１９は、図１８に示す鉄道車両に設置されたインバータの内部構造を示す平面図である。   18 is a side view partially showing a railway vehicle on which the semiconductor device (see FIG. 1) shown in FIG. 1 is mounted. FIG. 19 shows the internal structure of the inverter installed in the railway vehicle shown in FIG. FIG.

本実施の形態では、上記実施の形態のパワーモジュール２０（図１参照）を搭載した鉄道車両について説明する。図１８に示す鉄道車両２１は、例えば、図１に示すパワーモジュール２０が搭載されたものであり、車両本体２６と、集電装置であるパンタグラフ２２と、インバータ２３とを備えている。パワーモジュール２０は、車両本体２６の下部に設置されたインバータ２３に搭載されている（図１８および図１９参照）。   In the present embodiment, a railway vehicle equipped with the power module 20 (see FIG. 1) of the above embodiment will be described. A railcar 21 shown in FIG. 18 is mounted with the power module 20 shown in FIG. 1, for example, and includes a vehicle body 26, a pantograph 22 that is a current collector, and an inverter 23. The power module 20 is mounted on an inverter 23 installed at the lower part of the vehicle body 26 (see FIGS. 18 and 19).

図１９に示すように、インバータ２３の内部では、プリント基板（実装部材）２５上に複数のパワーモジュール２０が搭載され、さらにこれらのパワーモジュール２０を冷却する冷却装置２４が搭載されている。図１に示す本実施の形態のパワーモジュール２０では、半導体チップ１からの発熱量が多い。したがって、複数のパワーモジュール２０を冷却してインバータ２３の内部を冷却可能なように冷却装置２４が取り付けられている。つまり、図１のベース板４の底面が、図１９に示す冷却装置２４に接するように、パワーモジュール２０がインバータ２３に搭載される。   As shown in FIG. 19, inside the inverter 23, a plurality of power modules 20 are mounted on a printed circuit board (mounting member) 25, and a cooling device 24 that cools these power modules 20 is mounted. In the power module 20 of the present embodiment shown in FIG. 1, the amount of heat generated from the semiconductor chip 1 is large. Therefore, the cooling device 24 is attached so that the plurality of power modules 20 can be cooled to cool the inside of the inverter 23. That is, the power module 20 is mounted on the inverter 23 so that the bottom surface of the base plate 4 in FIG. 1 is in contact with the cooling device 24 shown in FIG.

これにより、図１８に示す鉄道車両２１において、図１に示すモジュールの接合構造が用いられた複数のパワーモジュール２０を搭載したインバータ２３が設けられていることにより、インバータ２３内が高温環境となった場合であっても、インバータ２３およびそれが設けられた鉄道車両２１の信頼性を高めることができる。すなわち、高温環境下での動作安定性と高電流負荷にも耐え得るパワーモジュール２０およびこれを用いたインバータシステムを実現することができる。   Accordingly, in the railway vehicle 21 shown in FIG. 18, the inverter 23 having the plurality of power modules 20 using the module joining structure shown in FIG. 1 is provided, so that the inside of the inverter 23 becomes a high temperature environment. Even in this case, the reliability of the inverter 23 and the railway vehicle 21 provided with the inverter 23 can be improved. That is, it is possible to realize a power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.

パワーモジュール２０は、複数であることは必須でなく、制御する装置の規模等に応じて単体での使用も可能である。
（実施の形態３）A plurality of power modules 20 are not essential, and can be used alone according to the scale of the device to be controlled.
(Embodiment 3)

次に、上記実施の形態１のパワーモジュール２０を搭載した自動車について説明する。図２０は、図１に示す半導体装置が搭載された自動車の一例を示す斜視図である。   Next, an automobile equipped with the power module 20 of the first embodiment will be described. FIG. 20 is a perspective view showing an example of an automobile on which the semiconductor device shown in FIG. 1 is mounted.

図２０に示す自動車２７は、例えば、図１に示すパワーモジュール２０が搭載されたものであり、車体２８と、タイヤ２９と、パワーモジュール２０（図１参照）を支持する実装部材である実装ユニット３０と、を備えている。   An automobile 27 shown in FIG. 20 is mounted with the power module 20 shown in FIG. 1, for example, and is a mounting unit that is a mounting member that supports the vehicle body 28, the tire 29, and the power module 20 (see FIG. 1). 30.

自動車２７では、パワーモジュール２０は、実装ユニット３０に含まれるインバータに搭載されているが、実装ユニット３０は、例えば、エンジン制御ユニット等であり、その場合、実装ユニット３０はエンジンの近傍に配置されている。この場合には、実装ユニット３０は、高温環境下での使用となり、これにより、パワーモジュール２０も高温状態となる。   In the automobile 27, the power module 20 is mounted on an inverter included in the mounting unit 30. The mounting unit 30 is, for example, an engine control unit, and in this case, the mounting unit 30 is disposed in the vicinity of the engine. ing. In this case, the mounting unit 30 is used in a high temperature environment, and the power module 20 is also in a high temperature state.

自動車２７において、図１に示す接合構造が用いられた複数のパワーモジュール２０を搭載したインバータが設けられていることにより、実装ユニット３０が高温環境となった場合であっても、自動車２７の信頼性を高めることができる。つまり自動車２７において、高温環境下での動作安定性と高電流負荷にも耐え得るパワーモジュール２０およびこれを用いたインバータシステムを実現することができる。
また、交流発電機、オルタネータ等にも適用することができる。Even if the mounting unit 30 is in a high temperature environment by providing an inverter in which the plurality of power modules 20 using the joining structure shown in FIG. Can increase the sex. That is, in the automobile 27, it is possible to realize a power module 20 that can withstand operation stability under a high temperature environment and a high current load, and an inverter system using the same.
It can also be applied to an AC generator, an alternator, and the like.

以上、本発明者らによってなされた発明を発明の実施の形態に基づき具体的に説明したが、本発明は前記発明の実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることは言うまでもない。   As mentioned above, the invention made by the present inventors has been specifically described based on the embodiment of the invention. However, the present invention is not limited to the embodiment of the invention, and various modifications can be made without departing from the scope of the invention. Needless to say, it can be changed.

なお、本発明は上記した実施の形態に限定されるものではなく、様々な変形例が含まれる。例えば、上記した実施の形態は本発明を分かりやすく説明するために詳細に説明したものであり、必ずしも説明した全ての構成を備えるものに限定されるものではない。   In addition, this invention is not limited to above-described embodiment, Various modifications are included. For example, the above-described embodiment has been described in detail for easy understanding of the present invention, and is not necessarily limited to one having all the configurations described.

また、ある実施の形態の構成の一部を他の実施の形態の構成に置き換えることが可能である。例えば、図１１〜図１４を用いて説明した実施の形態１の変形例のパワーモジュールを、実施の形態２または３のインバータに用いてもよい。   A part of the configuration of one embodiment can be replaced with the configuration of another embodiment. For example, the power module of the modification of the first embodiment described with reference to FIGS. 11 to 14 may be used for the inverter of the second or third embodiment.

上記の各実施例で説明したインバータは、実施の形態２の鉄道車両や実施の形態３の自動車を代表とする移動体のみならず、移動体の一種として、建設機械やエレベータにも適用可能である。   The inverter described in each of the above examples can be applied not only to a moving body represented by the railway vehicle of the second embodiment and the automobile of the third embodiment, but also to a construction machine or an elevator as a kind of moving body. is there.

さらに、本願発明の半導体装置は、太陽光発電装置、太陽光発電モジュールや風力発電機、風力発電モジュール等の発電装置の分野にも適用することが可能である。また、ホイストやアクチュエータ、圧縮機等を代表とする産業機械の分野にも適用可能である。
また、無停電電源装置、メインフレームや汎用計算機等の計算機の分野にも適用可能である。Furthermore, the semiconductor device of the present invention can also be applied to the field of power generation devices such as a solar power generation device, a solar power generation module, a wind power generator, and a wind power generation module. Moreover, it is applicable also to the field | area of the industrial machine represented by a hoist, an actuator, a compressor, etc.
The present invention is also applicable to the field of computers such as uninterruptible power supplies, mainframes and general purpose computers.

これらの例も高温環境下での動作安定性、高電流負荷に耐えることが可能となる。上記した半導体装置を用いる分野の装置を総称してパワーエレクトロニクス装置と呼ぶ。   These examples can also withstand operational stability under a high temperature environment and a high current load. Devices in the field using the semiconductor devices described above are collectively referred to as power electronics devices.

本願発明は、上記したパワーエレクトロニクスの分野の装置であれば適用可能であり、その信頼性向上に役立つ。   The present invention is applicable to any device in the field of power electronics described above, and is useful for improving its reliability.

本発明は、接合部を介して放熱を行う半導体装置およびその半導体装置を用いたパワーエレクトロニクス装置に適用して有効である。   INDUSTRIAL APPLICABILITY The present invention is effective when applied to a semiconductor device that dissipates heat through a junction and a power electronics device using the semiconductor device.

１ 半導体チップ
１ｃ 電極
２ はんだ
３ セラミック基板（配線基板）
３ｃａ、３ｃｂ、３ｃｃ 電極
４ ベース板（金属板）
５ はんだ（接合材）
５ａ はんだ（接合材）
５ｂ はんだ（接合材）
６ ワイヤ
７ 端子
８ ケース
９ 金属板
２０ パワーモジュール
DESCRIPTION OF SYMBOLS 1 Semiconductor chip 1c Electrode 2 Solder 3 Ceramic substrate (wiring board)
3ca, 3cb, 3cc electrode 4 Base plate (metal plate)
5 Solder (joining material)
5a Solder (joining material)
5b Solder (joining material)
6 Wire 7 Terminal 8 Case 9 Metal plate 20 Power module

Claims (12)

半導体チップと、
前記半導体チップを支持し、前記半導体チップに電気的に接続された配線基板と、
前記配線基板を支持する第１金属板と、
前記配線基板と前記第１金属板との間に配置された第２金属板と、
前記配線基板および前記第２金属板を接合する第１接合部と、
前記第１金属板および前記第２金属板を接合する第２接合部と
を有し、
前記第２金属板の中央部の厚みよりも、前記第２金属板の外周部の厚みが大きい、半導体装置。A semiconductor chip;
A wiring board that supports the semiconductor chip and is electrically connected to the semiconductor chip;
A first metal plate that supports the wiring board;
A second metal plate disposed between the wiring board and the first metal plate;
A first joint for joining the wiring board and the second metal plate;
A second joint for joining the first metal plate and the second metal plate;
A semiconductor device, wherein a thickness of an outer peripheral portion of the second metal plate is larger than a thickness of a central portion of the second metal plate. 請求項１記載の半導体装置において、
前記第２金属板の線膨張係数は、前記配線基板の線膨張係数と前記第１金属板の線膨張係数の間の値である、半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the linear expansion coefficient of the second metal plate is a value between the linear expansion coefficient of the wiring board and the linear expansion coefficient of the first metal plate. 請求項１記載の半導体装置において、
前記第１金属板上に、順に前記第２接合部、前記第２金属板、前記第１接合部、前記配線基板および前記半導体チップが配置され、
平面視において、前記第２金属板の前記外周部は、前記配線基板の外側に位置する、半導体装置。The semiconductor device according to claim 1,
On the first metal plate, the second joint portion, the second metal plate, the first joint portion, the wiring board, and the semiconductor chip are arranged in order,
The semiconductor device, wherein the outer peripheral portion of the second metal plate is located outside the wiring substrate in a plan view. 請求項３記載の半導体装置において、
前記第１金属板の上面に対して垂直な方向において、前記第２金属板の前記外周部は、前記中央部の上面よりも前記配線基板側に突出し、
前記第２金属板の前記中央部の前記上面と前記外周部の上面との間の前記方向における距離は、前記第２金属板の前記中央部の前記上面と前記配線基板との間の前記方向における距離よりも大きい、半導体装置。The semiconductor device according to claim 3.
In a direction perpendicular to the upper surface of the first metal plate, the outer peripheral portion of the second metal plate protrudes closer to the wiring board than the upper surface of the central portion,
The distance in the direction between the upper surface of the central portion of the second metal plate and the upper surface of the outer peripheral portion is the direction between the upper surface of the central portion of the second metal plate and the wiring board. A semiconductor device larger than the distance in 請求項１記載の半導体装置において、
前記第１金属板の上面に対して垂直な方向において、前記第２金属板の前記外周部は、前記中央部の上面よりも前記配線基板側に突出する、半導体装置。The semiconductor device according to claim 1,
The semiconductor device, wherein the outer peripheral portion of the second metal plate protrudes closer to the wiring board than the upper surface of the central portion in a direction perpendicular to the upper surface of the first metal plate. 請求項５記載の半導体装置において、
前記方向において、前記第２金属板の前記外周部は、前記中央部の下面よりも前記第１金属板側に突出し、
前記方向において、前記第２金属板の前記中央部の前記下面に対し、前記外周部が前記第１金属板側に突出する長さは、前記第２接合部の厚さよりも小さい、半導体装置。The semiconductor device according to claim 5.
In the said direction, the said outer peripheral part of the said 2nd metal plate protrudes in the said 1st metal plate side rather than the lower surface of the said center part,
The length of the outer peripheral portion protruding toward the first metal plate with respect to the lower surface of the central portion of the second metal plate in the direction is smaller than the thickness of the second bonding portion. 請求項１記載の半導体装置において、
前記第１金属板上に、順に前記第２接合部、前記第２金属板、前記第１接合部、前記配線基板および前記半導体チップが配置され、
前記半導体チップおよび前記配線基板は、それらの間に介在する第３接合部により接合され、
平面視において、前記第１接合部および前記第２接合部のそれぞれの面積は、前記第３接合部の面積よりも大きい、半導体装置。The semiconductor device according to claim 1,
On the first metal plate, the second joint portion, the second metal plate, the first joint portion, the wiring board, and the semiconductor chip are arranged in order,
The semiconductor chip and the wiring board are bonded by a third bonding portion interposed therebetween,
In plan view, each area of the first junction and the second junction is greater than the area of the third junction. 請求項１記載の半導体装置において、
前記第１接合部の厚さよりも、前記第２接合部の厚さの方が大きい、半導体装置。The semiconductor device according to claim 1,
A semiconductor device, wherein the thickness of the second junction is greater than the thickness of the first junction. 請求項１記載の半導体装置において、
前記第１接合部および前記第２接合部は、Ｓｎ系はんだ合金を含む、半導体装置。The semiconductor device according to claim 1,
The first joint portion and the second joint portion are semiconductor devices including an Sn-based solder alloy. 半導体チップと、
前記半導体チップを支持し、前記半導体チップに電気的に接続された配線基板と、
前記配線基板を支持する第１金属板と、
前記配線基板と前記第１金属板との間に配置された第２金属板と、
前記配線基板および前記第２金属板を接合する第１接合部と、
前記第１金属板および前記第２金属板を接合する第２接合部と
を有し、
前記第２金属板の中央部の厚みよりも、前記第２金属板の外周部の厚みが大きい半導体装置を有するインバータが搭載された、パワーエレクトロニクス装置。A semiconductor chip;
A wiring board that supports the semiconductor chip and is electrically connected to the semiconductor chip;
A first metal plate that supports the wiring board;
A second metal plate disposed between the wiring board and the first metal plate;
A first joint for joining the wiring board and the second metal plate;
A second joint for joining the first metal plate and the second metal plate;
A power electronics device on which an inverter having a semiconductor device having a thickness of an outer peripheral portion of the second metal plate larger than a thickness of a central portion of the second metal plate is mounted. 請求項１０記載のパワーエレクトロニクス装置であって、
前記パワーエレクトロニクス装置は、鉄道車両である、パワーエレクトロニクス装置。The power electronics device according to claim 10,
The power electronics device is a railroad vehicle. 請求項１０記載のパワーエレクトロニクス装置であって、
前記パワーエレクトロニクス装置は、自動車である、パワーエレクトロニクス装置。The power electronics device according to claim 10,
The power electronics device is a power electronics device which is an automobile.
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