JP2018073923A - Power semiconductor device, method of manufacturing the same, and power conversion device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power semiconductor device capable of increasing a current and securing bonding reliability without increasing a size of a lead frame, and to provide a method of manufacturing the same, and a power conversion device.SOLUTION: A power semiconductor device 101 comprises: a lead frame 5 that mounts power semiconductor elements, such as a switching element 3 and a rectification element 4 and the like, and that has a lead pattern 20 connected by electrodes of the power semiconductor elements and an aluminum wire 9 and a gold wire 10, and a lead 19 having a through-hole 19 into which an insertion terminal 2 is inserted; and an encapsulation body 6 that encapsulates among the power semiconductor element, the aluminum wire 9 and gold wire 10, and the lead pattern 20 with an encapsulation resin so as to expose the lead 18.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a power semiconductor device, a method for manufacturing a power semiconductor device, and a power conversion device, and more particularly to a power semiconductor device in which a power semiconductor element is mounted on a lead frame, a method for manufacturing a power semiconductor device, and a power conversion device. .

  Among semiconductor devices, power semiconductor devices are used for power control of a wide range of devices from industrial equipment to consumer electronics / information terminals, and high reliability is particularly required for industrial equipment, transportation equipment, and the like. In recent years, power modules for industrial and transportation equipment have been increased in current and function, and the package size has expanded accordingly. A DIP (Dual In-line Package) type module that can be expected to have high reliability is a module in which a resin is sealed with a transfer mold and terminals are arranged on the side surface of the package. In the transfer mold, it is necessary to use a lead frame. However, when the area of the lead frame is increased as the current increases, it is limited to the range of equipment constraints. In particular, in the DIP type module, the terminals protruding from both sides of the package in the manufacturing process occupy a part of the lead frame before processing, so the ratio of the package to the lead frame is reduced, and the current is increased. High functionality is difficult. In addition, in industrial and transportation modules, as a method of forming terminals, there is a demand for linear terminals for soldering and press-fit terminals that are fixed by caulking to the board, but in DIP type modules, redesign of the lead frame, Productivity deteriorated due to the burden of re-prototyping the mold.

  On the other hand, in patent document 1, the 1st lead frame which consists of a terminal and a package, and the 2nd lead frame which consists only of a part of terminal are prepared separately, and each is joined before a sealing process. It is integrated. Since the first and second lead frames are separated, there is an advantage that the required terminal shape can be easily changed. Moreover, in patent document 2, after completing the transfer mold of a sealing process in the state without a terminal, a press fit terminal is press-fitted in the female connector formed at the sealing process. Since no terminals are required in the lead frame, the module can have a large current up to the size limit of the lead frame.

JP 2014-154696 A (paragraph 0044, FIG. 13) JP 2013-152966 A (paragraph 0013, FIG. 1)

  However, in Patent Document 1, for example, the die bonding process for mounting the chip can be carried by the first lead frame, but the subsequent processes can be assembled only after both frames are joined. For this reason, there is a problem that the problem of increasing the lead frame size cannot be completely solved. Further, when two lead frames are overlapped and joined, the thickness of the joining portion where the two pieces overlap is increased. In the sealing process, the lead frame is clamped with a metal mold, but it cannot be clamped due to the thickness of the joint portion, and the sealing resin leaks, resulting in a deterioration in yield. Even if the plate thickness is reduced only in the overlapping portion and the total thickness of the lead frame is adjusted, there is a problem that the load on the clamp becomes unstable due to the non-uniform lead frame thickness caused by processing tolerances.

  In Patent Document 2, there is a problem in that a resin burr is formed around the through hole of the lead frame in the female connector during the sealing process, and the resin burr may bite and there is a risk of deterioration of characteristics due to an increase in contact resistance. Further, when the insertion terminal is inserted into the female connector of the package, there is a problem that the thickness of the package is increased because the connector needs to be deepened by the extent that the tip of the press-fit terminal protrudes from the lead frame. Further, in a package with an increased area, it is difficult to control the warpage of the package, and there is a problem in that the yield does not improve because the press-fit terminals cannot be inserted vertically due to variations in warpage. In addition, when the area is increased, when mounted on an external substrate, it is easily affected by warpage of the external substrate. There is a problem that stress is applied between the press-fit terminal and the connector due to warpage of the external substrate caused by thermal distortion between the external substrate and the mounted component, resulting in a decrease in bonding reliability.

  The present invention has been made to solve the above-described problems, and a power semiconductor device capable of increasing current and ensuring junction reliability without increasing the lead frame size, and An object is to provide a method for manufacturing a power semiconductor device.

  A power semiconductor device according to the present invention includes a power semiconductor element, a lead pattern having a lead pattern connected to an electrode of the power semiconductor element with a wire, and a lead portion provided with a through hole; and A sealing body in which a space between the power semiconductor element, the wire, and the lead pattern is sealed with a sealing resin so that a lead portion is exposed, and an insertion terminal that is inserted into the through hole are provided. Features.

  The method for manufacturing a power semiconductor device according to the present invention includes a step of placing a power semiconductor element on the lead pattern of a lead frame having a lead portion provided with a through hole and a lead pattern, and the power semiconductor. A step of connecting the electrode of the element and the lead pattern with a wire, and a step of sealing between the power semiconductor element, the wire, and the lead pattern with a sealing resin so that the lead portion is exposed. And inserting an insertion terminal into the through hole of the exposed lead portion.

  According to the present invention, by inserting an insertion terminal having a press-fit portion into a through-hole provided in a lead portion of a lead frame exposed from the sealing body, the current can be increased without increasing the lead frame size. Therefore, it is possible to ensure the bonding reliability.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view, a top view, and a cross-sectional view for explaining a configuration of a power semiconductor device according to a first embodiment of the present invention. It is a top view for demonstrating the internal structure of the power semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows the state before and after inserting an insertion terminal in the through-hole in the semiconductor device for electric power concerning Embodiment 1 of this invention. It is a flowchart figure which shows the manufacturing process of the power semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows one Example of the power semiconductor device concerning Embodiment 1 of this invention. It is sectional drawing which shows the other example of the insertion terminal of the semiconductor device for electric power concerning Embodiment 1 of this invention. It is sectional drawing which shows the other example of the insertion terminal of the semiconductor device for electric power concerning Embodiment 1 of this invention. It is sectional drawing for demonstrating the structure of the semiconductor device for electric power concerning Embodiment 2 of this invention. It is sectional drawing for demonstrating the structure of the semiconductor device for electric power concerning Embodiment 3 of this invention. It is a top view for demonstrating the structure of the lead part of the semiconductor device for electric power concerning Embodiment 4 of this invention. It is sectional drawing for demonstrating the structure of the power semiconductor device concerning Embodiment 5 of this invention. It is sectional drawing for demonstrating the structure of the power semiconductor device concerning Embodiment 6 of this invention. It is sectional drawing for demonstrating the other structure of the power semiconductor device concerning Embodiment 6 of this invention. It is sectional drawing for demonstrating the structure of the insertion terminal of the semiconductor device for electric power concerning Embodiment 7 of this invention. It is a block diagram which shows the structure of the power conversion system to which the power converter device concerning Embodiment 8 of this invention is applied.

Embodiment 1 FIG.
FIG. 1 shows a configuration of main members used for manufacturing a power semiconductor device and a power semiconductor device according to a first embodiment of the present invention. FIG. 1 (a) is a perspective view of the power semiconductor device. 1B is a top view of the power semiconductor device, and FIG. 1C is a cross-sectional view taken along line AA in FIG. 1B. FIG. 2 is a top view showing a structure inside the sealing body 6 of the power semiconductor device of FIG.

  As shown in FIG. 1, a power semiconductor device 101 includes a sealing body 6 formed by sealing a semiconductor element or the like mounted on a lead frame 5 also serving as an electric circuit with a sealing resin, and a sealing body 6. From the lead 18 which is a plurality of lead portions exposed from the side surface of the lead, and the insertion terminal 2 for connection inserted in the through hole 19 provided in the lead 18 for electrical connection with an external substrate or an external circuit It is configured.

  A lead 18 that is a part of the lead frame 5 exposed from the sealing body 6 is provided with a through hole 19, and the lead 18 and the insertion terminal 2 are electrically connected through the through hole 19. The insertion terminal 2 is made of an alloy containing copper, for example. On the surface of the lead frame 5 used as a circuit board, a switching element 3 and a rectifying element 4 which are power semiconductor elements are joined with solder 7 on the back electrode side. A back electrode side of an IC (Integrated Circuit) 17 of the control circuit is bonded by a conductive bonding material 16. The conductive bonding material 16 may be a conductive bonding material such as Ag paste or solder. The switching element 3 is, for example, an IGBT (Insulated Gate Bipolar Transistor), and the rectifying element 4 is, for example, an FwDi (Free Wheeling Diode).

  FIG. 2 shows a circuit diagram of a portion of the lead pattern 20 in the lead frame 5 on which the power semiconductor element is mounted and a portion of the lead pattern 20 that is electrically connected to the power semiconductor element. The surface of the switching element 3 and the rectifying element 4 and the lead pattern 20 are electrically connected by an aluminum wire 9, and the gate electrode of the switching element 3 and the lead pattern 20 are electrically connected by a gold wire 10. The lead pattern 20 on which the power semiconductor element is mounted is bent toward the aluminum plate 13 as compared with the lead pattern 20 on which the IC 17 is mounted.

On the back surface of the portion of the lead pattern 20 on which the power semiconductor element is mounted, the aluminum plate 13 is electrically insulated and fixed by an adhesive resin 14 having high heat dissipation. The adhesive resin 14 includes, for example, an inorganic material including SiO ₂ , BN, AlN, and Al ₂ O ₃ having high thermal conductivity, and thermosetting and thermoplastic such as an epoxy resin, a polyimide resin, and an acrylic resin that have an adhesion and insulation function. Consists of resin. The same effect can be obtained with different materials as long as they have similar functions. One surface of the aluminum plate 13 is exposed from the sealing body 6. The aluminum plate 13 may be a member having a high heat dissipation property, and may be another metal such as copper, or a ceramic such as SiO ₂ , AlN, or Si ₃ N ₄ .

  The lead 18 exposed from the sealing body 6 is provided with a circular through hole 19 and is electrically connected by inserting the insertion terminal 2 into the through hole 19. FIG. 3 is a cross-sectional view showing a state before and after inserting the insertion terminal 2 into the through hole 19. 3A is a view before insertion, FIG. 3B is after insertion, and FIG. 3C is a top view of the lead 18. As shown in FIG. 3A, an elliptical press-fit portion 2a having a hollow portion 2h cut out in the center is provided at the lower portion of the insertion terminal 2 for insertion into the lead 18. The central portion of the insertion terminal 2 has a fixed portion 2b having a step, and the hollow portion 2h is formed across the fixed portion 2b. The upper portion of the insertion terminal 2 has a straight terminal portion 2c which is a linear terminal portion.

  When the insertion terminal 2 is connected to the through hole 19, the press fit portion 2 a is press-fitted into the through hole 19. At this time, the press-fit portion 2a is deformed and is mechanically fixed to the through hole by a repulsive force at the time of deformation. At the time of insertion, the fixing portion 2b is pushed in until it contacts the lead 18. The fixing part 2b serves to stop the insertion operation.

  Next, a method for manufacturing the power semiconductor device 101 will be described. FIG. 4 is a flowchart showing manufacturing steps of the power semiconductor device according to the first embodiment of the present invention. As shown in FIG. 4, first, as a die bonding step (step S <b> 401), the IC 17 is fixed on the lead frame 5 with the conductive bonding material 16, and the switching element 3 and the rectifying element 4 are bonded with the Pb-free solder 7.

  Subsequently, as a wire bonding step (step S402), the switching element 3, the rectifying element 4, and the lead pattern 20 are connected by the aluminum wire 9 by wire bonding. Next, the gate of the switching element 3, the IC 17, and the lead pattern 20 are connected by the gold wire 10 by wire bonding. An aluminum plate 13 is bonded to the back surface of the lead pattern 20 on which the switching element 3 and the rectifying element 4 are mounted with an adhesive resin 14.

  Finally, in the sealing step (step S403), the lead frame 5 is placed on a molding die for sealing and sealed with a sealing resin using a transfer mold. After sealing, an excess portion of the lead frame is removed, and the insertion terminal 2 is press-fitted and fixed to the lead 18 exposed from the sealing body 6, whereby the power semiconductor device 101 is formed. When the insertion terminal is press-fitted, the lead around the through hole is supported and the fixing portion of the insertion terminal is pushed down for insertion.

  Thus, in the first embodiment, by providing the insertion terminal 2 in the power semiconductor device 101, the insertion terminal 2 is attached after the sealing process in the manufacturing process, and the space of the insertion terminal is provided in the lead frame before processing. Since this is not necessary, the productivity can be improved by increasing the number of packages in the lead frame. Further, by increasing the package area in the lead frame, the module can be increased in current. In addition to the power semiconductor elements, for example, a space for incorporating a control circuit for a BSD (Bootstrap Diode) or a BSC (Bootstrap capacitor), which has been conventionally externally attached to an external substrate, is secured to improve functionality. You can also.

  As described above, according to the power semiconductor device 101 according to the first embodiment of the present invention, the power semiconductor elements such as the switching element 3 and the rectifying element 4 are mounted, the electrode of the power semiconductor element, and aluminum The lead semiconductor 20 provided with a lead pattern 20 having a lead pattern 20 connected by a wire 9 and a gold wire 10 and a lead 18 having a through hole 19 into which the insertion terminal 2 is inserted, and the lead 18 is exposed. Since the sealing body 6 that seals the space between the aluminum wire 9 and the gold wire 10 and the lead pattern 20 with the sealing resin is provided, the current can be increased without increasing the lead frame size, Bonding reliability can be ensured.

  Further, since the lead frames are not divided as in Patent Document 1, there is no joint between the lead frames, and resin leakage does not occur during mold clamping in the sealing process. Furthermore, since the insertion terminal 2 is retrofitted, the material of the lead frame and the insertion terminal can be changed. For example, the lead frame is made of an inexpensive alloy with high copper purity to ensure conductivity. On the other hand, the insertion terminal is low in purity of copper, and by adding iron or the like to increase the rigidity, the repulsion force when the insertion terminal is inserted into the through hole is increased, thereby improving the reliability.

  Further, by separating the insertion terminal and the lead frame, productivity can be improved by freely changing the length of the insertion terminal regardless of the size of the lead frame or the design of the lead frame. The fixing portion 2b of the insertion terminal has an effect of stopping the insertion operation and making the terminal length constant.

  Further, in the press-fit terminal as in Patent Document 2, the press-fit portion and the fixed portion are separated from each other, but in the insertion terminal 2 of the first embodiment, the fixed portion 2b and the press-fit portion 2a are integrated to form a hollow portion. 2h is formed straddling to the inside of the fixed part 2b. The lead 18 of the lead frame 5 into which the insertion terminal 2 is inserted is as thin as about 0.3 to 1.5 mm, and in the conventional insertion terminal, the press-fit portion penetrates the lead frame. On the other hand, in the power semiconductor device 101 according to the first embodiment, since the press-fit portion 2a is directly below the fixing portion 2b of the insertion terminal 2, the through hole and the press-fit portion can be reliably fixed. Since the hollow portion 2h in the fixed portion 2b is also deformed at the time of insertion, the repulsive force of the press fit portion 2a can be obtained, so that stable bonding is possible. Further, since the hollow portion 2h is formed across the fixing portion 2b, the press fit portion is fixed to the through hole with a high repulsive force.

  Furthermore, in Patent Document 2, since the female connector is formed by transfer molding, there is a possibility that resin enters the female connector and a resin burr is formed. If a resin burr enters during the insertion of a press-fit terminal, the contact resistance increases and a characteristic deterioration is assumed. In order to prevent resin burrs from being processed by laser processing or blast processing, in addition to additional processing steps, damage to the chip due to heating and deformation of the hole shape of the female connector occur, and press-fit terminals are inserted. Stability may be reduced. In the power semiconductor device 101 according to the first embodiment, since there is no damage or deformation due to such an additional process, the joining property of the insertion terminal is stabilized. Further, when the insertion terminal is inserted into the female connector of the package, it is necessary to deepen the connector by the amount that the distal end of the insertion terminal protrudes from the lead frame, so that the package thickness increases. In contrast, in the first embodiment, the press-fit portion 2a protruding from the through hole 19 remains hollow and does not require a space. Therefore, the package thickness can be reduced, and the productivity is reduced by reducing the sealing resin. Can be improved.

  In addition, when the warpage of the package is large, if it is inserted into the female connector of the package as in the prior art, there is a possibility of buckling without entering vertically. On the other hand, in the power semiconductor device 101 of the first embodiment, the lead 18 itself bends along a jig for supporting the lead when inserted, so that the insertion terminal 2 is inserted vertically. As a result, it is possible to tolerate warpage, so productivity is improved. Even when the external substrate 21 is warped due to heat shrinkage of the mounted component, one end of the lead 18 is fixed as shown in FIG. 5, but the other end is not fixed and deforms up and down. Therefore, it is possible to follow the warp of the external substrate by bending. For this reason, the stress applied to the press-fit portion is reduced and the joining reliability is improved. In particular, when the package is enlarged (for example, the package size is 34 × 85 mm or more), it is easily affected by the warp of the substrate, so that the effect of the first embodiment becomes remarkable.

  Further, in Patent Document 2, when the press-fit terminal comes into contact with the sealing resin, the sealing resin contracts and expands during a temperature cycle, and stress is applied to the press-fit portion, which may reduce the bonding strength. In particular, when the package size is increased, the amount of shrinkage of the sealing resin may increase due to transfer mold in the sealing process, so that the sealing resin deforms with respect to temperature rather than the lead frame. It's easy to do. In the power semiconductor device 101 according to the first embodiment, since the press-fit portion 2a is joined only to the through-hole 19, it has high reliability with respect to the temperature cycle without receiving stress due to shrinkage of the sealing resin. Can be obtained. In particular, if both the insertion terminal and the lead frame are made of the same main component, such as a copper alloy, the linear expansion coefficient is close, and thermal distortion is unlikely to occur.

  In general, since a power semiconductor device generates a voltage of several hundred volts to several tens of kV, it is necessary to insulate between through holes on an external substrate. In the power semiconductor device 101 according to the first embodiment, the insertion terminal 2 is inserted in the width direction (W direction) from the direction perpendicular to the wiring direction (V direction) of the leads 18 as shown in FIG. 2 (see FIG. 3A), the press-fit portion 2a of the insertion terminal 2 is inserted into the through hole 19 of the lead 18 (see FIG. 3B). The two straight terminal portions 2c can be inserted into the external substrate. That is, the width direction (W direction) of the insertion terminal can be arranged in parallel with the wiring direction (V direction) of the lead 18. In the insulation between the leads of the power semiconductor device, the portion except the lead width is the insulation distance between the leads, but the thickness between the insertion terminal and the insertion terminal is excluded as in the first embodiment. Therefore, the insulation distance can be made longer between the insertion terminals. Since the insulation distance between the insertion terminals can be increased, the insulation distance between the through holes on the external substrate can be extended. This increases the degree of design freedom for the pattern on the external substrate and improves the reliability related to insulation such as tracking and migration.

  Further, the cross section of the insertion terminal 2 is a rectangle having a long width in the lead wiring direction, and even if the width is increased, the insulation distance between the insertion terminals is not shortened. Therefore, the width of the insertion terminal can be increased more than the width of the lead. . As a result, the heat capacity can be increased by making the cross-sectional area of the insertion terminal larger than the cross-sectional area of the lead, thereby suppressing the heat generation of the terminal itself and preventing the temperature from rising even with heat transmitted from the power semiconductor element. can do. For this reason, the temperature of the external substrate can be lowered. By increasing the width of the insertion terminal, not only the heat capacity can be increased, but also the surface area can be increased to increase the heat dissipation, so that the temperature is hardly increased. For example, the width of the lead is preferably 2 to 4 mm in consideration of the size of the through hole and the insulation distance between the lead terminals, but the width of the insertion terminal can be formed more than twice.

  In the insertion terminal according to the first embodiment, the press-fit portion and the fixing portion do not have to be integrated. As shown in FIG. 6, the insertion terminal 22 has a shape in which a notch 22d is formed in a part of the fixing portion 22b. In this case, the same effect can be obtained. The notch 22d is shaped upward from the lower end of the fixed portion 22b. By inserting the notch 22d, the base of the press-fit portion 22a is constricted, and the sectional moment of inertia becomes small, so that the movement becomes easy. For this reason, as shown in FIG. 6A, even if the through hole 19 is inclined due to warping of the package or the like, the base of the press-fit portion 22a is deformed and follows during insertion (see FIG. 6B). Easy to insert. Further, the straight terminal portions 2c and 22c of the insertion terminals 2 and 22 may not be linear. As shown in FIG. 7, for example, external substrate insertion press-fit portions 23e and 24e that can be press-fit connected to the external substrate like the insertion terminals 23 and 24 may be used.

Embodiment 2. FIG.
In the first embodiment, the case where the lead 18 having the same thickness as the lead pattern 20 is used has been described. In the second embodiment, a case where multiple leads are used will be described.

  FIG. 8 is a sectional view showing a configuration of the power semiconductor device 102 according to the second embodiment of the present invention. As shown in FIG. 8, the power semiconductor device 102 includes a multiple lead 40 in which two leads are folded and stacked. The multiple lead 40 is formed with a through hole 41 penetrating the multiple lead 40. The other configuration of the power semiconductor device 102 is the same as that of the power semiconductor device 101 of the first embodiment, and a description thereof is omitted. The manufacturing method is the same as that of the first embodiment except that the lead frame 50 in which the multiple leads 40 are formed in advance is provided, and the description thereof is omitted.

  As described above, according to the power semiconductor device 102 according to the second exemplary embodiment of the present invention, the multiple leads 40 are provided by bending the leads and overlapping the two sheets. By increasing the contact area between the portion 2a and the multiple leads 40 and increasing the bonding strength, the bonding strength increases with respect to vibration when mounted on an external substrate. Furthermore, since the contact area between the multiple lead and the insertion terminal can be increased, the electrical resistance at the joint interface between the multiple lead and the insertion terminal is lowered, and the temperature of the external substrate can be lowered while suppressing the heat generation of the terminal.

Embodiment 3 FIG.
In the second embodiment, the case where the multiple leads 40 are used has been described. In the third embodiment, the case where different thickness leads are used will be described.

  FIG. 9 is a sectional view showing a configuration of the power semiconductor device 103 according to the third embodiment of the present invention. As shown in FIG. 9, the power semiconductor device 103 includes different thickness leads 42 in which the thickness of the leads 18 is different from that in the first embodiment. The different thickness lead 42 is formed with a through hole 43 that penetrates the different thickness lead 42. The different thickness lead 42 is thicker than the lead pattern 20 in the sealing body 6 and has a thickness of 0.5 to 3.0 mm. The root portion 42 a of the different thickness lead 42 is covered with the sealing body 6. The other configuration of the power semiconductor device 103 is the same as that of the power semiconductor device 101 of the first embodiment, and a description thereof is omitted. The manufacturing method is the same as that of the first embodiment except that the lead frame 51 in which the different thickness leads 42 are formed in advance, and the description thereof is omitted.

  As described above, according to the power semiconductor device 103 according to the third embodiment of the present invention, the different thickness leads 42 that are thicker than the lead pattern 20 are provided, and the root portion 42 a of the different thickness lead 42 is formed by the sealing body 6. Since the different thickness lead 42 is covered, the different thickness portion 42 is connected to the inside of the sealing body 6 in addition to the increase in the plate thickness, so that the rigidity of the different thickness lead 42 is increased. For this reason, the effect of increasing the contact area as in the second embodiment and the deformation of the lead accompanying the deformation of the through hole when the insertion terminal is inserted can be suppressed.

  Although it is possible to increase the plate thickness of the entire lead frame, the provision of the different thickness lead 42 has the following advantages. The aluminum plate 13 is bonded to the lower surface of the lead pattern 20 on which the power semiconductor element is mounted with an adhesive resin. When the plate thickness of the lead pattern 20 mounted on the power semiconductor element is increased, the bondability between the adhesive resin and the lead pattern 20 is reduced due to a thermal strain mismatch between the lead pattern 20 and the aluminum plate 13 during a temperature cycle in actual operation. For this reason, in order to increase the bonding reliability, it is desirable to increase the plate thickness of the different thickness lead 42 and only the lead root portion 42 a connected from the different thickness lead 42 to the sealing body 6.

Embodiment 4 FIG.
In the first embodiment, the case where the round hole-shaped through hole 19 is formed in the lead 18 has been described. In the fourth embodiment, the case where a slit-shaped through hole is formed will be described.

  FIG. 10 is a plan view showing the configuration of the lead 18 of the power semiconductor device 104 according to the fourth embodiment of the present invention. As shown in FIG. 10A, the power semiconductor device 104 has a slit-like through hole 44 in which both ends of a circle are cut off. The through-hole 44 is long along the lead wiring direction, and the short side is arcuate. Further, the width of the through hole 44 is narrower than that of the first embodiment in the width direction of the lead. In the first embodiment, a lead width larger than the diameter of the through hole is required, but in the fourth embodiment, a lead can be formed with a lead width smaller than the diameter. The other configuration of the power semiconductor device 104 is the same as that of the power semiconductor device 101 of the first embodiment, and a description thereof is omitted. The manufacturing method is the same as that of the first embodiment except that the lead frame 5 in which the leads 18 having the slit-like through holes 44 are formed in advance, and the description thereof is omitted.

  As described above, according to the power semiconductor device 104 according to the fourth exemplary embodiment of the present invention, since the slit 18 is provided in the lead 18, by reducing the lead width, The insulation distance can be increased, and high reliability for insulation can be obtained. Further, when inserting the insertion terminal 2, the length of the slit-like through hole 44 can serve as a guide and can be inserted perpendicular to the lead. Furthermore, the short length of the slit-shaped through hole 44 is suppressed to be equal to the plate thickness of the insertion terminal or less than the plate thickness +0.2 mm, so that the long side becomes a guide when the insertion terminal is inserted and is perpendicular to the lead. Can be inserted into. Note that the side on the short side of the through hole is not limited to an arc shape. As shown in FIG. 10B, the same effect can be obtained even in a linear shape.

Embodiment 5. FIG.
In the first embodiment, the case where one lead hole 19 is formed in the lead 18 has been described. In the fifth embodiment, a case where a plurality of through holes are formed in a solid manner will be described.

  FIG. 11 is a cross-sectional view showing a configuration of power semiconductor device 105 according to the fifth embodiment of the present invention. As shown in FIG. 11, the power semiconductor device 105 is provided with two through holes 19 in each lead 18 side by side in the lead wiring direction. The insertion terminals 2 are inserted into the respective through holes 19. Other configurations of the power semiconductor device 105 are the same as those of the power semiconductor device 101 of the first embodiment, and a description thereof is omitted. The manufacturing method is the same as that of the first embodiment except that the lead frame 5 in which each lead 18 is formed with two through holes 19 is prepared in advance, and the description thereof is omitted.

  In the power semiconductor device, the switching element 3 and the rectifying element 4 generate heat, and the temperature of the module may be 150 ° C. or higher. The heat of the element is also conducted to the lead pattern 20 and is transmitted to the external substrate via the insertion terminal 2. At this time, if a heat-sensitive component is installed on the external substrate, the component terminal may be heated by the heat of the insertion terminal 2 to reduce the reliability of the component. On the other hand, in the fifth embodiment, two through holes 19 are provided, and the heat transmitted to the insertion terminal 2 is dispersed to suppress the heat conducted to the external board, thereby improving the reliability of the parts of the external board. be able to.

  The number of through-holes 19 is not limited to two, and the same effect can be obtained with three or more through-holes 19, and the insertion terminal 2 may be inserted only into necessary leads according to the heat generated by the leads.

  As described above, according to the power semiconductor device 105 according to the fifth embodiment of the present invention, each lead 18 is provided with the plurality of through holes 19, and the heat conducted from the inserted insertion terminal 2 to the external substrate. Therefore, the heat conducted to the external substrate can be suppressed and the reliability of the components of the external substrate can be improved.

  Since the lead is disposed outside the package, the path through which the heat of the power semiconductor element is conducted is long and difficult to be transmitted. This effect is also enjoyed in the first to fourth embodiments, but in the fifth embodiment, the effect that heat is hardly transmitted can be amplified by further increasing the number of insertion terminals.

Embodiment 6 FIG.
In the fifth embodiment, the case where the insertion terminal 2 is inserted into each of the two through holes 19 provided in the lead 18 has been described. In the sixth embodiment, a case where one of the through holes is jumper-wired will be described. .

  FIG. 12 shows the configuration of the power semiconductor device according to the sixth embodiment of the present invention. FIG. 12 (a) is a top view of the power semiconductor device, and FIG. 1 (b) is FIG. It is an arrow directional cross-sectional view in the BB line. As shown in FIG. 12, the power semiconductor device 106 is provided with two through holes 19 in each lead 18 side by side in the lead wiring direction. In the power semiconductor device 106, the insertion terminal 2 is inserted into each of the two through holes 19 on the switching element 3 and rectifying element 4 sides, but the outer through hole 19 is inserted into the through hole 19 on the IC 17 side. The insertion terminals 2 are respectively inserted only into. A jumper wiring 25 is inserted into the inner through hole 19 close to the sealing body 6. Unlike the insertion terminal 2, the jumper wiring 25 does not have a straight terminal portion connected to the external substrate, but has two press-fit portions in the same direction and can be connected to the two leads 18. The other configuration of the power semiconductor device 106 is the same as that of the power semiconductor device 101 of the first embodiment, and a description thereof is omitted. The manufacturing method is the same as that of the first embodiment except that the lead frame 5 in which each lead 18 is formed with two through holes 19 is prepared in advance, and the description thereof is omitted.

  As shown in FIG. 12A, the jumper wiring 25 connects the first lead 18a and the second lead 18b. For example, when the second lead 18b is a dummy lead that is not connected to the lead pattern, the first lead 18a and the second lead 18b can be electrically connected to each other by connecting them with the jumper wiring 25. When the insertion terminal 2 is inserted into the second lead 18b, the same electrical signal as that of the first lead 18a can be transmitted to the external substrate. For this reason, when it is necessary to change the wiring layout on the external substrate, the lead arrangement can be changed by connecting the jumper wiring 25. When the lead frame is redesigned, the processing cost of the lead frame and a transfer mold die are required. However, by providing the jumper wiring 25, the same member can be used, and the productivity is improved. In particular, by forming jumpers lower than the upper and lower surfaces of the sealing body 6, it is easy to ensure insulation from the external substrate when mounted on the external substrate.

  The same effect can be obtained by connecting the jumper wiring 25 to the lead on the lead frame on which the switching element 3 and the rectifying element 4 are mounted. Further, as shown in FIG. 13, the jumper wiring 25 may be inserted from a direction opposite to the insertion terminal 2 inserted into the through hole 19 outside the lead 18. By disposing on the opposite surface, an insulation distance from the wiring of the external substrate can be taken. Furthermore, a complicated circuit can be configured by forming a plurality of jumpers on both sides of the lead.

  As described above, according to the power semiconductor device 106 according to the sixth embodiment of the present invention, each lead 18 is provided with the plurality of through holes 19 and the jumper wiring 25 is provided in one of the through holes. Therefore, when it is necessary to change the wiring layout on the external substrate, it is possible to change the lead arrangement by connecting the jumper wiring, and the same member can be used, thereby improving the productivity. In addition, by forming jumpers lower than the upper and lower surfaces of the sealing body 6, it is easy to ensure insulation from the external substrate when mounted on the external substrate. Furthermore, by inserting the jumper wiring 25 from the direction opposite to the insertion terminal 2 inserted into the through hole 19 outside the lead 18, an insulation distance from the wiring on the external substrate can be obtained.

Embodiment 7 FIG.
In the first embodiment, the case where the elliptical press-fit portion 2a is formed in the insertion terminal 2 has been described. In the sixth embodiment, the case where a burred portion is provided in the press-fit portion will be described.

  FIG. 14 is a cross-sectional view showing the configuration of the insertion terminal 26 of the power semiconductor device 108 according to the seventh embodiment of the present invention. As shown in FIG. 14, the insertion terminal 26 is provided with a protrusion 26f at the position of the press-fit portion. The burr 26f is installed so as to engage with the lower surface of the lead after the lead is inserted. The other configuration of the power semiconductor device 108 is the same as that of the power semiconductor device 101 of the first embodiment, and a description thereof is omitted.

  As described above, according to the power semiconductor device 108 according to the seventh embodiment of the present invention, the insertion terminal 26 is provided with the burrs 26f so as to engage with the lower surfaces of the leads after the leads are inserted. The portion 26f is anchored to the lead 18 so that the insertion terminal is less likely to come out and the joining reliability is improved.

  In the first to seventh embodiments, the power semiconductor element functioning as a switching element or a rectifying element may be a general element based on a silicon wafer. However, in the present invention, silicon carbide (SiC ), Gallium nitride (GaN) -based materials, or so-called wide band gap semiconductor materials having a wider band gap than silicon, such as diamond. The power semiconductor device 101 of the present invention has a particularly remarkable effect when a semiconductor element formed using a wide bandgap semiconductor material and capable of operating with a high current capacity and operating at high temperature is used. In particular, it can be suitably used for a power semiconductor element using silicon carbide. The device type is not particularly limited, but may be a MOSFET (Metal Oxide Semiconductor Field-Effect-Transistor) other than the IGBT, or any other vertical semiconductor element.

  Since switching elements and rectifying elements formed of wide band gap semiconductors have lower power loss than elements formed of silicon, it is possible to increase the efficiency of switching elements and rectifying elements. High efficiency can be achieved. In addition, because it has high voltage resistance and high allowable current density, it is possible to reduce the size of switching elements and rectifier elements. By using these reduced switching elements and rectifier elements, power semiconductor devices can also be reduced in size. Or, further increase in current becomes possible. In addition, since it has high heat resistance, it can operate at high temperatures, and it is possible to reduce the size of the heat dissipating fins (coolers) attached to the heat sink and the air cooling of the water cooling part. Large current can be achieved.

  For this reason, the heat capacity can be increased by increasing the cross-sectional area of the insertion terminal. However, when combined with a wired band gap semiconductor, the effect is exhibited and the characteristics of the wide band gap semiconductor can be utilized. Both the switching element and the rectifying element may be formed of a wide band gap semiconductor, or one of the elements may be formed of a wide band gap semiconductor.

Embodiment 8 FIG.
In the present embodiment, the power semiconductor device according to the first to seventh embodiments described above is applied to a power conversion device. Although the present invention is not limited to a specific power converter, hereinafter, a case where the present invention is applied to a three-phase inverter will be described as an eighth embodiment.

  FIG. 15: is a block diagram which shows the structure of the power conversion system to which the power converter device concerning this Embodiment is applied.

  The power conversion system illustrated in FIG. 15 includes a power supply 100, a power conversion device 200, and a load 300. The power source 100 is a DC power source and supplies DC power to the power conversion device 200. The power source 100 can be composed of various types, for example, can be composed of a direct current system, a solar battery, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to the alternating current system. Also good. The power supply 100 may be configured by a DC / DC converter that converts DC power output from the DC system into predetermined power.

  The power conversion device 200 is a three-phase inverter connected between the power supply 100 and the load 300, converts the DC power supplied from the power supply 100 into AC power, and supplies the AC power to the load 300. As shown in FIG. 15, the power conversion device 200 converts a DC power into an AC power and outputs the main conversion circuit 201, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. And.

  The load 300 is a three-phase electric motor that is driven by AC power supplied from the power conversion device 200. Note that the load 300 is not limited to a specific application, and is an electric motor mounted on various electric devices. For example, the load 300 is used as an electric motor for a hybrid vehicle, an electric vehicle, a railway vehicle, an elevator, or an air conditioner.

  Hereinafter, details of the power conversion device 200 will be described. The main conversion circuit 201 includes a switching element and a free wheel diode (not shown). When the switching element switches, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the present embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and respective switching elements. It can be composed of six anti-parallel diodes. Each switching element and each free-wheeling diode of the main conversion circuit 201 are configured by a power semiconductor device corresponding to any of the above-described first to seventh embodiments (described here as the power semiconductor device 101). The six switching elements are connected in series for each of the two switching elements to constitute upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.

  The main conversion circuit 201 includes a drive circuit (not shown) that drives each switching element. However, the drive circuit may be built in the power semiconductor device 101, and what is the power semiconductor device 101? Another configuration may be provided with a drive circuit. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from the control circuit 203 described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is kept on, the drive signal is a voltage signal (on signal) that is equal to or higher than the threshold voltage of the switching element. When the switching element is kept off, the drive signal is a voltage that is equal to or lower than the threshold voltage of the switching element. Signal (off signal).

  The control circuit 203 controls the switching element of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, the time (ON time) during which each switching element of the main converter circuit 201 is to be turned on is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element in accordance with the voltage to be output. Then, a control command (control signal) is supplied to the drive circuit included in the main conversion circuit 201 so that an ON signal is output to the switching element that should be turned on at each time point and an OFF signal is output to the switching element that should be turned off. Is output. In accordance with this control signal, the drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element.

  In the power conversion device according to the present embodiment, since the semiconductor device according to the first to seventh embodiments is applied as the switching element and the free wheel diode of the main conversion circuit 201, the reliability can be improved.

  In the present embodiment, the example in which the present invention is applied to the two-level three-phase inverter has been described. However, the present invention is not limited to this, and can be applied to various power conversion devices. In the present embodiment, a two-level power converter is used. However, a three-level or multi-level power converter may be used. When power is supplied to a single-phase load, the present invention is applied to a single-phase inverter. You may apply. In addition, when power is supplied to a direct current load or the like, the present invention can be applied to a DC / DC converter or an AC / DC converter.

  In addition, the power conversion device to which the present invention is applied is not limited to the case where the load described above is an electric motor. For example, the power source of an electric discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system It can also be used as a device, and can also be used as a power conditioner for a photovoltaic power generation system, a power storage system, or the like.

  It should be noted that the present invention can be freely combined with each other within the scope of the invention, and each embodiment can be appropriately modified or omitted.

2, 22, 23, 24, 25, 26 Insertion terminal, 2a, 22a, 23a, 24a, 26a Press fit part, 2b, 22b, 23b, 24b, 26b Fixed part, 2c, 22c, 26c Linear terminal part, 3 Switching Element, 4 Rectifying element, 5, 50, 51 Lead frame, 6 Sealed body, 9 Aluminum wire, 10 Gold wire, 18, 18a, 18b, 40, 42 Lead, 19, 41, 43, 44, 45 Through hole, 20 lead pattern, 21 external substrate, 22d, 24d notch, 26f burrs, 100 power supply, 101, 102, 103, 104, 105, 106, 107, 108 power semiconductor device, 200 power conversion device, 201 main conversion circuit , 203 Control circuit, 300 load

Claims (18)

A lead frame having a power semiconductor element mounted thereon, a lead pattern connected to the electrode of the power semiconductor element by a wire, and a lead portion provided with a through hole;
A sealing body in which a space between the power semiconductor element, the wire, and the lead pattern is sealed with a sealing resin so that the lead portion is exposed;
An electric power semiconductor device comprising: an insertion terminal that is inserted into the through hole.   The insertion terminal has a press-fit portion that is inserted into the through hole, a terminal portion that is connected to an external substrate, and a fixing portion that connects the press-fit portion and the terminal portion and engages the lead portion. The power semiconductor device according to claim 1.   The power semiconductor device according to claim 2, wherein in the insertion terminal, the fixing portion has a notch in a base portion of the press fit portion.   4. The power semiconductor device according to claim 2, wherein the insertion terminal has the terminal portion having the same shape as the press fit portion. 5.   5. The electric power according to claim 2, wherein the insertion terminal is provided with a burr portion in the press fit portion, and the burr portion engages with the lead portion. 6. Semiconductor device.   6. The insertion terminal according to claim 1, wherein the insertion terminal is inserted in a direction perpendicular to a width direction of the insertion terminal in parallel with a wiring direction of the lead portion. The power semiconductor device according to the above.   The power semiconductor device according to claim 1, wherein the insertion terminal has a cross-sectional area larger than a cross-sectional area of the lead portion.   8. The power semiconductor device according to claim 1, wherein the lead portion is formed to be overlapped in multiple by folding back one end. 9.   9. The power semiconductor device according to claim 1, wherein the lead portion has a thickness larger than that of the lead pattern, and a base thereof is covered with the sealing body. 10. .   10. The power semiconductor device according to claim 1, wherein the lead portion has the circular or slit-shaped through-hole. 11.   11. The power semiconductor device according to claim 1, wherein the lead portion includes at least two or more through holes.   2. The lead part, wherein the insertion terminal connected by a jumper wiring is inserted into the through hole of one lead part and the through hole of another lead part. Item 12. The power semiconductor device according to any one of Items 11.   13. The power semiconductor device according to claim 1, wherein the lead terminal is inserted with the insertion terminal connected by a jumper wiring from the front surface side or the back surface side.   14. The power semiconductor device according to claim 12, wherein the insertion terminal connected by the jumper wiring is formed to be lower than a height of the sealing body.   The power semiconductor device according to claim 1, wherein the power semiconductor element is a wide band gap semiconductor.   The power semiconductor device according to claim 15, wherein the wide band gap semiconductor is a semiconductor using silicon carbide, a gallium nitride-based material, or diamond. Placing a power semiconductor element on the lead pattern of a lead frame having a lead portion and a lead pattern provided with a through hole; and
Connecting the electrode of the power semiconductor element and the lead pattern by a wire;
Sealing the power semiconductor element, the wire, and the lead pattern with a sealing resin so that the lead portion is exposed;
And a step of inserting an insertion terminal into the through hole of the exposed lead portion. A main conversion circuit having the power semiconductor device according to any one of claims 1 to 16 for converting input power and outputting the converted power.
And a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit.

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