JP7199167B2 - Power semiconductor module, power converter, and method for manufacturing power semiconductor module - Google Patents

Description

The present invention relates to a power semiconductor module including a power semiconductor element and a control semiconductor element for controlling the power semiconductor element, a power converter, and a method of manufacturing the power semiconductor module.

In order to reduce the cost of inverter control devices, attempts have been made to reduce the size of control circuit boards. Along with this, power semiconductor modules mounted on control circuit boards are also required to be reduced in cost and size. For this reason, an intelligent power module (hereinafter referred to as IPM) has been manufactured in which not only a power semiconductor chip for electric power but also an IC chip for controlling the semiconductor chip are incorporated in one package. As this IPM, DIP (Dual In-line Package), SIP (Single In-line Package), SOP (Small Outline Package), etc. have been commercialized as package shapes.

In these packages, the leads for connection with the mounting board protrude outward from the insulating mold resin that seals the semiconductor chip or the like, so the package size tends to increase. Accordingly, non-lead type SON (Small Outline Non-leaded Package) and QFN (Quad Flat Non-lead Package) package shapes have been developed for ICs, memories, LSIs, and the like. Moreover, since a semiconductor chip generates a large amount of heat during operation, it is necessary to dissipate the generated heat to the outside of the package.

For example, as in Japanese Patent Laid-Open No. 2002-200012, if the lead portion on which the semiconductor chip is mounted is arranged on the mounting surface side and insulated with mold resin, the insulation of the package is maintained, but heat is not released to the mounting substrate. It becomes difficult to attach cooling fins, etc., and it becomes difficult to cool positively. Therefore, for example, in Japanese Unexamined Patent Application Publication No. 2002-100000, the lead portion on which the semiconductor chip is mounted is exposed to the outside and is actively cooled by attaching a cooling agent or cooling fins.

Japanese Patent Application Laid-Open No. 2002-203936 (paragraphs 0015 to 0020, FIG. 1) JP 2006-86273 A (paragraphs 0008 to 0009, FIG. 1)

However, in the case of the structure in which the lead portion on which the semiconductor chip is mounted is exposed, as in Patent Document 2, in the case of the power semiconductor chip, the mounting surface is at a high voltage, so the exposed lead portion is also at a high voltage. There was a problem that insulation was not maintained.

The present application discloses a technique for solving the above-mentioned problems, which can actively release the heat generated by the semiconductor chip while maintaining the insulation of the package, and can be miniaturized by a non-lead type package. It is an object of the present invention to obtain a power semiconductor module, a power conversion device, and a method of manufacturing the power semiconductor module that can

A power semiconductor module disclosed in the present application includes a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on a substrate mounting surface side, and the first die pad a power semiconductor chip mounted on the second die pad portion; a control semiconductor chip for controlling the power semiconductor chip mounted on the second die pad portion; and a mold resin covering the power semiconductor chip and the control semiconductor chip, The first die pad portion is arranged at a position offset from the external terminal portion via the bent portion in a direction away from the substrate mounting surface, and the second die pad portion is disposed from the external terminal portion via the bent portion. The second die pad portion is arranged at a position offset in a direction away from the board mounting surface, and the offset amount of the second die pad portion is smaller than the offset amount of the first die pad portion.
a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on a substrate mounting surface side; and a power semiconductor chip mounted on the first die pad portion. , a control semiconductor chip that controls the power semiconductor chip mounted on the second die pad portion; and a mold resin that covers the power semiconductor chip and the control semiconductor chip, wherein the first die pad portion is connected to the external terminal portion The second die pad portion is arranged at a position offset in a direction away from the substrate mounting surface via a bent portion, and the second die pad portion is provided on the substrate mounting surface as the external terminal portion.
a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on a substrate mounting surface side; and a power semiconductor chip mounted on the first die pad portion. , a control semiconductor chip that controls the power semiconductor chip mounted on the second die pad portion; and a mold resin that covers the power semiconductor chip and the control semiconductor chip, wherein the first die pad portion is connected to the external terminal portion is offset from the substrate mounting surface in a direction away from the substrate mounting surface via the bent portion, and the second die pad portion is offset from the external terminal portion toward the heat dissipation surface on the side opposite to the substrate mounting surface. The second die pad portion is arranged at a position offset in a direction away from the substrate mounting surface through the portion, and the offset amount of the second die pad portion is smaller than the offset amount of the first die pad portion.
a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on a substrate mounting surface side; and a power semiconductor chip mounted on the first die pad portion. , a control semiconductor chip that controls the power semiconductor chip mounted on the second die pad portion; and a mold resin that covers the power semiconductor chip and the control semiconductor chip, wherein the first die pad portion is connected to the external terminal portion is arranged at a position offset toward the heat dissipation surface on the side opposite to the substrate mounting surface in the direction away from the substrate mounting surface via the bent portion, and the second die pad portion serves as the external terminal portion to the substrate It is characterized by being provided on the mounting surface.

In the method for manufacturing a power semiconductor module disclosed in the present application, a first die pad portion and a second die pad portion connected to a plurality of external terminal portions via bent portions are provided, and the first die pad portion is located on the substrate mounting surface side. preparing a lead frame in which the second die pad is arranged at a position offset in a direction away from the substrate mounting surface side by an offset smaller than the offset of the first die pad, After mounting a power semiconductor chip or a control semiconductor chip on the substrate mounting surface side of the first die pad portion or the second die pad portion of the lead frame or on the heat dissipation surface side opposite to the substrate mounting surface, the control semiconductor chip Alternatively, a step of mounting the power semiconductor chip on the heat dissipation surface side or the substrate mounting surface side of the second die pad portion or the first die pad portion of the lead frame; a third connection of the lead frame between a connection pad portion and a surface electrode of the control semiconductor chip or the power semiconductor chip, a surface electrode of the control semiconductor chip or the power semiconductor chip and the control semiconductor chip and the power semiconductor chip; After wire wiring is performed between the pad portions from the heat radiation surface side or the substrate mounting surface side, the first connection pad portion or the second connection pad portion of the lead frame and the power semiconductor chip or the control semiconductor chip are connected. Between the surface electrode, the surface electrode of the power semiconductor chip or the control semiconductor chip, and the third connection pad portion of the lead frame between the power semiconductor chip and the control semiconductor chip, the substrate mounting surface side or the It is characterized by including a step of wire wiring from the heat radiation surface side and a molding step of covering the power semiconductor chip and the control semiconductor chip with molding resin.

Further, a first die pad portion and a second die pad portion are provided to be connected to the plurality of external terminal portions through the bent portions, respectively, and the first die pad portion is arranged at a position offset in a direction away from the board mounting surface side. preparing a lead frame in which the second die pad portion is arranged on a substrate mounting surface as an external terminal portion; After mounting the control semiconductor chip or the power semiconductor chip on the mounting surface side or the heat radiation surface side opposite to the board mounting surface, respectively, the heat radiation of the second die pad portion or the first die pad portion of the lead frame. a step of mounting on the surface side or the substrate mounting surface side, respectively; after wire wiring between the surface electrode of the power semiconductor chip and the third connection pad portion of the lead frame between the control semiconductor chip and the power semiconductor chip from the heat dissipation surface side or the board mounting surface side; , a first connection pad portion or a second connection pad portion of the lead frame and a surface electrode of the power semiconductor chip or the control semiconductor chip, a surface electrode of the power semiconductor chip or the control semiconductor chip, the power semiconductor chip and the control wire wiring between the third connection pad portions of the lead frame between the semiconductor chips from the substrate mounting surface side or the heat radiation surface side; and forming the power semiconductor chip and the control semiconductor chip with molding resin. and a covering molding step.

According to the present application, the heat generated from the power semiconductor chip is dissipated by arranging the die pad portion on which the power semiconductor chip is mounted at a position offset from the external terminal portion via the bent portion in the direction away from the substrate mounting surface. It is possible to obtain a power semiconductor module in which heat is easily dissipated from the heat dissipating surface opposite to the substrate mounting surface.

1 is a plan view showing the configuration of a power semiconductor module according to Embodiment 1, viewed from the surface side; FIG. 1 is a cross-sectional view showing the configuration of a power semiconductor module according to Embodiment 1; FIG. 2 is a plan view showing the entire lead frame used in the power semiconductor module according to Embodiment 1; FIG. 4 is a cross-sectional view showing an offset amount of a control semiconductor chip in the power semiconductor module according to Embodiment 1; FIG. 4 is a flow chart diagram showing a method for manufacturing a power semiconductor module according to Embodiment 1. FIG. 4 is a cross-sectional view showing another configuration of the power semiconductor module according to Embodiment 1; FIG. 4 is a cross-sectional view showing another configuration of the power semiconductor module according to Embodiment 1; FIG. It is the top view seen from the surface side which shows the structure of the conventional power semiconductor module. FIG. 3 is a cross-sectional view showing the configuration of a conventional power semiconductor module; FIG. 10 is a plan view showing the entire lead frame used in a conventional power semiconductor module; FIG. 10 is a plan view showing the configuration of a power semiconductor module according to Embodiment 2, viewed from the surface side; FIG. 10 is a plan view showing the configuration of the power semiconductor module according to Embodiment 2, viewed from the back side; FIG. 8 is a cross-sectional view showing the configuration of a power semiconductor module according to Embodiment 2; FIG. 8 is a plan view showing the entire lead frame used in the power semiconductor module according to Embodiment 2; FIG. 11 is a cross-sectional view showing an offset amount of a control semiconductor chip in the power semiconductor module according to Embodiment 2; FIG. 11 is a plan view showing the configuration of a power semiconductor module according to Embodiment 3, viewed from the surface side; FIG. 11 is a plan view showing the configuration of a power semiconductor module according to Embodiment 3, viewed from the back side; FIG. 11 is a cross-sectional view showing the configuration of a power semiconductor module according to Embodiment 3; FIG. 11 is a plan view showing the entire lead frame used in the power semiconductor module according to Embodiment 3; FIG. 11 is a cross-sectional view showing an offset amount of a control semiconductor chip in a power semiconductor module according to Embodiment 3; FIG. 12 is a block diagram showing the configuration of a power conversion system to which a power conversion device according to Embodiment 4 is applied;

Embodiment 1.
FIG. 1 is a plan view showing the configuration of power semiconductor module 101 according to Embodiment 1, viewed from the surface side. 2 is a cross-sectional view taken along line AA of FIG. 1. FIG. FIG. 3 is a plan view showing the entire lead frame 111 used in the power semiconductor module 101, and the area S1 in FIG. 3 corresponds to FIG. 1, illustration of the mold resin 26 is omitted.

As shown in FIGS. 1, 2 and 3, the power semiconductor module 101 includes a power semiconductor chip 22, a control semiconductor chip 23, a power die pad 14a as a first die pad portion of a lead frame 111 on which the power semiconductor chip 22 is mounted, A control die pad 15a as a second die pad portion of a lead frame 111 on which a control semiconductor chip 23 is mounted, a bent portion 14b and an external terminal portion 14c of the lead frame 111 connected to the power die pad 14a, and a lead frame 111 connected to the control die pad 15a. Wire wiring 38 connecting the bent portion 15 b and the external terminal portion 15 c , the surface electrode of the power semiconductor chip 22 and the surface electrode of the control semiconductor chip 23 , and the first wiring 37 connecting the surface electrode of the power semiconductor chip 22 and the wire wiring 37 . The connection pad 10a which is the connection pad portion, the bent portion 10b of the lead frame 111 connected to the connection pad 10a and the external terminal portion 10c, the surface electrode of the control semiconductor chip 23 and the second connection pad portion connected via the wire wiring 39. A connection pad 11a, a bent portion 11b of a lead frame 111 connected to the connection pad 11a, an external terminal portion 11c, and a mold resin 26 are provided.

The power semiconductor chip 22 and the control semiconductor chip 23 are mounted on the board mounting surface 31 side of the power semiconductor module 101 of the power die pad 14a and the control die pad 15a, respectively. The control semiconductor chip 23 is a semiconductor that controls the power semiconductor chip 22 and has functions such as gate driving and current detection of the power semiconductor chip 22 . The power semiconductor chip 22 and the control semiconductor chip 23 are mounted using solders 28 and 29 on the power die pad 14a and the control die pad 15a, respectively. For mounting, instead of the solders 28 and 29, a conductive adhesive typified by Ag paste, or a sintered material of Ag or Cu, or the like may be used. Furthermore, components such as capacitors and resistors may be implemented as required. Also, the number of control semiconductor chips 23 is not limited to one, and a plurality of chips may be mounted in the power semiconductor module 101 .

The power semiconductor chip 22 employs a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), a diode, or a power MOS-FET (Metal-Oxide-Semiconductor Field-Effect Transistor). Here, a MOS-FET is used as the power semiconductor chip 22 .

Control semiconductor chips such as HVIC (High Voltage IC) and LVIC (Low-Voltage Integrated Circuit) are adopted as the control semiconductor chip 23 . In the embodiment of the present application, the control semiconductor chip 23 includes an HVIC (control semiconductor chip 23 on the upper side in FIG. 1) that controls the power semiconductor chip 22 on the high voltage side and an LVIC (control semiconductor chip 23 on the upper side in FIG. 1) that controls the power semiconductor chip 22 on the low voltage side (FIG. 1 under the control semiconductor chip 23).

The lead frame 111 is made of Cu or Al and its alloy. The surface may be plated with Ni or Ag to prevent oxidation. The wire wirings 37, 38, and 39 are made of materials such as Al, Cu, Au, Ag, and their alloys, and have a cylindrical shape with a diameter of about 10 μm to about 500 μm. method is used. The molding resin 26 is made of an insulating epoxy base material mixed with a material such as silica or alumina to improve heat conduction.

FIG. 4 is a diagram for explaining the position of the power semiconductor chip 22 in the power semiconductor module 101. As shown in FIG. As shown in FIG. 4, the power die pad 14a on which the power semiconductor chip 22 is mounted is offset from the external terminal portion 14c of the lead frame 111 in the direction away from the substrate mounting surface 31 via the bent portion 14b. The offset amount is an offset amount L1 that does not expose the lead frame 111 to the outside when sealed with the mold resin 26, and can be arbitrarily selected as long as the power die pad 14a is insulated from the outside. However, in order to improve the cooling performance, the thickness of the mold resin 26 between the power die pad 14a and the heat dissipation surface 30 on the outside of the module should be thin.

Also, although the power die pad 14a and the control die pad 15a have the same offset amount in FIG. 2, there is no problem even if they are different. By offsetting the power die pad 14a and the control die pad 15a from the external terminal portions 14c and 15c, it is possible to expose only the external terminal portions 14c and 15c which will be joint portions with the mounting substrate during mounting. As a result, it becomes easier to control the area where the solder is wetted and spread during board mounting, and the occurrence of defects during board mounting can be suppressed.

In addition, the wire wirings 37, 38, 39 are not exposed from the mold resin, and the wire wirings 37, 38, 39 having different potentials do not come into contact with the power semiconductor chip 22, the control semiconductor chip 23, etc., and insulation is maintained. distance is required. Ag or the like is partially applied on the lead frame 111 at the locations where the wire wirings 37, 38, and 39 are joined and the locations where the power semiconductor chip 22 and the control semiconductor chip 23 are mounted, in order to improve bonding and mounting. It is desirable that the surface is plated with

Next, a method for manufacturing power semiconductor module 101 according to Embodiment 1 will be described with reference to FIG. FIG. 5 is a flow chart showing the procedure for manufacturing the power semiconductor module 101 according to the first embodiment.

First, a lead frame 111 is prepared in which the position of the power die pad 14a on which the power semiconductor chip 22 is mounted is offset from the external terminal portion 14c of the lead frame 111 in the direction away from the board mounting surface 31 via the bent portion 14b. Then, the power semiconductor chip 22 and the control semiconductor chip 23 are mounted on the substrate mounting surface 31 side of the power die pad 14a and the control die pad 15a of the lead frame 111 using solders 28 and 29, respectively (mounting step, step S501).

Subsequently, the power semiconductor chip 22 and the control semiconductor chip 23 are connected to the lead frame 111 using the wire wirings 37, 38 and 39 (wire connection, step S502). At this time, between the power semiconductor chip 22 and the lead frame 111 (connection pads 10a), between the power semiconductor chip 22 and the control semiconductor chip 23, and between the control semiconductor chip 23 and the lead frame 111 (connection pads 11a) If the wire wirings 37, 38 and 39 are of the same type, they can be joined at the same time. It is desirable to select suitable wiring. Also, the order in which these wire wirings 37, 38, and 39 are joined can be arbitrarily selected.

Next, using the mold resin 26, only the external terminal portions 10c, 11c, 14c, and 15c to be mounted on the substrate are exposed, and other members are sealed (mold step, step S503). As a molding method, transfer molding may be used, but it is preferable to use compression molding that can suppress deformation of wire wiring.

Subsequently, the portion of the lead frame 111 that is not covered with the mold resin 26 is plated (plating step, step S504). As the plating, Sn plating, Sn--Cu plating, or the like is selected in order to cope with soldering at the time of substrate mounting. If the entire surface of the lead frame is plated in advance, or if it is determined that the surface treatment is unnecessary for soldering when mounting on the board, this plating may be omitted.

Finally, each power semiconductor module 101 is cut by a die press or the like and separated into individual power semiconductor modules as SON (Small Outline No Lead Package) type or QFN (Quad For Non-Lead Package) type packages. 101 is obtained (cutting step, step S505).

During operation of the power semiconductor module 101, the power semiconductor chip 22 mainly generates heat. After the power semiconductor module 101 is mounted on the substrate, the heat generated from the power semiconductor chip 22 is released from the heat dissipation surface 30 opposite to the substrate mounting surface 31 .

Therefore, a thermally conductive insulating sheet having a higher thermal conductivity than the mold resin 26 may be separately added to the heat dissipation surface 30 side of the power die pad 14a of the power semiconductor module 101 . FIG. 6 shows a cross-sectional view of a power semiconductor module 101 having a heat conductive insulating sheet 40 on the side of the heat dissipation surface 30 of the power die pad 14a. Thermally conductive insulating sheets include, for example, epoxy sheets filled with boron nitride, alumina, or silica fillers. As a result, the heat generated from the power semiconductor chip 22 can be easily radiated locally from the heat radiation surface 30 via the power die pad 14a and the thermally conductive insulating sheet 40 .

Moreover, a metallic cooling fin may be connected to the heat radiation surface 30 side of the power semiconductor module 101 . FIG. 7 shows a cross-sectional view of a power semiconductor module 101 having cooling fins 41 on the heat radiation surface 30 side of the power semiconductor module 101 via heat radiation grease 24 . The heat dissipation grease 24 that connects the cooling fins 41 includes, for example, silicone-based thermal grease. Existing screws or clips are used to fix the cooling fins 41 . Cooling fins include, for example, metal such as aluminum. By adding the cooling fins 41, it becomes possible to actively dissipate heat, and it is possible to drive the power semiconductor chip 22 under conditions that generate more heat.

The power semiconductor module 101, which is such a SON type or QFN type package, does not require leads for insertion terminals, as compared with a conventional DIP type package. FIG. 8 shows a plan view of the configuration of a power semiconductor module having a conventional DIP type package, viewed from the surface side. 9 is a cross-sectional view taken along line DD of FIG. 8. FIG. FIG. 10 is a plan view showing the entire lead frame 120 used in a conventional power semiconductor module, and the area S0 in FIG. 10 corresponds to FIG. 8, illustration of the mold resin 26 is omitted.

As shown in FIG. 9, the conventional power semiconductor module has leads 25 for insertion terminals. 3 and 10, the lead frame 111 and the lead frame 120 have the same vertical width, but the power semiconductor module 101 has a larger number of power semiconductor modules than the lead frame 101, although the horizontal width is shorter. many. From this, it can be seen that the number of power semiconductor modules that can be obtained from one lead frame 111 is improved. Therefore, by increasing the number of power semiconductor modules 101 that can be obtained from one lead frame 111, it is possible to shorten the time required for molding.

As described above, according to the power semiconductor module 101 of the first embodiment, the lead frame 111 provided with the power die pad 14a and the control die pad 15a connected to the external terminal portions 14c and 15c provided on the substrate mounting surface 31 , a power semiconductor chip 22 mounted on the power die pad 14a, a control semiconductor chip 23 for controlling the control semiconductor chip 23 mounted on the control die pad 15a, and a mold resin 26 covering the power semiconductor chip 22 and the control semiconductor chip 23. The power die pad 14a is arranged at a position offset from the external terminal portion 14c via the bent portion 14b in the direction away from the substrate mounting surface 31, so that the heat generated from the power semiconductor chip is transferred to the substrate. A highly reliable power semiconductor module can be obtained in which heat is easily dissipated from the heat dissipating surface opposite to the mounting surface. In addition, as compared with the conventional power semiconductor module, the leads for the insertion terminals are not required, so that miniaturization can be achieved. In addition, since the number of power semiconductor modules that can be obtained from one lead frame increases, it is possible to shorten the time required for molding each power semiconductor module.

In addition, since the power die pad 14a is provided with the thermally conductive insulating sheet 40 between the substrate mounting surface 31 and the heat radiation surface 30 on the opposite side, heat can be dissipated locally from the heat radiation surface. Furthermore, since the heat radiation surface 30 opposite to the substrate mounting surface 31 is provided with the cooling fins 41, it is possible to positively radiate heat, and the power semiconductor chip can be driven under the condition that it generates more heat. .

Embodiment 2.
In the first embodiment, the power semiconductor chip 22 and the control semiconductor chip 23 are mounted on the substrate mounting surface 31 side of the power semiconductor module 101 of the power die pad 14a and the control die pad 15a. , the case where the control semiconductor chip 23 is mounted on the side of the heat radiation surface 30 opposite to the substrate mounting surface 31 of the control die pad 15a.

FIG. 11 is a plan view showing the configuration of power semiconductor module 102 according to Embodiment 2, viewed from the front side, and FIG. 12 is a plan view viewed from the back side. 13 is a cross-sectional view taken along line BB in FIGS. 11 and 12. FIG. FIG. 14 is a plan view showing the entire lead frame 112 used in the power semiconductor module 102, and the region S2 of FIG. 14 corresponds to FIGS. 11 and 12. FIG. 11 and 12, illustration of the mold resin 26 is omitted.

As shown in FIGS. 11, 12, 13, and 14, in the power semiconductor module 102, the control semiconductor chip 23 is mounted on the side of the heat radiation surface 30 opposite to the substrate mounting surface 31 of the control die pad 15a. A wire wiring 38 between the control semiconductor chip 23 and the power semiconductor chip 22 is connected through both surfaces of the connection pad 19a, which is the third connection pad portion.

FIG. 15 is a diagram for explaining the positions of the power semiconductor chip 22 and the control semiconductor chip 23 in the power semiconductor module 102. As shown in FIG. As shown in FIG. 15, the control die pad 15a on which the control semiconductor chip 23 is mounted is offset from the external terminal portion 15c of the lead frame 112 in the direction away from the substrate mounting surface 31 via the bent portion 15b. The offset amount is an offset amount L2 smaller than the offset amount L1 of the power die pad 14a on which the power semiconductor chip 22 is mounted, and can be arbitrarily selected as long as the control die pad 15a is insulated from the outside.

Also, by offsetting the power die pad 14a and the control die pad 15a from the external terminal portions 14c and 15c, only the external terminal portions 14c and 15c, which are to be bonded to the mounting substrate during mounting, can be exposed. As a result, it becomes easier to control the area where the solder is wetted and spread during board mounting, and the occurrence of defects during board mounting can be suppressed.

In FIG. 13, the connection pad 19a is offset similarly to the power die pad 14a, but it can be arbitrarily selected as long as it is larger than the offset amount L2 of the control die pad 15a and equal to or smaller than the offset amount L1. However, the wire wiring 38 must be routed so as not to contact the power semiconductor chip 22, the control semiconductor chip 23, and the lead frame of the different potential so as to cause dielectric breakdown. Therefore, by adjusting the amount of offset of the connection pad 19a, the above-mentioned contact or the like can be prevented. Other configurations of the power semiconductor module 102 according to the second embodiment are the same as those of the power semiconductor module 101 according to the first embodiment, and corresponding parts are denoted by the same reference numerals, and descriptions thereof are omitted.

Next, a method for manufacturing power semiconductor module 102 according to the second embodiment will be described. A method of manufacturing the power semiconductor module 102 is basically the same as that of the first embodiment, and will be described with reference to FIG. 5 used in the first embodiment.

First, the power die pad 14a on which the power semiconductor chip 22 is mounted is set at a position separated from the substrate mounting surface 31 by the offset amount L1 via the bent portion 14b with respect to the external terminal portion 14c of the lead frame 112. The control die pad 15a on which the chip 23 is mounted is set at a position separated from the substrate mounting surface 31 via the bent portion 15b with respect to the external terminal portion 15c of the lead frame 112 by an offset amount L2 smaller than the offset amount L1. A frame 112 is prepared, and the power semiconductor chip 22 is mounted on the substrate mounting surface 31 side of the power die pad 14a of the lead frame 112 using solder 28. After that, the lead frame 112 is turned over, and the control semiconductor chip 23 is led. The control die pad 15a of the frame 112 is mounted on the heat dissipation surface 30 side using the solder 29 (mounting step, step S501).

Although the control semiconductor chip 23 is mounted after the power semiconductor chip 22 is mounted in the second embodiment, the power semiconductor chip 22 may be mounted after the control semiconductor chip 23 is mounted. Also, as in the first embodiment, instead of the solders 28 and 29, a conductive adhesive or the like may be used.

Subsequently, wire wirings 38 and 39 are used to connect between the control semiconductor chip 23 and the lead frame 112 (connection pads 11a) and between the surface electrodes of the control semiconductor chip 23 and the connection pads 19a. 112 is turned over, and the power semiconductor chip 22 and the lead frame 112 (connection pad 10a) are connected, and the surface electrode of the power semiconductor chip 22 and the connection pad 19a are connected (wire connection, step S502).

At this time, after the wire connection on the control semiconductor chip 23 side, the wire wiring 38 is already bonded to the heat radiation surface 30 side of the connection pad 19a. When doing so, it is necessary to prevent the jig for fixing the lead frame 112 and the stage on which the lead frame 112 is placed from interfering with the wire wiring 38 on the control semiconductor chip 23 side.

Note that the wire wiring 38 may be bonded to the same location on both sides of the connection pad 19a, respectively, or even if the bonding position of the wire wiring 38 is changed on the substrate mounting surface 31 side and the heat radiation surface 30 side of the connection pad 19a, the wire There is no problem if the wiring 38 can be joined without breaking. Further, in the second embodiment, the wire wiring on the control semiconductor chip 23 side is performed first, and then the wire wiring on the power semiconductor chip 22 side is performed. 22 side wiring may be used. Moreover, the wire wiring on the control semiconductor chip 23 side and the wire wiring on the power semiconductor chip 22 side may be performed simultaneously from both sides. In this way, wire wiring can be performed from both sides at the same time, thereby shortening the time required for wire wiring.

As for the processes from step S503 to step S505, the power semiconductor module 102 is obtained as a SON type or QFN type package by performing the same operations as in the first embodiment.

Since the offset amount L1 of the control die pad 15a differs from the offset amount L2 of the power die pad 14a in this way, the power semiconductor chip 22, which is a heat source, is separated from the control semiconductor chip 23, and the control semiconductor chip 23 malfunctions due to heat. Actuation and increase in leakage current can be reduced. Also, the thickness of the power semiconductor module can be reduced by the area V in the conventional power semiconductor module of FIG. As a result, the amount of mold resin 26 used is reduced accordingly, and cost reduction can be achieved. 14 and 10, the vertical width of lead frame 112 and lead frame 120 is the same, but the horizontal width is shorter. Since the number of power semiconductor modules 102 is larger than that of the lead frame 112, the number of power semiconductor modules 102 obtained from one lead frame 112 is improved, thereby shortening the time required for molding each power semiconductor module. becomes possible.

As described above, according to the power semiconductor module 102 of the second embodiment, the control die pad 15a is arranged at a position offset from the external terminal portion 15c in the direction away from the substrate mounting surface 31 via the bent portion 15b. Since the offset amount of the control die pad 15a is set to be smaller than the offset amount of the power die pad 14a, not only the effects of the first embodiment but also the power semiconductor chip serving as the heat source is separated from the control semiconductor chip, resulting in heat generation. It is possible to reduce the malfunction of the control semiconductor chip and the increase in leakage current due to the above, and obtain a power semiconductor module with higher reliability. Also, compared with the power semiconductor module shown in FIG. 9, the mold resin can be made smaller by the amount of the V region, so the amount of mold resin used is reduced accordingly, and cost reduction can be realized. Moreover, the wire wiring on the control semiconductor chip 23 side and the wire wiring on the power semiconductor chip 22 side may be performed simultaneously from both sides. In this way, wire wiring can be performed from both sides at the same time, thereby shortening the time required for wire wiring.

Embodiment 3.
In the first and second embodiments, the control die pad 15a on which the control semiconductor chip 23 is mounted is directed away from the substrate mounting surface 31 via the bent portion 15b with respect to the external terminal portions 15c of the lead frames 111 and 112. In the third embodiment, a description will be given of a case in which the offset is not performed.

FIG. 16 is a plan view showing the configuration of power semiconductor module 103 according to Embodiment 3 as seen from the front side, and FIG. 17 is a plan view as seen from the back side. FIG. 18 is a cross-sectional view taken along arrow CC in FIGS. 16 and 17. FIG. FIG. 19 is a plan view showing the entire lead frame 113 used in the power semiconductor module 103, and the region S3 of FIG. 19 corresponds to FIGS. 16 and 17. FIG. 16 and 17, illustration of the mold resin 26 is omitted.

As shown in FIGS. 16, 17, 18, and 19, in power semiconductor module 103, control semiconductor chip 23 is mounted on the heat dissipation surface of control die pad 15a on the opposite side of substrate mounting surface 31, as in the second embodiment. 30 side, and wire wiring 38 between the control semiconductor chip 23 and the power semiconductor chip 22 is connected via both surfaces of the connection pad 19a.

FIG. 20 is a diagram for explaining the positions of the power semiconductor chip 22 and the control semiconductor chip 23 in the power semiconductor module 103. As shown in FIG. As shown in FIG. 18, unlike the first and second embodiments, the control die pad 15a on which the control semiconductor chip 23 is mounted is not offset, and the control die pad 15a itself is bonded to the mounting substrate during mounting. A portion of the external terminal portion is exposed on the substrate mounting surface. Other configurations of the power semiconductor module 103 according to Embodiment 3 are the same as those of the power semiconductor module 101 according to Embodiment 1, and corresponding parts are denoted by the same reference numerals, and descriptions thereof are omitted.

Next, a method for manufacturing power semiconductor module 103 according to Embodiment 3 will be described. A method of manufacturing the power semiconductor module 103 is basically the same as that of the first embodiment, and will be described with reference to FIG. 5 used in the first embodiment.

First, the power die pad 14a on which the power semiconductor chip 22 is mounted is set at a position separated from the board mounting surface 31 by the offset amount L1 via the bent portion 14b with respect to the external terminal portion 14c of the lead frame 113. A lead frame 113 is prepared in which a control die pad 15a on which a chip 23 is mounted is set at a position where a part thereof is exposed on a substrate mounting surface 31 as an external terminal portion of the lead frame 113 without offset, and a power semiconductor chip 22 is mounted. The power die pad 14 a of the lead frame 113 is mounted on the board mounting surface 31 side of the power die pad 14 a of the lead frame 113 using solder 28 . The control semiconductor chip 23 is mounted on the heat dissipation surface 30 side of the control die pad 15a of the lead frame 113 using solder 29 (mounting step, step S501).

As for the processes from step S502 to step S505, the power semiconductor module 102 is obtained as a SON type or QFN type package by performing the same operation as in the second embodiment.

In this manner, the power semiconductor chip 22 serving as a heat source is separated from the control semiconductor chip 23 by the amount of offset L1, and malfunction of the control semiconductor chip 23 and an increase in leak current due to heat can be reduced. Also, as in the second embodiment, the thickness of the power semiconductor module can be reduced by the area V in the conventional power semiconductor module in FIG. As a result, the amount of mold resin 26 used is reduced accordingly, and cost reduction can be achieved. 19, 3, and 14, the elimination of the offset of the control die pad 15a eliminates the need for the external terminal portions 14c, 15c, the bent portions 14b, 15b, and the routing portion. Since the width is reduced by , the size of the module can be reduced, the number of power semiconductor modules obtained from one lead frame 113 is increased, and the time required for molding can be shortened.

As described above, according to the power semiconductor module 103 according to the third embodiment, the control die pad 15a is provided as an external terminal portion so as to be exposed on the substrate mounting surface 31 without offset. In addition to this effect, the power semiconductor chip, which is a heat source, is separated from the control semiconductor chip as much as possible, which further reduces malfunctions of the control semiconductor chip and increases in leakage current due to heat, and further increases reliability. A power semiconductor module can be obtained. Also, compared with the power semiconductor module shown in FIG. 9, the mold resin can be made smaller by the amount of the V region, so the amount of mold resin used is reduced accordingly, and cost reduction can be achieved. In addition, since the offset of the control die pad is eliminated, the external terminal portion, bent portion, and routing portion are not required, and the lateral width is reduced accordingly, so that the size of the module can be reduced. The number of semiconductor modules that can be obtained is improved, and the time required for molding can be shortened. Moreover, the wire wiring on the control semiconductor chip 23 side and the wire wiring on the power semiconductor chip 22 side may be performed simultaneously from both sides. In this way, wire wiring can be performed from both sides at the same time, thereby shortening the time required for wire wiring.

Embodiment 4.
Embodiment 4 is obtained by applying the power semiconductor modules according to Embodiments 1 to 3 described above to a power converter. Although the present application is not limited to a specific power converter, a case where the present application is applied to a three-phase inverter will be described below as a fourth embodiment.

FIG. 21 is a block diagram showing the configuration of a power conversion system to which the power converter according to Embodiment 4 is applied.

The power conversion system shown in FIG. 21 includes a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power converter 200 . The power supply 100 can be composed of various things, for example, it can be composed of a DC system, a solar battery, a storage battery, or it can be composed of a rectifier circuit or an AC/DC converter connected to an AC system. good too. Also, the power supply 100 may be configured by a DC/DC converter that converts DC power output from the DC system into predetermined power.

Power converter 200 is a three-phase inverter connected between power supply 100 and load 300 , converts DC power supplied from power supply 100 into AC power, and supplies AC power to load 300 . As shown in FIG. 21, the power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, and a control circuit 203 that outputs a control signal for controlling the main conversion circuit 201 to the main conversion circuit 201. and

The load 300 is a three-phase electric motor driven by AC power supplied from the power converter 200 . The load 300 is not limited to a specific application, but is an electric motor mounted on various electrical equipment, for example, a hybrid vehicle or an electric vehicle, a railway vehicle, an elevator, or an electric motor for an air conditioner.

Details of the power converter 200 will be described below. The main conversion circuit 201 includes a switching element and a freewheeling diode (not shown). By switching the switching element, the DC power supplied from the power supply 100 is converted into AC power and supplied to the load 300 . Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the fourth embodiment is a two-level three-phase full bridge circuit, and has six switching elements and It can consist of six freewheeling diodes in anti-parallel. Each switching element and each free wheel diode of the main conversion circuit 201 is configured by a power semiconductor module (here, the power semiconductor module 101 will be described) corresponding to one of the first to third embodiments described above. Six switching elements are connected in series every two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. Output terminals of the upper and lower arms, that is, three output terminals of the main conversion circuit 201 are connected to the load 300 .

Further, the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element. A configuration including a circuit may be employed. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies it to the control electrode of the switching element of the main conversion circuit 201 . Specifically, in accordance with a control signal from the control circuit 203, which will be described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When maintaining the switching element in the ON state, the driving signal is a voltage signal (ON signal) equal to or higher than the threshold voltage of the switching element, and when maintaining the switching element in the OFF state, the driving signal is a voltage equal to or less than the threshold voltage of the switching element. signal (off signal).

The control circuit 203 controls the switching elements of the main converter circuit 201 so that desired power is supplied to the load 300 . Specifically, based on the power to be supplied to the load 300, the time (on time) during which each switching element of the main conversion circuit 201 should be in the ON state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) to the drive circuit provided in the main conversion circuit 201 so that an ON signal is output to the switching element that should be in the ON state at each time point, and an OFF signal is output to the switching element that should be in the OFF state. to output The drive circuit outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

In the power conversion device according to Embodiment 4, since the semiconductor device according to Embodiments 1 to 3 is applied as the switching element and the freewheel diode of the main conversion circuit 201, reliability can be improved.

In the fourth embodiment, an example in which the present application is applied to a two-level three-phase inverter has been described, but the present application is not limited to this, and can be applied to various power converters. In the fourth embodiment, a two-level power conversion device is used, but a three-level or multi-level power conversion device may be used. I don't mind. Moreover, when power is supplied to a DC load or the like, the present invention can be applied to a DC/DC converter or an AC/DC converter.

In addition, the power conversion device to which the present application is applied is not limited to the case where the above-mentioned load is an electric motor. It can also be used as a power conditioner such as a photovoltaic power generation system or an electric storage system.

While this application describes various exemplary embodiments and examples, various features, aspects, and functions described in one or more embodiments may not apply to particular embodiments. can be applied to the embodiments singly or in various combinations. Accordingly, numerous variations not illustrated are envisioned within the scope of the technology disclosed herein. For example, modification, addition or omission of at least one component, extraction of at least one component, and combination with components of other embodiments shall be included.

14a power die pad 14b bending portion 14c external terminal portion 15a control die pad 15b bending portion 15c external terminal portion 22 power semiconductor chip 23 control semiconductor chip 26 mold resin 30 heat dissipation surface 31 substrate mounting surface 101 Power semiconductor module, L1 Offset amount.

Claims (13)

a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on the substrate mounting surface side;
a power semiconductor chip mounted on the first die pad;
a control semiconductor chip that controls the power semiconductor chip mounted on the second die pad;
a mold resin covering the power semiconductor chip and the control semiconductor chip,
The first die pad portion is arranged at a position offset from the external terminal portion via a bent portion in a direction away from the substrate mounting surface,
The second die pad portion is arranged at a position offset from the external terminal portion in a direction away from the board mounting surface via the bent portion, and the offset amount of the second die pad portion is the same as that of the first die pad portion. A power semiconductor module, wherein the offset amount is smaller than the offset amount. a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on the substrate mounting surface side;
a power semiconductor chip mounted on the first die pad;
a control semiconductor chip that controls the power semiconductor chip mounted on the second die pad;
a mold resin covering the power semiconductor chip and the control semiconductor chip,
The first die pad portion is arranged at a position offset from the external terminal portion via a bent portion in a direction away from the substrate mounting surface,
The power semiconductor module, wherein the second die pad portion is provided on the substrate mounting surface as the external terminal portion. a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on the substrate mounting surface side;
a power semiconductor chip mounted on the first die pad;
a control semiconductor chip that controls the power semiconductor chip mounted on the second die pad;
a mold resin covering the power semiconductor chip and the control semiconductor chip;
with
The first die pad portion is arranged at a position offset from the external terminal portion toward the heat dissipation surface on the opposite side of the substrate mounting surface in a direction away from the substrate mounting surface via the bent portion,
The second die pad portion is arranged at a position offset from the external terminal portion in a direction away from the board mounting surface via the bent portion, and the offset amount of the second die pad portion is the same as that of the first die pad portion. A power semiconductor module, wherein the offset amount is smaller than the offset amount. a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on the substrate mounting surface side;
a power semiconductor chip mounted on the first die pad;
a control semiconductor chip that controls the power semiconductor chip mounted on the second die pad;
a mold resin covering the power semiconductor chip and the control semiconductor chip;
with
The first die pad portion is arranged at a position offset from the external terminal portion toward the heat dissipation surface on the opposite side of the substrate mounting surface in a direction away from the substrate mounting surface via the bent portion,
The power semiconductor module, wherein the second die pad portion is provided on the substrate mounting surface as the external terminal portion. The power semiconductor chip is mounted on the substrate mounting surface side of the first die pad portion, and the control semiconductor chip is mounted on the heat dissipation surface side of the second die pad portion opposite to the substrate mounting surface. The power semiconductor module according to any one of claims 1 to 4 . a first connection pad portion of the lead frame connected to the surface electrode of the power semiconductor chip via wire wiring;
The power semiconductor according to any one of claims 1 to 5 , further comprising a second connection pad portion of the lead frame connected to the surface electrode of the control semiconductor chip via wire wiring. module. a third connection pad portion of the lead frame between the power semiconductor chip and the control semiconductor chip, the surface electrode of the power semiconductor chip and the surface electrode of the control semiconductor chip and the third connection pad portion, respectively; 6. The power semiconductor module according to claim 5 , wherein the and are connected through wire wiring. 8. The power according to any one of claims 1 to 7 , wherein the first die pad section is provided with a thermally conductive insulating sheet between the board mounting surface and the heat dissipation surface on the opposite side. semiconductor module. 9. The power semiconductor module according to any one of claims 1 to 8 , further comprising cooling fins on a heat radiation surface opposite to the substrate mounting surface. a main conversion circuit having the power semiconductor module according to any one of claims 1 to 9 , for converting input power and outputting the power;
and a control circuit that outputs a control signal for controlling the main conversion circuit to the main conversion circuit. A first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions via bent portions are provided, and the first die pad portion is arranged at a position offset in a direction away from the board mounting surface side, A lead frame is prepared in which the second die pad portion is arranged at a position separated from the substrate mounting surface by an offset amount smaller than the offset amount of the first die pad portion, and the power semiconductor chip or the control semiconductor chip is mounted on the lead frame. After mounting the first die pad portion or the second die pad portion on the substrate mounting surface side or the heat dissipation surface side opposite to the substrate mounting surface, the control semiconductor chip or the power semiconductor chip is mounted on the second die pad portion of the lead frame. a step of mounting the die pad portion or the first die pad portion on the heat dissipation surface side or the substrate mounting surface side;
A second connection pad portion or a first connection pad portion of the lead frame and a surface electrode of the control semiconductor chip or the power semiconductor chip, a surface electrode of the control semiconductor chip or the power semiconductor chip, the control semiconductor chip and the power semiconductor After wiring from the heat dissipation surface side or the board mounting surface side between the respective third connection pad portions of the lead frame between chips, the first connection pad portion or the second connection pad of the lead frame is connected. and a surface electrode of the power semiconductor chip or the control semiconductor chip, and a third connection pad portion of the lead frame between the surface electrode of the power semiconductor chip or the control semiconductor chip and the power semiconductor chip and the control semiconductor chip. wire wiring from the substrate mounting surface side or the heat dissipation surface side between each of
and a molding step of covering the power semiconductor chip and the control semiconductor chip with molding resin. A first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions via bent portions are provided, and the first die pad portion is arranged at a position offset in a direction away from the board mounting surface side, A lead frame having a second die pad portion provided as an external terminal portion on a substrate mounting surface is prepared, and a power semiconductor chip or a control semiconductor chip is mounted on the substrate mounting surface of the first die pad portion or the second die pad portion of the lead frame. side or the heat dissipation surface side opposite to the board mounting surface, the control semiconductor chip or the power semiconductor chip is mounted on the second die pad portion of the lead frame or the heat dissipation surface side of the first die pad portion. Alternatively, a step of respectively mounting on the substrate mounting surface side;
A second connection pad portion or a first connection pad portion of the lead frame and a surface electrode of the control semiconductor chip or the power semiconductor chip, a surface electrode of the control semiconductor chip or the power semiconductor chip, the control semiconductor chip and the power semiconductor After wiring from the heat dissipation surface side or the board mounting surface side between the respective third connection pad portions of the lead frame between chips, the first connection pad portion or the second connection pad of the lead frame is connected. and a surface electrode of the power semiconductor chip or the control semiconductor chip, and a third connection pad portion of the lead frame between the surface electrode of the power semiconductor chip or the control semiconductor chip and the power semiconductor chip and the control semiconductor chip. wire wiring from the substrate mounting surface side or the heat dissipation surface side between each of
and a molding step of covering the power semiconductor chip and the control semiconductor chip with molding resin. 13. The method of manufacturing a power semiconductor module according to claim 11 , wherein in the wire wiring step, wire wiring is simultaneously performed from the substrate mounting surface side and the heat radiation surface side.

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