JP2020004893A - Power semiconductor module, power conversion device, and method of manufacturing power semiconductor module - Google Patents

Abstract

To provide a power semiconductor module capable of actively releasing heat generated from a semiconductor chip while keeping package insulation and also capable of being miniaturized by a non-lead type package, a power conversion device, and a method of manufacturing a power semiconductor module.SOLUTION: A power semiconductor module includes: a lead frame 111 provided with a power die pad 14a and a control die pad 15a connected to external terminal portions 14c, 15c, respectively, provided on a substrate mounting surface 31; a power semiconductor chip 22 mounted on the power die pad 14a; a control semiconductor chip 23 mounted on the control die pad 15, the control semiconductor chip controlling the power semiconductor chip 22; and a mold resin 26 covering the power semiconductor chip 22 and the control semiconductor chip 23. The power die pad 14a is arranged at a position offset in a direction away from the substrate mounting surface 31 via a bent part 14b from the external terminal portion 14c.SELECTED DRAWING: Figure 2

Description

  The present application relates to a power semiconductor module, a power conversion device, and a method for manufacturing a power semiconductor module that include a power semiconductor element and a control semiconductor element that controls the power semiconductor element.

  In order to reduce the cost of the inverter control device, the size of the control circuit board has been reduced. Accordingly, the power semiconductor module mounted on the control circuit board is also required to be reduced in cost and size. For this reason, not only power semiconductor chips for power but also intelligent power modules (hereinafter, referred to as IPMs) in which an IC chip for controlling the semiconductor chips is incorporated in one package have been manufactured. As the IPM, DIP (Dual In-line Package), SIP (Single In-line Package), SOP (Small Outline Package), and the like have been commercialized as package shapes.

  In these packages, the size of the package tends to increase because the leads for connecting to the mounting board protrude outward from the molding resin of the insulator that seals the semiconductor chip and the like. Therefore, non-lead type SON (Small Outline Non-leaded Package) and QFN (Quad Flat Non-lead Package) package shapes have been developed for ICs, memories, LSIs, and the like. In addition, since a semiconductor chip generates a large amount of heat during operation, it is necessary to release the generated heat to the outside of the package.

  For example, as in Patent Document 1, when a lead portion on which a semiconductor chip is mounted is arranged on the mounting surface side and is insulated with a mold resin, the insulation of the package is maintained, but heat is released to the mounting substrate. It becomes difficult to attach cooling fins and the like, and it becomes difficult to actively cool. Therefore, for example, in Patent Literature 2, a lead portion on which a semiconductor chip is mounted is exposed to the outside, and cooling is actively performed by attaching a cooling agent or cooling fin.

JP-A-2002-203936 (paragraphs 0015 to 0020, FIG. 1) JP-A-2006-86273 (paragraphs 0008 to 0009, FIG. 1)

  However, in the structure in which the lead portion on which the semiconductor chip is mounted is exposed as in Patent Document 2, in the case of a power semiconductor chip, the exposed lead portion also has a high voltage because the mounting surface has a high voltage, There was a problem that insulation was not maintained.

  The present application discloses a technique for solving the above-described problem, and can actively release heat of a semiconductor chip while maintaining the insulation of the package, and reduce the size of the package by a non-lead type package. It is an object of the present invention to obtain a power semiconductor module, a power converter, and a method of manufacturing a power semiconductor module, which are capable of performing the above-described steps.

  The power semiconductor module disclosed in the present application is a lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on the substrate mounting surface side, and the first die pad portion A power semiconductor chip mounted on the first die pad, a control semiconductor chip for controlling the power semiconductor chip mounted on the second die pad portion, and a mold resin covering the power semiconductor chip and the control semiconductor chip, The die pad portion is disposed at a position offset from the external terminal portion in a direction away from the substrate mounting surface via a bent portion.

  The method for manufacturing a power semiconductor module disclosed in the present application is provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions via a bent portion, and the first die pad portion and the second die pad A lead frame disposed at a position offset in a direction away from the substrate mounting surface side, and a power semiconductor chip and a control semiconductor chip are mounted on the substrate of the first die pad portion and the second die pad portion of the lead frame. Mounting on the mounting surface side, the first connection pad portion of the lead frame and the surface electrode of the power semiconductor chip, the surface electrode of the power semiconductor chip and the surface electrode of the control semiconductor chip, the surface of the control semiconductor chip A wire is connected between the electrode and each of the second connection pad portions of the lead frame. Characterized in that it comprises a step, a molding step for covering the power semiconductor chip and said control semiconductor chip in a molding resin.

  Further, a first die pad portion and a second die pad portion respectively connected to the plurality of external terminal portions via a bent portion are provided, and the first die pad portion is disposed at a position offset in a direction away from the substrate mounting surface side. Preparing a lead frame provided at a position where the second die pad portion is separated from the substrate mounting surface by an offset amount smaller than the offset amount of the first die pad portion, and connecting a power semiconductor chip or a control semiconductor chip to the lead frame; After being mounted on the substrate mounting surface side of the first die pad portion or the second die pad portion or on the heat dissipation surface side opposite to the substrate mounting surface, the control semiconductor chip or the power semiconductor chip is mounted on the lead frame of the lead frame. Mounted on the heat dissipation surface side or the substrate mounting surface side of the second die pad portion or the first die pad portion The second connection pad portion or the first connection pad portion of the lead frame, the surface electrode of the control semiconductor chip or the power semiconductor chip, the surface electrode of the control semiconductor chip or the power semiconductor chip, the control semiconductor chip, and After wire-wiring between each of the third connection pad portions of the lead frame between the power semiconductor chips from the heat dissipation surface side or the substrate mounting surface side, the first connection pad portion or the third connection pad portion of the lead frame is connected. A second connection pad portion and a surface electrode of the power semiconductor chip or the control semiconductor chip, a third electrode of the lead frame between the surface electrode of the power semiconductor chip or the control semiconductor chip and the power semiconductor chip and the control semiconductor chip; The space between each of the connection pad portions is the board mounting surface side or A step of wire wired from the radiating surface, characterized in that it comprises a molding step for covering the power semiconductor chip and said control semiconductor chip in a molding resin.

  Further, a first die pad portion and a second die pad portion respectively connected to the plurality of external terminal portions via a bent portion are provided, and the first die pad portion is disposed at a position offset in a direction away from the substrate mounting surface side. Preparing a lead frame in which the second die pad portion is disposed on a substrate mounting surface as an external terminal portion, and mounting a power semiconductor chip or a control semiconductor chip on the substrate of the first die pad portion or the second die pad portion of the lead frame; After mounting the control semiconductor chip or the power semiconductor chip on the mounting surface side or the heat radiation surface side opposite to the substrate mounting surface, respectively, the heat radiation of the second die pad portion or the first die pad portion of the lead frame is performed. Mounting on a surface side or the substrate mounting surface side, respectively, and a second connection pad portion of the lead frame. Or the first connection pad portion and a surface electrode of the control semiconductor chip or the power semiconductor chip, and the lead frame between the control semiconductor chip or the surface electrode of the power semiconductor chip and the control semiconductor chip and the power semiconductor chip. After wire-wiring between the respective third connection pad portions from the heat dissipation surface side or the substrate mounting surface side, the first connection pad portion or the second connection pad portion of the lead frame and the power semiconductor chip or the Mounting the substrate between the surface electrode of the control semiconductor chip, the power semiconductor chip or the third connection pad portion of the lead frame between the power semiconductor chip and the control semiconductor chip and the surface electrode of the control semiconductor chip; Wiring a wire from a surface side or the heat radiation surface side; Characterized in that it comprises a molding step for covering the word semiconductor chip and said control semiconductor chip in a molding resin.

  According to the present application, by disposing the die pad portion on which the power semiconductor chip is mounted at a position offset from the external terminal portion in a direction away from the substrate mounting surface via the bent portion, heat generated from the power semiconductor chip is reduced. A power semiconductor module that easily radiates heat from the heat radiating surface opposite to the substrate mounting surface can be obtained.

FIG. 2 is a plan view showing the configuration of the power semiconductor module according to the first embodiment as viewed from the front side. FIG. 2 is a cross-sectional view illustrating a configuration of the power semiconductor module according to the first embodiment. FIG. 2 is a plan view showing the entire lead frame used for the power semiconductor module according to the first embodiment. FIG. 3 is a cross-sectional view showing an offset amount of a control semiconductor chip in the power semiconductor module according to the first embodiment. FIG. 5 is a flowchart showing a method for manufacturing the power semiconductor module according to the first embodiment. FIG. 5 is a sectional view showing another configuration of the power semiconductor module according to the first embodiment. FIG. 5 is a sectional view showing another configuration of the power semiconductor module according to the first embodiment. It is the top view which looked at the structure of the conventional power semiconductor module from the surface side. FIG. 11 is a cross-sectional view illustrating a configuration of a conventional power semiconductor module. It is a top view which shows the whole lead frame used for the conventional power semiconductor module. FIG. 14 is a plan view showing the configuration of a power semiconductor module according to a second embodiment as viewed from the front side. FIG. 13 is a plan view showing the configuration of a power semiconductor module according to a second embodiment as viewed from the back surface side. FIG. 13 is a cross-sectional view illustrating a configuration of a power semiconductor module according to a second embodiment. FIG. 13 is a plan view showing the entire lead frame used for the power semiconductor module according to the second embodiment. FIG. 13 is a cross-sectional view illustrating an offset amount of a control semiconductor chip in the power semiconductor module according to the second embodiment. FIG. 14 is a plan view showing the configuration of a power semiconductor module according to a third embodiment as viewed from the front side. FIG. 14 is a plan view showing the configuration of a power semiconductor module according to a third embodiment as viewed from the back surface side. FIG. 13 is a cross-sectional view illustrating a configuration of a power semiconductor module according to a third embodiment. FIG. 14 is a plan view showing the entire lead frame used for the power semiconductor module according to the third embodiment. FIG. 14 is a cross-sectional view illustrating an offset amount of a control semiconductor chip in a power semiconductor module according to a third embodiment. FIG. 13 is a block diagram illustrating a configuration of a power conversion system to which a power conversion device according to a fourth embodiment is applied.

Embodiment 1 FIG.
FIG. 1 is a plan view showing the configuration of the power semiconductor module 101 according to the first embodiment as viewed from the front side. FIG. 2 is a sectional view taken along the line AA in FIG. FIG. 3 is a plan view showing the entire lead frame 111 used for the power semiconductor module 101, and the region S1 in FIG. 3 corresponds to FIG. In FIG. 1, illustration of the mold resin 26 is omitted.

  As shown in FIGS. 1, 2 and 3, the power semiconductor module 101 includes a power semiconductor chip 22, a control semiconductor chip 23, a power die pad 14a as a first die pad portion of a lead frame 111 on which the power semiconductor chip 22 is mounted, The control die pad 15a as a second die pad portion of the lead frame 111 on which the control semiconductor chip 23 is mounted, the bent portion 14b of the lead frame 111 connected to the power die pad 14a and the external terminal portion 14c, and the lead frame 111 connected to the control die pad 15a The bent portion 15b and the external terminal portion 15c, the wire wiring 38 connecting the surface electrode of the power semiconductor chip 22 and the surface electrode of the control semiconductor chip 23, and the first wire connecting the surface electrode of the power semiconductor chip 22 with the wire wiring 37 The connection pad that is the connection pad The connection pad 11a, which is a second connection pad portion connected to the bent portion 10b of the lead frame 111 connected to the connection pad 10a and the external terminal portion 10c via the wire wiring 39, and the connection. It comprises a bent portion 11b of the lead frame 111 connected to the pad 11a, an external terminal portion 11c, and a mold resin 26.

  The power semiconductor chip 22 and the control semiconductor chip 23 are mounted on the substrate mounting surface 31 side of the power semiconductor module 101 of the power die pad 14a and the control die pad 15a, respectively. The control semiconductor chip 23 is a semiconductor that controls the power semiconductor chip 22 and has functions such as gate driving of the power semiconductor chip 22 and current detection. The power semiconductor chip 22 and the control semiconductor chip 23 are mounted on the power die pad 14a and the control die pad 15a using solders 28 and 29, respectively. In mounting, instead of the solders 28 and 29, a conductive adhesive represented by an Ag paste or a sintered material of Ag or Cu may be used. Further, components such as a capacitor and a resistor may be mounted as needed. Further, the number of control semiconductor chips 23 is not limited to one, and a plurality of control semiconductor chips 23 may be mounted in the power semiconductor module 101.

  The power semiconductor chip 22 employs a power semiconductor element such as an IGBT (Insulated Gate Bipolar Transistor), a Diode, or a power MOS-FET (Metal-Oxide-Semiconductor Field-Effect Transistor). Here, a MOS-FET is used as the power semiconductor chip 22.

  As the control semiconductor chip 23, a control semiconductor chip such as an HVIC (High Voltage IC) and an LVIC (Low-Voltage Integrated Circuit) is adopted. In the embodiment of the present application, the control semiconductor chip 23 includes an HVIC (the upper control semiconductor chip 23 in FIG. 1) for controlling the high-voltage side power semiconductor chip 22 and an LVIC (FIG. 1) for controlling the low voltage side power semiconductor chip 22. 1 lower control semiconductor chip 23) is used.

  The lead frame 111 is made of Cu or Al or an alloy thereof. The surface may be plated with Ni or Ag to prevent oxidation. The wire wirings 37, 38, and 39 are made of a material such as Al, Cu, Au, Ag, or an alloy thereof and have a columnar shape having a diameter of about 10 μm to about 500 μm. The existing bonding such as a ball bond or a wedge bond is used for bonding. A method is used. As the mold resin 26, a material obtained by mixing a material such as silica or alumina with an insulating epoxy-based base material to improve heat conduction is used.

  FIG. 4 is a diagram for explaining the position of the power semiconductor chip 22 in the power semiconductor module 101. As shown in FIG. 4, the power die pad 14a on which the power semiconductor chip 22 is mounted is offset from the external terminal portion 14c of the lead frame 111 in a direction away from the substrate mounting surface 31 via the bent portion 14b. The offset amount can be arbitrarily selected as long as the lead frame 111 is not exposed to the outside when sealed with the mold resin 26 and the power die pad 14a is insulated from the outside. However, in order to improve the cooling performance, it is preferable that the thickness of the mold resin 26 between the power die pad 14a and the heat radiation surface 30 on the outside of the module is thin.

  Further, in FIG. 2, the offset amounts of the power die pad 14a and the control die pad 15a are the same, but there is no problem even if they are different. By offsetting the power die pad 14a and the control die pad 15a from the external terminal portions 14c and 15c, only the external terminal portions 14c and 15c that are to be joined to the mounting substrate during mounting can be exposed. This makes it easy to control the region where the solder spreads during mounting on the board, and can suppress the occurrence of defects during mounting on the board.

  In addition, the wire wirings 37, 38, and 39 are not exposed from the mold resin, and do not contact between the wire wirings 37, 38, and 39 having different potentials, the power semiconductor chip 22, the control semiconductor chip 23, and the like, so that insulation is maintained. Required distance. On the lead frame 111 where the wire wirings 37, 38 and 39 are bonded and where the power semiconductor chip 22 and the control semiconductor chip 23 are mounted, Ag or the like is partially used to improve bonding and mounting properties. It is desirable that the surface be plated.

  Next, a method of manufacturing power semiconductor module 101 according to the first embodiment will be described with reference to FIG. FIG. 5 is a flowchart showing a procedure of manufacturing the power semiconductor module 101 according to the first embodiment.

  First, a lead frame 111 in which the position of the power die pad 14a for mounting the power semiconductor chip 22 is offset with respect to the external terminal portion 14c of the lead frame 111 in a direction away from the substrate mounting surface 31 via the bent portion 14b is prepared. Then, the power semiconductor chip 22 and the control semiconductor chip 23 are mounted on the power die pad 14a and the control die pad 15a of the lead frame 111 using the solders 28 and 29, respectively (mounting step, step S501).

  Subsequently, the power semiconductor chip 22 and the control semiconductor chip 23 are connected to the lead frame 111 using the wire wirings 37, 38, and 39 (wire connection, step S502). At this time, between the power semiconductor chip 22 and the lead frame 111 (connection pad 10a), between the power semiconductor chip 22 and the control semiconductor chip 23, and between the control semiconductor chip 23 and the lead frame 111 (connection pad 11a). If the wire wirings 37, 38, and 39 are of the same type, they can be bonded at the same time. However, the optimum is determined by the current capacity flowing through the power semiconductor chip 22 and the electrode size of the bonding portion of the control semiconductor chip 23. It is desirable to select a proper wire wiring. Also, the order in which these wire wirings 37, 38, 39 are joined can be arbitrarily selected.

  Next, using the mold resin 26, only the external terminal portions 10c, 11c, 14c, and 15c to be mounted on the substrate are exposed, and other members are sealed (molding step, step S503). As a molding method, a transfer mold may be used, but it is preferable to use a compression mold capable of suppressing deformation of wire wiring.

  Subsequently, the portion of the lead frame 111 that is not covered with the mold resin 26 is plated (plating process, step S504). As plating, Sn plating, Sn-Cu plating, or the like is selected in order to cope with soldering at the time of board mounting. If the entire surface of the lead frame has been subjected to plating in advance, or if it is determined that surface treatment is not necessary for soldering at the time of mounting the board, the plating may be omitted.

  Finally, each power semiconductor module 101 is cut by a die press or the like, and singulated to form a SON (Small Outline No Lead Package) type or QFN (Quad For Non-Lead Package) type package. 101 is obtained (cutting step, step S505).

  During operation of the power semiconductor module 101, the power semiconductor chip 22 mainly generates heat. After the power semiconductor module 101 is mounted on the substrate, the heat generated from the power semiconductor chip 22 escapes from the heat radiation surface 30 opposite to the substrate mounting surface 31.

  Therefore, a heat conductive insulating sheet having higher heat conductivity than the mold resin 26 may be additionally provided on the heat radiating surface 30 side of the power die pad 14a of the power semiconductor module 101. FIG. 6 is a cross-sectional view of the power semiconductor module 101 including the heat conductive insulating sheet 40 on the heat dissipation surface 30 side of the power die pad 14a. An example of the heat conductive insulating sheet is an epoxy sheet filled with a filler made of boron nitride, alumina or silica. Thereby, heat generated from the power semiconductor chip 22 is easily radiated locally from the heat radiation surface 30 via the power die pad 14a and the heat conductive insulating sheet 40.

  Further, a metal cooling fin may be connected to the heat radiation surface 30 side of the power semiconductor module 101. FIG. 7 is a cross-sectional view of the power semiconductor module 101 including the cooling fins 41 on the heat radiation surface 30 side of the power semiconductor module 101 via the heat radiation grease 24. The heat radiation grease 24 connecting the cooling fins 41 includes, for example, thermal grease based on silicone. For fixing the cooling fin 41, an existing screw or clip is used. Examples of the cooling fin include a metal such as aluminum. By adding the cooling fins 41, heat can be actively dissipated, and the power semiconductor chip 22 can be driven under more heat-generating conditions.

  The power semiconductor module 101 which is such a SON type or QFN type package does not require leads for insertion terminals as compared with a conventional DIP type package. FIG. 8 is a plan view showing the configuration of a conventional power semiconductor module having a DIP type package as viewed from the front side. FIG. 9 is a sectional view taken along the arrow DD in FIG. FIG. 10 is a plan view showing the entire lead frame 120 used in the conventional power semiconductor module, and the region S0 in FIG. 10 corresponds to FIG. In FIG. 8, illustration of the mold resin 26 is omitted.

  As shown in FIG. 9, the conventional power semiconductor module includes leads 25 for insertion terminals. When FIG. 3 and FIG. 10 are compared, the lead frame 111 and the lead frame 120 have the same vertical width, but the power semiconductor module 101 has a smaller number of power semiconductor modules despite the reduced horizontal width. Many. This indicates that the number of power semiconductor modules per lead frame 111 can be increased. Therefore, the number of power semiconductor modules 101 to be removed per lead frame 111 is improved, so that the time required for molding can be reduced.

  As described above, according to power semiconductor module 101 of the first embodiment, lead frame 111 provided with power die pad 14a and control die pad 15a connected to external terminal portions 14c and 15c provided on substrate mounting surface 31. A power semiconductor chip 22 mounted on the power die pad 14a, a control semiconductor chip 23 for controlling the control semiconductor chip 23 mounted on the control die pad 15a, and a mold resin 26 covering the power semiconductor chip 22 and the control semiconductor chip 23. And the power die pad 14a is disposed at a position offset from the external terminal portion 14c via the bent portion 14b in a direction away from the substrate mounting surface 31, so that the heat generated from the power semiconductor chip It is easy to radiate heat from the heat radiation side opposite to the mounting surface, It is possible to obtain a highly sexual power semiconductor module. Further, as compared with the conventional power semiconductor module, leads for the insertion terminals are not required, so that downsizing can be achieved. In addition, since the number of power semiconductor modules per lead frame is increased, the time required for molding per power semiconductor module can be reduced.

  Further, since the power die pad 14a is provided with the heat conductive insulating sheet 40 between the substrate mounting surface 31 and the heat radiating surface 30 on the opposite side, heat can be locally radiated from the heat radiating surface. Further, since the cooling fins 41 are provided on the heat radiating surface 30 opposite to the substrate mounting surface 31, heat can be positively radiated, and the power semiconductor chip can be driven under a condition that generates more heat. .

Embodiment 2 FIG.
In the first embodiment, a case has been described where the power semiconductor chip 22 and the control semiconductor chip 23 are mounted on the substrate mounting surface 31 side of the power semiconductor module 101 of the power die pad 14a and the control die pad 15a. The case where the control semiconductor chip 23 is mounted on the heat radiation surface 30 of the control die pad 15a opposite to the substrate mounting surface 31 will be described.

  FIG. 11 is a plan view of the configuration of power semiconductor module 102 according to Embodiment 2 as viewed from the front side, and FIG. 12 is a plan view as viewed from the back side. FIG. 13 is a sectional view taken along the arrow BB in FIGS. 11 and 12. FIG. 14 is a plan view showing the entire lead frame 112 used for the power semiconductor module 102, and the region S2 in FIG. 14 corresponds to FIGS. 11 and 12, the illustration of the mold resin 26 is omitted.

  As shown in FIGS. 11, 12, 13, and 14, in the power semiconductor module 102, the control semiconductor chip 23 is mounted on the heat dissipation surface 30 opposite to the substrate mounting surface 31 of the control die pad 15 a, Wire wiring 38 between the control semiconductor chip 23 and the power semiconductor chip 22 is connected via both surfaces of a connection pad 19a which is a third connection pad portion.

  FIG. 15 is a diagram for explaining positions of the power semiconductor chip 22 and the control semiconductor chip 23 in the power semiconductor module 102. As shown in FIG. 15, the control die pad 15a on which the control semiconductor chip 23 is mounted is offset from the external terminal portion 15c of the lead frame 112 in a direction away from the substrate mounting surface 31 via the bent portion 15b. The offset amount is an offset amount L2 smaller than the offset amount L1 of the power die pad 14a on which the power semiconductor chip 22 is mounted, and can be arbitrarily selected as long as the control die pad 15a is insulated from the outside.

  In addition, by offsetting the power die pad 14a and the control die pad 15a from the external terminal portions 14c and 15c, only the external terminal portions 14c and 15c that are to be joined to the mounting substrate during mounting can be exposed. This makes it easy to control the region where the solder spreads during mounting on the board, and can suppress the occurrence of defects during mounting on the board.

  In FIG. 13, the connection pad 19a is also offset similarly to the power die pad 14a, but can be arbitrarily selected as long as it is larger than the offset L2 of the control die pad 15a and equal to or less than the offset L1. However, it is necessary to wire the wiring 38 so that it does not approach the power semiconductor chip 22, the control semiconductor chip 23, and the lead frame of the different potential so as to make contact and dielectric breakdown. Therefore, the contact and the like can be prevented by adjusting the offset amount of the connection pad 19a. Other configurations of the power semiconductor module 102 according to the second embodiment are the same as those of the power semiconductor module 101 according to the first embodiment, and the corresponding parts are denoted by the same reference numerals and description thereof will be omitted.

  Next, a method for manufacturing power semiconductor module 102 according to the second embodiment will be described. The method of manufacturing the power semiconductor module 102 is basically the same as that of the first embodiment, and will be described with reference to FIG. 5 used in the first embodiment.

  First, the power die pad 14a on which the power semiconductor chip 22 is mounted is set at a position away from the external terminal portion 14c of the lead frame 112 by the offset amount L1 from the substrate mounting surface 31 via the bent portion 14b, and The control die pad 15a on which the chip 23 is mounted is located at a position separated from the external terminal portion 15c of the lead frame 112 by an offset amount L2 smaller than the offset amount L1 from the substrate mounting surface 31 via the bent portion 15b. A frame 112 is prepared, and the power semiconductor chip 22 is mounted on the substrate mounting surface 31 side of the power die pad 14a of the lead frame 112 by using solder 28, and thereafter, the front and back of the lead frame 112 are exchanged, and the control semiconductor chip 23 is mounted. Heat radiation surface 3 of control die pad 15a of frame 112 On the side, it is implemented using a solder 29 (mounting step, step S501).

  In the second embodiment, the control semiconductor chip 23 is mounted after mounting the power semiconductor chip 22. However, the power semiconductor chip 22 may be mounted after mounting the control semiconductor chip 23 first. Further, similarly to the first embodiment, a conductive adhesive or the like may be used instead of the solders 28 and 29.

  Subsequently, the control semiconductor chip 23 and the lead frame 112 (connection pad 11a) and the surface electrode of the control semiconductor chip 23 and the connection pad 19a are connected using the wire wirings 38 and 39, and then the lead frame is connected. The front and rear surfaces of the power semiconductor chip 112 are reversed, and the connection between the power semiconductor chip 22 and the lead frame 112 (connection pad 10a) and the connection between the surface electrode of the power semiconductor chip 22 and the connection pad 19a (wire connection, step S502).

  At this time, after the wire connection on the control semiconductor chip 23 side, since the wire wiring 38 is already bonded to the heat radiation surface 30 side of the connection pad 19a, the wire wiring 38 is bonded to the substrate mounting surface 31 side of the connection pad 19a. In this case, it is necessary to prevent the jig for fixing the lead frame 112 and the stage on which the lead frame 112 is arranged from interfering with the wire wiring 38 on the control semiconductor chip 23 side.

  Note that the wire wiring 38 may be bonded to the same place on both sides of the connection pad 19a, or the bonding position of the wire wiring 38 may be changed between the board mounting surface 31 side and the heat radiation surface 30 side of the connection pad 19a. There is no problem if the wires 38 can be joined without breaking. Further, in the second embodiment, the wiring of the control semiconductor chip 23 is performed first, and then the wiring of the power semiconductor chip 22 is performed. The wiring on the 22 side may be provided. Further, the wiring on the control semiconductor chip 23 and the wiring on the power semiconductor chip 22 may be simultaneously performed from both sides. As described above, by simultaneously performing the wire wiring from both sides, the time required for the wire wiring can be reduced.

  The power semiconductor module 102 is obtained as a SON type or QFN type package by performing the same operations as those of the first embodiment in steps S503 to S505.

  As described above, since the offset amount L1 of the control die pad 15a is different from the offset amount L2 of the power die pad 14a, the power semiconductor chip 22 serving as a heat source is separated from the control semiconductor chip 23, and the control semiconductor chip 23 is erroneously heated. The increase in operation and leakage current can be reduced. Further, the thickness of the power semiconductor module can be reduced by the area V in the conventional power semiconductor module of FIG. As a result, the amount of use of the mold resin 26 is reduced accordingly, and cost reduction can be realized. When FIG. 14 and FIG. 10 are compared, the vertical widths of the lead frame 112 and the lead frame 120 are the same, but the power semiconductor module is similar to the first embodiment although the horizontal width is reduced. Since the number of power semiconductor modules 102 is larger, the number of power semiconductor modules 102 that can be removed per lead frame 112 is improved, thereby shortening the time required for molding each power semiconductor module. It becomes possible.

  As described above, according to power semiconductor module 102 in the second embodiment, control die pad 15a is disposed at a position offset from external terminal portion 15c in a direction away from substrate mounting surface 31 via bent portion 15b. Since the offset amount of the control die pad 15a is made smaller than the offset amount of the power die pad 14a, not only the effect of the first embodiment, but also the power semiconductor chip serving as a heat source is separated from the control semiconductor chip. As a result, it is possible to reduce the malfunction of the control semiconductor chip and the increase in the leakage current, and to obtain a highly reliable power semiconductor module. Further, as compared with the power semiconductor module shown in FIG. 9, the molding resin can be reduced by the amount corresponding to the V region, so that the amount of the molding resin used is reduced correspondingly and cost reduction can be realized. Further, the wiring on the control semiconductor chip 23 and the wiring on the power semiconductor chip 22 may be simultaneously performed from both sides. As described above, by simultaneously performing the wire wiring from both sides, the time required for the wire wiring can be reduced.

Embodiment 3 FIG.
In the first and second embodiments, the control die pad 15a on which the control semiconductor chip 23 is mounted is moved away from the board mounting surface 31 via the bent portion 15b with respect to the external terminal portions 15c of the lead frames 111 and 112. In the third embodiment, the case where the offset is not performed will be described.

  FIG. 16 is a plan view of the configuration of power semiconductor module 103 according to the third embodiment as viewed from the front side, and FIG. 17 is a plan view of the configuration as viewed from the back side. FIG. 18 is a sectional view taken along the arrow CC in FIGS. 16 and 17. FIG. 19 is a plan view showing the entire lead frame 113 used for the power semiconductor module 103, and the region S3 in FIG. 19 corresponds to FIGS. 16 and 17. 16 and 17, illustration of the mold resin 26 is omitted.

  As shown in FIGS. 16, 17, 18, and 19, in the power semiconductor module 103, similarly to the second embodiment, the control semiconductor chip 23 has a heat radiating surface opposite to the substrate mounting surface 31 of the control die pad 15a. It is mounted on the 30 side, and a wire wiring 38 between the control semiconductor chip 23 and the power semiconductor chip 22 is connected via both surfaces of the connection pad 19a.

  FIG. 20 is a diagram for explaining positions of the power semiconductor chip 22 and the control semiconductor chip 23 in the power semiconductor module 103. As shown in FIG. 18, unlike the first and second embodiments, the control die pad 15a on which the control semiconductor chip 23 is mounted is not offset, and the control die pad 15a itself is bonded to the mounting board during mounting. Some of the external terminal portions are exposed on the substrate mounting surface. Other configurations of the power semiconductor module 103 according to the third embodiment are the same as those of the power semiconductor module 101 according to the first embodiment, and corresponding parts are denoted by the same reference numerals and description thereof is omitted.

  Next, a method for manufacturing power semiconductor module 103 according to the third embodiment will be described. The method for manufacturing the power semiconductor module 103 is basically the same as in the first embodiment, and will be described with reference to FIG. 5 used in the first embodiment.

  First, the power die pad 14a on which the power semiconductor chip 22 is mounted is set at a position separated from the external terminal portion 14c of the lead frame 113 by an offset amount L1 from the substrate mounting surface 31 via the bent portion 14b, and The control die pad 15a on which the chip 23 is mounted is prepared without offset, as the external terminal portion of the lead frame 113, the lead frame 113 set at a position where a part is exposed on the substrate mounting surface 31, and the power semiconductor chip 22 is mounted. The power die pad 14a of the lead frame 113 is mounted on the substrate mounting surface 31 side of the power die pad 14a using the solder 28, and then the lead frame 113 is turned over, and the power semiconductor chip 22 is replaced with the substrate mounting surface 31 of the power die pad 14a of the lead frame 113. On the side, mounted using solder 28, control semiconductor The radiating surface 30 side of the control die pad 15a of the lead frame 113 and tip 23 is mounted using a solder 29 (mounting step, step S501).

  The power semiconductor module 102 is obtained as a SON type or QFN type package by performing the same operation as in the second embodiment for the processes from step S502 to step S505.

  As described above, the power semiconductor chip 22 serving as a heat source is separated from the control semiconductor chip 23 by the offset amount L1, so that malfunction of the control semiconductor chip 23 due to heat and an increase in leak current can be reduced. Further, as in the second embodiment, the thickness of the power semiconductor module can be reduced by the region V in the conventional power semiconductor module of FIG. As a result, the amount of use of the mold resin 26 is reduced accordingly, and cost reduction can be realized. Further, as can be seen by comparing FIG. 19 with FIGS. 3 and 14, since the offset of the control die pad 15a is eliminated, the external terminal portions 14c and 15c, the bent portions 14b and 15b, and the routing portion are not required. Only the width is reduced, so that the module size can be reduced, the number of power semiconductor modules per lead frame 113 can be increased, and the time required for molding can be reduced.

  As described above, according to the power semiconductor module 103 in the third embodiment, the control die pad 15a is provided as an external terminal portion so as to be exposed on the substrate mounting surface 31 without any offset. In addition to the effects of the above, the power semiconductor chip serving as a heat source is separated from the control semiconductor chip as much as possible, and the malfunction of the control semiconductor chip due to heat and the increase in leak current can be further reduced, and the reliability is further improved. A power semiconductor module can be obtained. Further, as compared with the power semiconductor module shown in FIG. 9, the molding resin can be reduced by the amount corresponding to the V region, so that the amount of the molding resin used is reduced correspondingly and cost reduction can be realized. In addition, since the offset of the control die pad is eliminated, the external terminal portion, the bent portion and the routing portion are not required, and the width is reduced accordingly, so that the module size can be reduced, and the power per lead frame 113 can be further reduced. The number of semiconductor modules can be increased, and the time required for molding can be reduced. Further, the wiring on the control semiconductor chip 23 and the wiring on the power semiconductor chip 22 may be simultaneously performed from both sides. As described above, by simultaneously performing the wire wiring from both sides, the time required for the wire wiring can be reduced.

Embodiment 4 FIG.
In the fourth embodiment, the power semiconductor module according to the first to third embodiments is applied to a power converter. Although the present application is not limited to a specific power conversion device, a case where the present application is applied to a three-phase inverter will be described below as a fourth embodiment.

  FIG. 21 is a block diagram illustrating a configuration of a power conversion system to which the power conversion device according to the fourth embodiment is applied.

  The power conversion system illustrated in FIG. 21 includes a power supply 100, a power conversion device 200, and a load 300. Power supply 100 is a DC power supply, and supplies DC power to power conversion device 200. The power supply 100 can be composed of various things, for example, it can be composed of a DC system, a solar cell, a storage battery, or can be composed of a rectifier circuit or an AC / DC converter connected to an AC system. Is also good. Further, the power supply 100 may be configured by a DC / DC converter that converts DC power output from a DC system into predetermined power.

  Power conversion device 200 is a three-phase inverter connected between power supply 100 and load 300, converts DC power supplied from power supply 100 into AC power, and supplies AC power to load 300. As shown in FIG. 21, power conversion device 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs the same, and a control circuit 203 that outputs a control signal for controlling main conversion circuit 201 to main conversion circuit 201. And

  Load 300 is a three-phase electric motor driven by AC power supplied from power conversion device 200. The load 300 is not limited to a specific application, but is a motor mounted on various electric devices, and is used as, for example, a hybrid vehicle or an electric vehicle, a railway vehicle, an elevator, or a motor for an air conditioner.

  Hereinafter, the details of the power conversion device 200 will be described. The main conversion circuit 201 includes a switching element and a free wheel diode (not shown). The switching element switches to convert DC power supplied from the power supply 100 into AC power and supply the AC power to the load 300. Although there are various specific circuit configurations of the main conversion circuit 201, the main conversion circuit 201 according to the fourth embodiment is a two-level three-phase full bridge circuit, and includes six switching elements and each switching element. It can be composed of six freewheeling diodes that are antiparallel. Each switching element and each return diode of the main conversion circuit 201 are configured by a power semiconductor module (here, the power semiconductor module 101 will be described) corresponding to any of the above-described first to third embodiments. The six switching elements are connected in series for every two switching elements to form upper and lower arms, and each upper and lower arm forms each phase (U phase, V phase, W phase) of the full bridge circuit. The output terminals of the upper and lower arms, that is, the three output terminals of the main conversion circuit 201 are connected to the load 300.

  Although the main conversion circuit 201 includes a drive circuit (not shown) for driving each switching element, the drive circuit may be built in the power semiconductor module 101 or may be driven separately from the power semiconductor module 101. A configuration including a circuit may be employed. The drive circuit generates a drive signal for driving the switching element of the main conversion circuit 201 and supplies the drive signal to the control electrode of the switching element of the main conversion circuit 201. Specifically, in accordance with a control signal from a control circuit 203 to be described later, a drive signal for turning on the switching element and a drive signal for turning off the switching element are output to the control electrode of each switching element. When the switching element is maintained in the ON state, the drive signal is a voltage signal (ON signal) higher than the threshold voltage of the switching element. When the switching element is maintained in the OFF state, the drive signal is lower than the threshold voltage of the switching element. Signal (off signal).

  The control circuit 203 controls the switching elements of the main conversion circuit 201 so that desired power is supplied to the load 300. Specifically, based on the power to be supplied to the load 300, a time (on-time) during which each switching element of the main conversion circuit 201 should be in an on-state is calculated. For example, the main conversion circuit 201 can be controlled by PWM control that modulates the ON time of the switching element according to the voltage to be output. Then, a control command (control signal) is issued to the drive circuit provided in the main conversion circuit 201 so that an ON signal is output to the switching element that is to be turned on at each time point and an OFF signal is output to the switching element that is to be turned off at each time. Is output. The drive circuit outputs an ON signal or an OFF signal as a drive signal to a control electrode of each switching element according to the control signal.

  In the power converter according to the fourth embodiment, since the semiconductor devices according to the first to third embodiments are applied as the switching element and the return diode of the main conversion circuit 201, the reliability can be improved.

  In the fourth embodiment, an example in which the present invention is applied to a two-level three-phase inverter has been described. However, the present invention is not limited to this, and can be applied to various power converters. In the fourth embodiment, a two-level power converter is used. However, a three-level or multi-level power converter may be used. When supplying power to a single-phase load, the present invention is applied to a single-phase inverter. It does not matter. In addition, when power is supplied to a DC load or the like, the present invention can be applied to a DC / DC converter or an AC / DC converter.

  The power converter to which the present invention is applied is not limited to the case where the above-described load is an electric motor. For example, a power supply device of an electric discharge machine or a laser machine, or an induction heating cooker or a non-contact power supply system It can also be used as a power conditioner for a solar power generation system or a power storage system.

  Although this application describes various exemplary embodiments and examples, the various features, aspects, and functions described in one or more embodiments may apply to particular embodiments. However, the present invention is not limited to this, and can be applied to the embodiment alone or in various combinations. Accordingly, innumerable modifications not illustrated are contemplated within the scope of the technology disclosed herein. For example, a case where at least one component is deformed, added or omitted, and a case where at least one component is extracted and combined with a component of another embodiment are included.

  14a power die pad, 14b bent portion, 14c external terminal portion, 15a control die pad, 15b bent portion, 15c external terminal portion, 22 power semiconductor chip, 23 control semiconductor chip, 26 mold resin, 30 heat radiation surface, 31 substrate mounting surface, 101 Power semiconductor module, L1 offset amount.

Claims (13)

A lead frame provided with a first die pad portion and a second die pad portion respectively connected to a plurality of external terminal portions provided on the substrate mounting surface side,
A power semiconductor chip mounted on the first die pad portion,
A control semiconductor chip for controlling the power semiconductor chip mounted on the second die pad portion,
And a mold resin covering the power semiconductor chip and the control semiconductor chip,
The power semiconductor module according to claim 1, wherein the first die pad portion is disposed at a position offset from the external terminal portion in a direction away from the substrate mounting surface via a bent portion.   The second die pad portion is disposed at a position offset from the external terminal portion in a direction away from the substrate mounting surface via the bent portion, and the offset amount of the second die pad portion is equal to or smaller than the first die pad portion. The power semiconductor module according to claim 1, wherein the power semiconductor module is smaller than the offset amount.   The power semiconductor module according to claim 1, wherein the second die pad portion is provided on the substrate mounting surface as the external terminal portion.   The power semiconductor chip is mounted on a substrate mounting surface side of the first die pad portion, and the control semiconductor chip is mounted on a heat radiation surface side of the second die pad portion opposite to the substrate mounting surface. The power semiconductor module according to claim 2 or 3, wherein A first connection pad portion of the lead frame connected to the surface electrode of the power semiconductor chip via a wire,
The power semiconductor according to any one of claims 1 to 4, further comprising a second connection pad portion of the lead frame connected to a surface electrode of the control semiconductor chip via a wire. module.   A third connection pad portion of the lead frame between the power semiconductor chip and the control semiconductor chip; and a surface electrode of the power semiconductor chip and a surface electrode of the control semiconductor chip and the third connection pad portion, respectively. The power semiconductor module according to claim 4, wherein the power semiconductor module is connected via a wire.   The power supply according to any one of claims 1 to 6, wherein the first die pad portion is provided with a heat conductive insulating sheet between the substrate mounting surface and an opposite heat radiation surface. Semiconductor module.   The power semiconductor module according to any one of claims 1 to 7, wherein a cooling fin is provided on a heat radiation surface opposite to the substrate mounting surface. A main conversion circuit having the power semiconductor module according to any one of claims 1 to 8 for converting input power and outputting the power,
A control circuit for outputting a control signal for controlling the main conversion circuit to the main conversion circuit. A first die pad portion and a second die pad portion respectively connected to the plurality of external terminal portions via a bent portion are provided, and the first die pad portion and the second die pad portion are respectively offset in a direction away from the substrate mounting surface side. Prepare a lead frame disposed at the position, the step of mounting a power semiconductor chip and a control semiconductor chip on the substrate mounting surface side of the first die pad portion and the second die pad portion of the lead frame, respectively,
A first connection pad portion of the lead frame and a surface electrode of the power semiconductor chip; a surface electrode of the power semiconductor chip and a surface electrode of the control semiconductor chip; a surface electrode of the control semiconductor chip and a second connection pad of the lead frame; Wiring between each of the sections;
And a molding step of covering the power semiconductor chip and the control semiconductor chip with a molding resin. A first die pad portion and a second die pad portion respectively connected to the plurality of external terminal portions via a bent portion are provided, and the first die pad portion is disposed at a position offset in a direction away from the substrate mounting surface side, Prepare a lead frame disposed at a position where the second die pad portion is separated from the substrate mounting surface side by an offset amount smaller than the offset amount of the first die pad portion, and connect a power semiconductor chip or a control semiconductor chip to the lead frame. After mounting on the substrate mounting surface side of the first die pad portion or the second die pad portion or on the heat radiation surface side opposite to the substrate mounting surface, the control semiconductor chip or the power semiconductor chip is mounted on the second side of the lead frame. A step of mounting the die pad portion or the first die pad portion on the heat dissipation surface side or the substrate mounting surface side;
A second connection pad portion or a first connection pad portion of the lead frame, a surface electrode of the control semiconductor chip or the power semiconductor chip, a surface electrode of the control semiconductor chip or the power semiconductor chip, the control semiconductor chip, and the power semiconductor After wire-wiring between the third connection pad portions of the lead frame between the chips from the heat dissipation surface side or the substrate mounting surface side, the first connection pad portion or the second connection pad of the lead frame Part and a surface electrode of the power semiconductor chip or the control semiconductor chip, a third connection pad part of the lead frame between the surface electrode of the power semiconductor chip or the control semiconductor chip and the power semiconductor chip and the control semiconductor chip Between the substrate mounting surface side and the A step of wire wiring from the side,
And a molding step of covering the power semiconductor chip and the control semiconductor chip with a molding resin. A first die pad portion and a second die pad portion respectively connected to the plurality of external terminal portions via a bent portion are provided, and the first die pad portion is disposed at a position offset in a direction away from the substrate mounting surface side, A lead frame having a second die pad portion provided on a substrate mounting surface as an external terminal portion is prepared, and a power semiconductor chip or a control semiconductor chip is mounted on the substrate mounting surface of the first die pad portion or the second die pad portion of the lead frame. After mounting the control semiconductor chip or the power semiconductor chip on the second die pad portion or the first die pad portion of the lead frame, Or mounting each on the substrate mounting surface side,
A second connection pad portion or a first connection pad portion of the lead frame, a surface electrode of the control semiconductor chip or the power semiconductor chip, a surface electrode of the control semiconductor chip or the power semiconductor chip, the control semiconductor chip, and the power semiconductor After wire-wiring between the third connection pad portions of the lead frame between the chips from the heat dissipation surface side or the substrate mounting surface side, the first connection pad portion or the second connection pad of the lead frame Part and a surface electrode of the power semiconductor chip or the control semiconductor chip, a third connection pad part of the lead frame between the surface electrode of the power semiconductor chip or the control semiconductor chip and the power semiconductor chip and the control semiconductor chip Between the substrate mounting surface side and the A step of wire wiring from the side,
And a molding step of covering the power semiconductor chip and the control semiconductor chip with a molding resin.   The method of manufacturing a power semiconductor module according to claim 11, wherein, in the step of wiring, wire wiring is performed simultaneously from the substrate mounting surface side and the heat radiation surface side.

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