JPWO2017191799A1 - 半導体集積回路装置 - Google Patents
半導体集積回路装置 Download PDFInfo
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- JPWO2017191799A1 JPWO2017191799A1 JP2018515711A JP2018515711A JPWO2017191799A1 JP WO2017191799 A1 JPWO2017191799 A1 JP WO2017191799A1 JP 2018515711 A JP2018515711 A JP 2018515711A JP 2018515711 A JP2018515711 A JP 2018515711A JP WO2017191799 A1 JPWO2017191799 A1 JP WO2017191799A1
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Abstract
Description
図1は第1実施形態に係る半導体集積回路装置のレイアウト構成例を示す平面図である。図1に示すスタンダードセル1,2はそれぞれ、ナノワイヤFETを用いて、入力Aおよび出力Yを有するインバータを構成する。図1では、図面横方向をX方向(第1方向に相当)とし、図面縦方向をY方向(第2方向に相当)としている。以降のレイアウト平面図についても同様である。図1では、スタンダードセル1,2は、X方向に延びる同じセル列に配置されている。
図3は本実施形態に係る半導体集積回路装置のレイアウト構成の他の例を示す平面図である。図3のレイアウト構成は、基本的には図1と同様であり、共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。図3では、スタンダードセル2Aのレイアウトが、図1のスタンダードセル2と少し異なっている。
図4は本実施形態に係る半導体集積回路装置のレイアウト構成の他の例を示す平面図である。図4のレイアウト構成は、基本的には図1と同様であり、共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。図4では、スタンダードセル2Bのレイアウトが、図1のスタンダートセル2と少し異なっている。
図5は本実施形態に係る半導体集積回路装置のレイアウト構成の他の例を示す平面図である。図5のレイアウト構成は、基本的には図1と同様であり、共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。図5では、スタンダードセル2Cのレイアウトが、図1のスタンダードセル2と少し異なっている。
図6は第2実施形態に係る半導体集積回路装置のレイアウト構成例を示す平面図である。図6に示すスタンダードセル1,3はそれぞれ、ナノワイヤFETを用いて、入力Aおよび出力Yを有するインバータを構成する。また、図6では、スタンダードセル1,3は、X方向に延びる同じセル列に配置されている。図6のレイアウト構成では、図1と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。なお、スタンダードセル1のレイアウト構成は、第1実施形態で示したものと同様である。
図7は第3実施形態に係る半導体集積回路装置のレイアウト構成の他の例を示す平面図である。図7に示すスタンダードセル1,4はそれぞれ、ナノワイヤFETを用いて、入力Aおよび出力Yを有するインバータを構成する。また、図7では、スタンダードセル1,4は、X方向に延びる同じセル列に配置されている。図7のレイアウト構成では、図1と共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。なお、スタンダードセル1のレイアウト構成は、第1実施形態で示したものと同様である。
図8(a),(b)は本実施形態におけるスタンダードセル4の他の例である。図8(a)のスタンダードセル4Aでは、回路の論理動作に寄与しないダミートランジスタであるナノワイヤFET P42,N42は、両方のパッドがダミーパッドになっている。
上述の各実施形態では、Y方向においてパッド端が一致する2個のナノワイヤFETは、それぞれ別のスタンダードセルに含まれているものとして説明したが、単一のスタンダードセルに、Y方向においてパッド端が一致する2個のナノワイヤFETが含まれている構成であってもよい。
図10は第5実施形態に係る半導体集積回路装置のレイアウト構成例を示す平面図である。図10では、スタンダードセル101,102は、X方向に延びる同じセル列に配置されており、X方向において隣接して配置されている。
図12は本実施形態に係る半導体集積回路装置のレイアウト構成の他の例を示す平面図である。図12のレイアウト構成は、基本的には図1と同様であり、共通の構成要素には同一の符号を付しており、ここではその詳細な説明を省略する場合がある。図12では、スタンダードセル102Aのレイアウトが、図10のスタンダードセル102と少し異なっている。すなわち、スタンダードセル102Aにおいて、パッド242のY方向における配置範囲が大きくなっており、Y方向に4個に分離して形成されている。そして、パッド241,242,243は、Y方向における配置範囲および位置が同一である(破線a3,a4)。
2,2A,2B,2C,3,4,4A,4B 第2スタンダードセル
5 スタンダードセル
11,12,13,14 ナノワイヤ
21,22,23,24,25,26,27,28 パッド
25a,26a,27a,28a パッド
25b,26b,27b,28b ダミーパッド
31n,32n,31p,32p ゲート電極
35a,35b,36a,36b,37a,37b ダミーゲート電極
51,52,53,54 ナノワイヤ
61,62,63,64,65,66,67,68 パッド
71n,72n,71p,72p ゲート電極
131,133,141,143 ナノワイヤ
132,134,142,144 ダミーナノワイヤ
N1,N2,N31,N41,N51,N52 ナノワイヤFET
N32,N42 ダミートランジスタであるナノワイヤFET
P1,P2,P31,P41,P51,P52 ナノワイヤFET
P32,P42 ダミートランジスタであるナノワイヤFET
101 スタンダードセル
102 スタンダードセル
11A,11B,12A,12B,13A,13B,14A,14B ナノワイヤ
211,212,213,221,222,223,231,232,233,241,242,243 パッド
311p,312p,311n,312n,321p,322p,321n,322n ゲート電極
P1A,P1B,N1A,N1B,P2A,P2B,N2A,N2B ナノワイヤFET
Claims (21)
- 第1ナノワイヤFET(Field Effect Transistor)を備えた第1スタンダードセルと、
第2ナノワイヤFETを備えた第2スタンダードセルとを備え、
前記第1ナノワイヤFETは、
第1方向に延びるNa(Naは2以上の整数)本の第1ナノワイヤと、
前記第1ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記第1ナノワイヤの下面よりも低い位置にあり、前記第1ナノワイヤと接続された一対の第1パッドと、
前記第1方向と垂直をなす第2方向に延び、前記第1ナノワイヤの前記第1方向における所定範囲において、前記第1ナノワイヤの周囲を囲うように設けられた第1ゲート電極とを備えており、
前記第2ナノワイヤFETは、
前記第1方向に延びるNb(Nbは1以上でNaより小さい整数)本の第2ナノワイヤと、
前記第2ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記第2ナノワイヤの下面よりも低い位置にあり、前記第2ナノワイヤと接続された一対の第2パッドと、
前記第2方向に延び、前記第2ナノワイヤの前記第1方向における所定範囲において、前記第2ナノワイヤの周囲を囲うように設けられた第2ゲート電極とを備えており、
前記第1ナノワイヤFETの前記第1パッドと前記第2ナノワイヤFETの前記第2パッドとは、前記第2方向において、両端のうち少なくともいずれか一方の位置が、一致している
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第1ナノワイヤFETの前記第1パッドと前記第2ナノワイヤFETの前記第2パッドとは、前記第2方向において、両端の位置が一致している
ことを特徴とする半導体集積回路装置。 - 請求項2記載の半導体集積回路装置において、
前記第2ナノワイヤFETは、前記第2方向において、前記第2ナノワイヤの配置範囲の中心位置と、前記第2パッドの配置範囲の中心位置とが一致している
ことを特徴とする半導体集積回路装置。 - 請求項2記載の半導体集積回路装置において、
前記第2ナノワイヤFETは、前記第2方向において、前記第2ナノワイヤの配置範囲が、前記第2パッドの配置範囲に対して偏っている
ことを特徴とする半導体集積回路装置。 - 請求項1〜4のうちいずれか1項記載の半導体集積回路装置において、
前記第2ナノワイヤFETは、
前記第2パッド間において、前記第2ゲート電極と同一直線上に、当該第2ゲート電極と分離して配置されたダミーゲート電極を備えている
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第2スタンダードセルは、回路の論理動作に寄与しないダミートランジスタである、第3ナノワイヤFETを備え、
前記第3ナノワイヤFETは、
前記第2ナノワイヤFETの前記第2パッド間に設けられ、前記第1方向に延びるダミーナノワイヤと、
前記第2ナノワイヤFETの前記第2ゲート電極と同一直線上に、当該第2ゲート電極と分離して配置され、前記ダミーナノワイヤの前記第1方向における所定範囲において前記ダミーナノワイヤの周囲を囲うように設けられたダミーゲート電極とを備えた
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第2スタンダードセルは、回路の論理動作に寄与しないダミートランジスタである、第3ナノワイヤFETを備え、
前記第3ナノワイヤFETは、
前記第2ナノワイヤFETの前記第2ナノワイヤと並列に、前記第1方向に延びるように設けられたダミーナノワイヤと、
前記ダミーナノワイヤの前記第1方向における両端の少なくともいずれか一方に設けられ、下面が前記ダミーナノワイヤの下面よりも低い位置にあり、前記ダミーナノワイヤと接続されたダミーパッドとを備え、
前記ダミーパッドは、前記第2ナノワイヤFETの前記第2パッドと前記第2方向に並び、当該第2パッドと分離して、配置されている
ことを特徴とする半導体集積回路装置。 - 請求項7記載の半導体集積回路装置において、
前記第3ナノワイヤFETは、
第2ナノワイヤFETの前記第2ゲート電極と同一直線上に、当該第2ゲート電極と分離して配置され、前記ダミーナノワイヤの前記第1方向における所定範囲において前記ダミーナノワイヤの周囲を囲うように設けられたダミーゲート電極を備えた
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第2ゲート電極は、前記第1ゲート電極よりも短い
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第2スタンダードセルは、第3ナノワイヤFETを備え、
前記第3ナノワイヤFETは、
前記第1方向に延びるNa本の第3ナノワイヤと、
前記第3ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記第3ナノワイヤの下面よりも低い位置にあり、前記第3ナノワイヤと接続された一対の第3パッドと、
前記第2方向に延び、前記第3ナノワイヤの前記第1方向における所定範囲において、前記第3ナノワイヤの周囲を囲うように設けられた第3ゲート電極とを備えており、
前記第2スタンダードセルは、前記第2ナノワイヤFETの前記第2パッドの一方であり、かつ、前記第3ナノワイヤFETの前記第3パッドの一方である共有パッドを備え、
前記第1パッドの両方、前記第2パッドの他方、前記共有パッド、および、前記第3パッドの他方は、前記第2方向における位置および配置範囲が同一である
ことを特徴とする半導体集積回路装置。 - 請求項1記載の半導体集積回路装置において、
前記第2スタンダードセルは、第3ナノワイヤFETを備え、
前記第3ナノワイヤFETは、
前記第1方向に延びるNc(Ncは1以上でNaより小さい整数)本の第3ナノワイヤと、
前記第3ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記第3ナノワイヤの下面よりも低い位置にあり、前記第3ナノワイヤと接続された一対の第3パッドと、
前記第2方向に延び、前記第3ナノワイヤの前記第1方向における所定範囲において、前記第3ナノワイヤの周囲を囲うように設けられた第3ゲート電極とを備えており、
前記第2スタンダードセルは、前記第2ナノワイヤFETの前記第2パッドの一方であり、かつ、前記第3ナノワイヤFETの前記第3パッドの一方である共有パッドを備え、
前記第1パッドの両方、前記第2パッドの他方、前記共有パッド、および、前記第3パッドの他方は、前記第2方向における位置および配置範囲が同一である
ことを特徴とする半導体集積回路装置。 - 請求項1〜11のうちいずれか1項記載の半導体集積回路装置において、
前記第1および第2スタンダードセルは、前記第1方向に延びる同じセル列に、配置されている
ことを特徴とする半導体集積回路装置。 - 請求項12記載の半導体集積回路装置において、
前記第1および第2スタンダードセルは、隣接して配置されている
ことを特徴とする半導体集積回路装置。 - 第1ナノワイヤFET(Field Effect Transistor)と、回路の論理動作に寄与しないダミートランジスタである、第2ナノワイヤFETとを備えたスタンダードセルを備え、
前記第1ナノワイヤFETは、
第1方向に延びるナノワイヤと、
前記ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記ナノワイヤの下面よりも低い位置にあり、前記ナノワイヤと接続された一対のパッドと、
前記第1方向と垂直をなす第2方向に延び、前記ナノワイヤの前記第1方向における所定範囲において前記ナノワイヤの周囲を囲うように設けられたゲート電極とを備えており、
前記第2ナノワイヤFETは、
前記第1ナノワイヤFETのパッド間に設けられ、前記第1方向に延びるダミーナノワイヤと、
前記第1ナノワイヤFETのゲート電極と同一直線上に、前記ゲート電極と分離して配置され、前記ダミーナノワイヤの前記第1方向における所定範囲において前記ダミーナノワイヤの周囲を囲うように設けられたダミーゲート電極とを備えている
ことを特徴とする半導体集積回路装置。 - 第1ナノワイヤFET(Field Effect Transistor)と、回路の論理動作に寄与しないダミートランジスタである、第2ナノワイヤFETとを備えたスタンダードセルを備え、
前記第1ナノワイヤFETは、
第1方向に延びるナノワイヤと、
前記ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記ナノワイヤの下面よりも低い位置にあり、前記ナノワイヤと接続された一対のパッドと、
前記第1方向と垂直をなす第2方向に延び、前記ナノワイヤの前記第1方向における所定範囲において前記ナノワイヤの周囲を囲うように設けられたゲート電極とを備えており、
前記第2ナノワイヤFETは、
前記第1ナノワイヤFETのナノワイヤと並列に、前記第1方向に延びるように設けられたダミーナノワイヤと、
前記ダミーナノワイヤの前記第1方向における両端の少なくともいずれか一方に設けられ、下面が前記ダミーナノワイヤの下面よりも低い位置にあり、前記ダミーナノワイヤと接続されたダミーパッドとを備えており、
前記ダミーパッドは、前記第1ナノワイヤFETのパッドと前記第2方向に並び、当該パッドと分離して、配置されている
ことを特徴とする半導体集積回路装置。 - 請求項15記載の半導体集積回路装置において、
前記第2ナノワイヤFETは、
前記第1ナノワイヤFETのゲート電極と同一直線上に、当該ゲート電極と分離して配置され、前記ダミーナノワイヤの前記第1方向における所定範囲において前記ダミーナノワイヤの周囲を囲うように設けられたダミーゲート電極とを備えた、
ことを特徴とする半導体集積回路装置。 - 第1ナノワイヤFET(Field Effect Transistor)と、第2ナノワイヤFETとを備えたスタンダードセルを備え、
前記第1ナノワイヤFETは、
第1方向に延びるNa(Naは2以上の整数)本の第1ナノワイヤと、
前記第1ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記第1ナノワイヤの下面よりも低い位置にあり、前記第1ナノワイヤと接続された一対の第1パッドと、
前記第1方向と垂直をなす第2方向に延び、前記第1ナノワイヤの前記第1方向における所定範囲において、前記第1ナノワイヤの周囲を囲うように設けられた第1ゲート電極とを備えており、
前記第2ナノワイヤFETは、
第1方向に延びるNb(Nbは1以上でNaより小さい整数)本の第2ナノワイヤと、
前記第2ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記第2ナノワイヤの下面よりも低い位置にあり、前記第2ナノワイヤと接続された一対の第2パッドと、
前記第2方向に延び、前記第2ナノワイヤの前記第1方向における所定範囲において、前記第2ナノワイヤの周囲を囲うように設けられた第2ゲート電極とを備えており、
前記第1ナノワイヤFETの前記第1パッドと前記第2ナノワイヤFETの前記第2パッドとは、前記第2方向において、両端のうち少なくともいずれか一方の位置が、一致している
ことを特徴とする半導体集積回路装置。 - 請求項17記載の半導体集積回路装置において、
前記スタンダードセルは、前記第1ナノワイヤFETの前記第1パッドの一方であり、かつ、前記第2ナノワイヤFETの前記第2パッドの一方である共有パッドを備え、
前記第1パッドの他方、前記共有パッド、および、前記第2パッドの他方は、前記第2方向における位置および配置範囲が同一である
ことを特徴とする半導体集積回路装置。 - 請求項18記載の半導体集積回路装置において、
前記第2ナノワイヤFETは、前記スタンダードセルに含まれたナノワイヤFETの中で、前記スタンダードセルの前記第1方向における一方の端に、最も近い
ことを特徴とする半導体集積回路装置。 - 第1ナノワイヤFET(Field Effect Transistor)と、第2ナノワイヤFETとを備えたスタンダードセルを備え、
前記第1ナノワイヤFETは、
第1方向に延びるNa(Naは1以上の整数)本の第1ナノワイヤと、
前記第1ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記第1ナノワイヤの下面よりも低い位置にあり、前記第1ナノワイヤと接続された一対の第1パッドと、
前記第1方向と垂直をなす第2方向に延び、前記第1ナノワイヤの前記第1方向における所定範囲において、前記第1ナノワイヤの周囲を囲うように設けられた第1ゲート電極とを備えており、
前記第2ナノワイヤFETは、
第1方向に延びるNa本の第2ナノワイヤと、
前記第2ナノワイヤの前記第1方向における両端にそれぞれ設けられ、下面が前記第2ナノワイヤの下面よりも低い位置にあり、前記第2ナノワイヤと接続された一対の第2パッドと、
前記第2方向に延び、前記第2ナノワイヤの前記第1方向における所定範囲において、前記第2ナノワイヤの周囲を囲うように設けられた第2ゲート電極とを備えており、
前記スタンダードセルは、前記第1ナノワイヤFETの前記第1パッドの一方であり、かつ、前記第2ナノワイヤFETの前記第2パッドの一方である共有パッドを備え、
前記共有パッドは、前記第1パッドの他方、および、前記第2パッドの他方よりも、前記第2方向における配置範囲が小さい
ことを特徴とする半導体集積回路装置。 - 請求項20記載の半導体集積回路装置において、
前記第1ナノワイヤFETは、前記スタンダードセルに含まれたナノワイヤFETの中で、前記スタンダードセルの前記第1方向における一方の端に、最も近い
ことを特徴とする半導体集積回路装置。
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