JPWO2014184873A1 - 部品内蔵基板の製造方法及び部品内蔵基板 - Google Patents
部品内蔵基板の製造方法及び部品内蔵基板 Download PDFInfo
- Publication number
- JPWO2014184873A1 JPWO2014184873A1 JP2015516796A JP2015516796A JPWO2014184873A1 JP WO2014184873 A1 JPWO2014184873 A1 JP WO2014184873A1 JP 2015516796 A JP2015516796 A JP 2015516796A JP 2015516796 A JP2015516796 A JP 2015516796A JP WO2014184873 A1 JPWO2014184873 A1 JP WO2014184873A1
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- component
- metal layer
- insulating layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 72
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 71
- 229910052751 metal Inorganic materials 0.000 claims abstract description 174
- 239000002184 metal Substances 0.000 claims abstract description 174
- 239000010410 layer Substances 0.000 claims description 259
- 238000000034 method Methods 0.000 claims description 37
- 230000015572 biosynthetic process Effects 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 18
- 239000011347 resin Substances 0.000 claims description 17
- 229920005989 resin Polymers 0.000 claims description 17
- 238000007747 plating Methods 0.000 claims description 16
- 239000012790 adhesive layer Substances 0.000 claims description 15
- 239000004020 conductor Substances 0.000 claims description 13
- 230000000149 penetrating effect Effects 0.000 claims description 9
- 238000010030 laminating Methods 0.000 claims description 5
- 238000002360 preparation method Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 32
- 238000012986 modification Methods 0.000 description 10
- 230000004048 modification Effects 0.000 description 10
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000011810 insulating material Substances 0.000 description 7
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 239000000126 substance Substances 0.000 description 4
- 229910001220 stainless steel Inorganic materials 0.000 description 3
- 239000010935 stainless steel Substances 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 239000011889 copper foil Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 239000002244 precipitate Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000000047 product Substances 0.000 description 2
- 230000007261 regionalization Effects 0.000 description 2
- 238000012827 research and development Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000006355 external stress Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/293—Organic, e.g. plastic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2518—Disposition being disposed on at least two different sides of the body, e.g. dual array
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73217—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
- H01L2224/82009—Pre-treatment of the connector or the bonding area
- H01L2224/8203—Reshaping, e.g. forming vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10007—Types of components
- H05K2201/10166—Transistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
Field-Effect Transistor)を使用する場合、電気特性を向上させるために当該MOSFETのドレイン端子と部品内蔵基板の配線層とを電気的に接続するドレインビアを形成する。そして、部品内蔵基板の多層配線を形成するために、当該ドレインビアに接続された配線層(すなわち、内層配線)を絶縁層で覆うとともに、当該絶縁層の表面上に別の配線層(すなわち、外層配線)を形成することになる。
以下において、本発明の実施例に係る部品内蔵基板の製造方法について、図1乃至図9を参照して詳細に説明する。ここで、図1乃至図9は、本実施例に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。
本発明にかかる部品内蔵基板の製造方法は、上述した実施例に限定されることがなく、第2導通ビアが内側金属層と接触するように、内側金属層のパターン形成、第2ビア、及び第2導通ビアの形成を行ってもよい。このような場合の部品内蔵基板の製造方法及びこれによって製造される部品内蔵基板20’を図10乃至図13を参照しつつ説明する。ここで、図10乃至図13は、変形例に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。なお、上述した実施例における図1乃至図5の製造工程(準備工程〜第1ビア7の形成工程)の説明は、変形例における製造方法においても同一であるため、その説明は省略する。また、上述した実施例に係る部品内蔵基板20と同一構成については、同一の符号を付し、その説明を省略する。
2 金属膜
3 接着層
4 IC部品
4a 第1表面
4b 第1端子
4c 第2表面
4d 第2端子
5 第1絶縁層
6 内側金属層
7 第1ビア
8 第1導通ビア
9 第1端子用配線パターン
11 第2絶縁層
12 第3絶縁層
13 第1外側金属層
14 第2外側金属層
15 第2ビア
16 第2導通ビア
17 第2端子用配線パターン
20、20’ 部品内蔵基板
21 第2ビア
22 第2導通ビア
Claims (12)
- 第1表面側に第1端子を備えるとともに、前記1表面側よりも脆弱な構造を有する第2表面側に第2端子を備えるIC部品を内蔵する部品内蔵基板の製造方法であって、
表面上に金属膜が形成された支持板を準備する準備工程と、
前記金属膜の表面上に接着層を介して前記第1端子を接合するとともに、前記接着層側とは反対側に前記第2端子を配置してIC部品を搭載する搭載工程と、
前記金属膜及び前記IC部品を覆うように絶縁樹脂材料を積層し、前記IC部品を埋設する第1絶縁層を形成する第1絶縁層形成工程と、
前記第1絶縁層の表面上に内側金属層を形成する内側金属層形成工程と、
前記第1端子と前記金属膜とを電気的に接続して第1端子用配線パターンを形成する配線パターン形成工程と、
前記内側金属層を覆うように絶縁樹脂材料を積層して第2絶縁層を形成する第2絶縁層形成工程と、
前記第2絶縁層の表面上に外側金属層を形成する外側金属層形成工程と、
前記外側金属層から前記第1絶縁層及び前記第2絶縁層を貫通して前記第2端子に到達するビアを形成し、前記ビア内に導電体を充填して前記外側金属層と前記第2端子とを電気的に接続する導通ビアを形成する導通ビア形成工程と、を含むことを特徴とする部品内蔵基板の製造方法。 - 前記第1端子はソース端子及びゲート端子の少なくともいずれかであり、且つ前記第2端子はドレイン端子であることを特徴とする請求項1に記載の部品内蔵基板の製造方法。
- 前記内側金属層形成工程においては、前記内側金属層に所望の形状を形成するパターン形成工程を含み、
前記導通ビア形成工程においては、前記内側金属層の非形成部分における前記第2絶縁層を貫通し、前記外側金属層と前記第2端子とを直接的に接続することを特徴とする請求項1又は2に記載の部品内蔵基板の製造方法。 - 前記導通ビア形成工程においては、前記導通ビアと前記内側金属層とを接触させつつ、前記第2端子、前記内側金属層、及び前記外側金属層を導通ビアによって電気的に接続させることを特徴とする請求項1又は2に記載の部品内蔵基板の製造方法。
- 前記導通ビア形成工程においては、フィルドメッキ又は導電性ペーストの充填によって前記導通ビアを形成することを特徴とする請求項1乃至4のいずれか1項に記載の部品内蔵基板の製造方法。
- 前記外側金属層形成工程の後に前記導通ビア形成工程を行うことにより、前記IC部品におけるクラックの発生が防止されていることを特徴とする請求項1乃至5のいずれか1項に記載の部品内蔵基板の製造方法。
- 絶縁樹脂材料を含む第1絶縁層と、
第1表面側に第1端子を備え、且つ前記1表面側よりも脆弱な構造を有する第2表面側に第2端子を備えるとともに、前記絶縁層に埋設されたIC部品と、
前記IC部品の前記第1端子と前記第1絶縁層の外部とを電気的に接続する第1端子用配線パターンと、
前記第1絶縁層における前記第1端子用配線パターンの形成面とは反対側に形成された内側金属層と、
絶縁樹脂材料を含み、前記内側金属層を覆うように形成された第2絶縁層と、
前記第2絶縁層上に形成された外側金属層と、
前記第1絶縁層及び前記第2絶縁層を貫通して前記外側金属層と前記第2端子とを電気的に接続する導通ビアと、を有し、
前記導通ビアは、前記第1絶縁層を貫通する部分と、前記第2絶縁層を貫通する部分とが同一工程内にて形成されることを特徴とする部品内蔵基板。 - 前記第1端子はソース端子及びゲート端子の少なくともいずれかであり、且つ前記第2端子はドレイン端子であることを特徴とする請求項7に記載の部品内蔵基板。
- 前記導通ビアは、前記外側金属層と前記内側金属層とを電気的に接続することなく、前記外側金属層と前記第2端子とを直接的に接続することを特徴とする請求項7又は8に記載の部品内蔵基板。
- 前記導通ビアは、前記内側金属層を貫通しつつ、前記外側金属層、前記内側金属層、及び前記第2端子を電気的に接続することを特徴とする請求項7又は8に記載の部品内蔵基板。
- 前記導通ビアは、フィルドメッキ又は導電性ペーストの充填によって形成されることを特徴とする請求項7乃至10のいずれか1項に記載の部品内蔵基板。
- 前記外側金属層の形成後に前記導通ビアを形成することにより、前記IC部品にクラックが発生しないことを特徴とする請求項7乃至11に記載の部品内蔵基板。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2013/063432 WO2014184873A1 (ja) | 2013-05-14 | 2013-05-14 | 部品内蔵基板の製造方法及び部品内蔵基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2014184873A1 true JPWO2014184873A1 (ja) | 2017-02-23 |
JP6235575B2 JP6235575B2 (ja) | 2017-11-22 |
Family
ID=51897894
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015516796A Active JP6235575B2 (ja) | 2013-05-14 | 2013-05-14 | 部品内蔵基板の製造方法及び部品内蔵基板 |
Country Status (7)
Country | Link |
---|---|
US (1) | US9793218B2 (ja) |
EP (1) | EP2999319B1 (ja) |
JP (1) | JP6235575B2 (ja) |
KR (1) | KR20160007546A (ja) |
CN (1) | CN105210462B (ja) |
TW (1) | TWI622333B (ja) |
WO (1) | WO2014184873A1 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2016160775A1 (en) * | 2015-03-30 | 2016-10-06 | Murata Manufacturing Co., Ltd. | High-frequency transformer design for dc/dc resonant converters |
WO2017103998A1 (ja) * | 2015-12-15 | 2017-06-22 | 株式会社メイコー | 部品内蔵基板、及び部品内蔵基板の製造方法 |
WO2018182613A1 (en) * | 2017-03-30 | 2018-10-04 | Intel Corporation | Formation of tall metal pillars using multiple photoresist layers |
JP6904055B2 (ja) * | 2017-05-19 | 2021-07-14 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
CN109413892A (zh) * | 2018-12-17 | 2019-03-01 | 盐城维信电子有限公司 | 一种柔性线路板的导通孔局部电镀铜方法 |
CN109661126A (zh) * | 2018-12-17 | 2019-04-19 | 盐城维信电子有限公司 | 一种柔性线路板的导通孔整板电镀铜方法 |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001053447A (ja) * | 1999-08-05 | 2001-02-23 | Iwaki Denshi Kk | 部品内蔵型多層配線基板およびその製造方法 |
US6292366B1 (en) * | 2000-06-26 | 2001-09-18 | Intel Corporation | Printed circuit board with embedded integrated circuit |
JP2001332866A (ja) * | 2000-05-24 | 2001-11-30 | Matsushita Electric Ind Co Ltd | 回路基板及びその製造方法 |
WO2003065779A1 (en) * | 2002-01-31 | 2003-08-07 | Imbera Electronics Oy | Method for embedding a component in a base |
WO2003065778A1 (en) * | 2002-01-31 | 2003-08-07 | Imbera Electronics Oy | Method for embedding a component in a base and forming a contact |
JP2004179288A (ja) * | 2002-11-26 | 2004-06-24 | Shinko Electric Ind Co Ltd | 電子部品実装構造及びその製造方法 |
JP2005045228A (ja) * | 2003-07-09 | 2005-02-17 | Matsushita Electric Ind Co Ltd | 光学情報記録媒体とその製造方法 |
US20060145328A1 (en) * | 2005-01-06 | 2006-07-06 | Shih-Ping Hsu | Three dimensional package structure with semiconductor chip embedded in substrate and method for fabricating the same |
JP2007173276A (ja) * | 2005-12-19 | 2007-07-05 | Tdk Corp | Ic内蔵基板の製造方法 |
JP2007535157A (ja) * | 2004-04-27 | 2007-11-29 | イムベラ エレクトロニクス オサケユキチュア | 電子モジュール及びその製造方法 |
JP2008159805A (ja) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | プリント配線板、プリント配線板の製造方法および電子機器 |
JP2011522403A (ja) * | 2008-05-30 | 2011-07-28 | アーテー・ウント・エス・オーストリア・テヒノロギー・ウント・ジュステームテッヒニク・アクチェンゲゼルシャフト | 少なくとも1つの電子構成部品をプリント回路基板に組み込むための方法、およびプリント回路基板 |
JP2011249745A (ja) * | 2010-04-28 | 2011-12-08 | Denso Corp | 多層基板 |
WO2012009831A1 (zh) * | 2010-07-23 | 2012-01-26 | 欣兴电子股份有限公司 | 线路板及其制造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FI20040592A (fi) * | 2004-04-27 | 2005-10-28 | Imbera Electronics Oy | Lämmön johtaminen upotetusta komponentista |
KR100714196B1 (ko) * | 2005-07-11 | 2007-05-02 | 삼성전기주식회사 | 전기소자를 내장한 인쇄회로기판 및 그 제조방법 |
JP4535002B2 (ja) * | 2005-09-28 | 2010-09-01 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
JP4874305B2 (ja) | 2008-07-22 | 2012-02-15 | 株式会社メイコー | 電気・電子部品内蔵回路基板とその製造方法 |
US7902661B2 (en) * | 2009-02-20 | 2011-03-08 | National Semiconductor Corporation | Integrated circuit micro-module |
US8664043B2 (en) * | 2009-12-01 | 2014-03-04 | Infineon Technologies Ag | Method of manufacturing a laminate electronic device including separating a carrier into a plurality of parts |
JP2011222554A (ja) | 2010-04-02 | 2011-11-04 | Denso Corp | 半導体チップ内蔵配線基板 |
-
2013
- 2013-05-14 CN CN201380076622.6A patent/CN105210462B/zh not_active Expired - Fee Related
- 2013-05-14 US US14/890,896 patent/US9793218B2/en active Active
- 2013-05-14 WO PCT/JP2013/063432 patent/WO2014184873A1/ja active Application Filing
- 2013-05-14 EP EP13884904.7A patent/EP2999319B1/en active Active
- 2013-05-14 JP JP2015516796A patent/JP6235575B2/ja active Active
- 2013-05-14 KR KR1020157034006A patent/KR20160007546A/ko active IP Right Grant
-
2014
- 2014-03-26 TW TW103111181A patent/TWI622333B/zh not_active IP Right Cessation
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001053447A (ja) * | 1999-08-05 | 2001-02-23 | Iwaki Denshi Kk | 部品内蔵型多層配線基板およびその製造方法 |
JP2001332866A (ja) * | 2000-05-24 | 2001-11-30 | Matsushita Electric Ind Co Ltd | 回路基板及びその製造方法 |
US6292366B1 (en) * | 2000-06-26 | 2001-09-18 | Intel Corporation | Printed circuit board with embedded integrated circuit |
WO2003065779A1 (en) * | 2002-01-31 | 2003-08-07 | Imbera Electronics Oy | Method for embedding a component in a base |
WO2003065778A1 (en) * | 2002-01-31 | 2003-08-07 | Imbera Electronics Oy | Method for embedding a component in a base and forming a contact |
JP2004179288A (ja) * | 2002-11-26 | 2004-06-24 | Shinko Electric Ind Co Ltd | 電子部品実装構造及びその製造方法 |
JP2005045228A (ja) * | 2003-07-09 | 2005-02-17 | Matsushita Electric Ind Co Ltd | 光学情報記録媒体とその製造方法 |
JP2007535157A (ja) * | 2004-04-27 | 2007-11-29 | イムベラ エレクトロニクス オサケユキチュア | 電子モジュール及びその製造方法 |
US20060145328A1 (en) * | 2005-01-06 | 2006-07-06 | Shih-Ping Hsu | Three dimensional package structure with semiconductor chip embedded in substrate and method for fabricating the same |
JP2007173276A (ja) * | 2005-12-19 | 2007-07-05 | Tdk Corp | Ic内蔵基板の製造方法 |
JP2008159805A (ja) * | 2006-12-22 | 2008-07-10 | Toshiba Corp | プリント配線板、プリント配線板の製造方法および電子機器 |
JP2011522403A (ja) * | 2008-05-30 | 2011-07-28 | アーテー・ウント・エス・オーストリア・テヒノロギー・ウント・ジュステームテッヒニク・アクチェンゲゼルシャフト | 少なくとも1つの電子構成部品をプリント回路基板に組み込むための方法、およびプリント回路基板 |
JP2011249745A (ja) * | 2010-04-28 | 2011-12-08 | Denso Corp | 多層基板 |
WO2012009831A1 (zh) * | 2010-07-23 | 2012-01-26 | 欣兴电子股份有限公司 | 线路板及其制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI622333B (zh) | 2018-04-21 |
EP2999319A1 (en) | 2016-03-23 |
CN105210462B (zh) | 2018-05-25 |
KR20160007546A (ko) | 2016-01-20 |
CN105210462A (zh) | 2015-12-30 |
TW201511623A (zh) | 2015-03-16 |
WO2014184873A1 (ja) | 2014-11-20 |
EP2999319B1 (en) | 2020-07-08 |
US20160099215A1 (en) | 2016-04-07 |
JP6235575B2 (ja) | 2017-11-22 |
US9793218B2 (en) | 2017-10-17 |
EP2999319A4 (en) | 2017-01-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6235575B2 (ja) | 部品内蔵基板の製造方法及び部品内蔵基板 | |
TWI466607B (zh) | 具有內埋元件的電路板及其製作方法 | |
US9190386B2 (en) | Substrate, chip package and method for manufacturing substrate | |
JPWO2014162478A1 (ja) | 部品内蔵基板及びその製造方法 | |
TWI466606B (zh) | 具有內埋元件的電路板及其製作方法 | |
US20140233199A1 (en) | Component built-in board and method of manufacturing the same, and mounting body | |
KR20150081155A (ko) | 패키지 기판, 패키지 기판 제조 방법 및 이를 이용한 반도체 패키지 | |
KR20150137829A (ko) | 패키지 기판 및 패키지 기판 제조 방법 | |
JP6084283B2 (ja) | 部品内蔵基板及びその製造方法 | |
US9433108B2 (en) | Method of fabricating a circuit board structure having an embedded electronic element | |
TWI477214B (zh) | 具有內埋元件的電路板及其製作方法 | |
JP2009060144A (ja) | 電子部品内蔵型多層基板 | |
WO2014188493A1 (ja) | 部品内蔵基板及びその製造方法 | |
JP2008084998A (ja) | 板状体およびそれを用いた回路装置の製造方法 | |
WO2017103998A1 (ja) | 部品内蔵基板、及び部品内蔵基板の製造方法 | |
JP2005243986A (ja) | 配線基板の製造方法 | |
TW201023319A (en) | Packaging substrate and method for fabricating the same | |
JP2011044523A (ja) | 樹脂多層基板及び該樹脂多層基板の製造方法 | |
TW200931458A (en) | Capacitors and method for manufacturing the same | |
JP6839099B2 (ja) | 部品内蔵基板及び部品内蔵基板の製造方法 | |
CN105244348A (zh) | 封装基板及其制造方法 | |
JP2005063988A (ja) | 配線基板の製造方法 | |
KR20160014432A (ko) | 절연 필름, 이를 이용한 인쇄회로기판 및 그 제조 방법 | |
KR20150134699A (ko) | 회로기판의 제조방법 | |
JP2004063577A (ja) | 半導体パッケージの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20170118 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170303 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20170524 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20170822 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20170926 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20171018 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20171026 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6235575 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |