JP6839099B2 - 部品内蔵基板及び部品内蔵基板の製造方法 - Google Patents
部品内蔵基板及び部品内蔵基板の製造方法 Download PDFInfo
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- JP6839099B2 JP6839099B2 JP2017561097A JP2017561097A JP6839099B2 JP 6839099 B2 JP6839099 B2 JP 6839099B2 JP 2017561097 A JP2017561097 A JP 2017561097A JP 2017561097 A JP2017561097 A JP 2017561097A JP 6839099 B2 JP6839099 B2 JP 6839099B2
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- 238000004519 manufacturing process Methods 0.000 title claims description 54
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 360
- 229910052802 copper Inorganic materials 0.000 claims description 344
- 239000010949 copper Substances 0.000 claims description 344
- 239000000758 substrate Substances 0.000 claims description 108
- 229920005989 resin Polymers 0.000 claims description 29
- 239000011347 resin Substances 0.000 claims description 29
- 238000000034 method Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 13
- 230000008569 process Effects 0.000 claims description 6
- 238000010030 laminating Methods 0.000 claims description 3
- 230000017525 heat dissipation Effects 0.000 description 19
- 239000000853 adhesive Substances 0.000 description 16
- 230000001070 adhesive effect Effects 0.000 description 16
- 239000011889 copper foil Substances 0.000 description 16
- 230000015572 biosynthetic process Effects 0.000 description 10
- 238000007747 plating Methods 0.000 description 8
- 239000004020 conductor Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 230000006872 improvement Effects 0.000 description 5
- 238000005530 etching Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 238000012986 modification Methods 0.000 description 4
- 229910001220 stainless steel Inorganic materials 0.000 description 4
- 239000010935 stainless steel Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000001678 irradiating effect Effects 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229920006332 epoxy adhesive Polymers 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000001556 precipitation Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000013585 weight reducing agent Substances 0.000 description 1
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
- H05K1/0203—Cooling of mounted components
- H05K1/0204—Cooling of mounted components using means for thermal conduction connection in the thickness direction of the substrate
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
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- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H01—ELECTRIC ELEMENTS
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
以下において、本発明の実施例1に係る部品内蔵基板の製造方法及び完成した部品内蔵基板について、図1乃至図8を参照して詳細に説明する。ここで、図1乃至図4、図7及び図10は、本実施例1に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。また、図5及び図6は、内蔵されたIC部品の各端子を平面視した場合におけるIC部品、銅端子、及びビアの位置関係を示す部分拡大平面図であり、図5が第1銅端子側(図4における下側)の部分拡大平面図、図6が第2銅端子側(図4における上側)の部分拡大平面図を示す。更に、図8及び図9は、内蔵されたIC部品の各端子を平面視した場合におけるIC部品、銅端子、及び銅接続部の位置関係を示す部分拡大平面図であり、図8が第1銅端子側(図7における下側)の部分拡大平面図、図9が第2銅端子側(図7における上側)の部分拡大平面図を示す。
以下において、実施例1とは異なる製造方法にて本発明に係る部品内蔵基板を製造すること、及び製造される部品内蔵基板について、図13乃至図18を参照しつつ実施例2として説明する。ここで、図13乃至図18は、本実施例2に係る部品内蔵基板の製造方法の各製造工程における概略断面図である。
本発明の第1実施態様に係る部品内蔵基板は、絶縁樹脂材料を含む絶縁層と、第1表面に第1銅端子、及び前記第1表面とは反対側の第2表面に第2銅端子を備えるとともに、前記絶縁層に埋設されたIC部品と、前記絶縁層の第1表面に形成された第1外層配線パターンと、前記絶縁層の第1表面とは反対側の第2表面に形成された第2外層配線パターンと、前記第1銅端子と前記第1外層配線パターンとを電気的に接続する第1銅接続部と、前記第2銅端子と前記第2外層配線パターンとを電気的に接続する第2銅接続部と、を有し、前記第1銅端子と前記第1銅接続部と接続面は前記第1銅端子の表面形状に沿って位置し、前記第2銅端子と前記第2銅接続部と接続面は前記第2銅端子の表面形状に沿って位置していることである。
2 接着剤
3 支持部材
4 IC部品
4a 第1表面
4b 第1銅端子
4c 第2表面
4d 第2銅端子
5 絶縁層
5a 第1表面
5b 第2表面
6 プリプレグ
7 配線パターン付樹脂体
7a 樹脂基体
7b 配線パターン
7c 貫通孔
7d 側面
8 プリプレグ
9 挟持板(支持板)
11 第1ビア
12 第2ビア
13 第3ビア
14 第4ビア
15 第1導通ビア(第1銅接続部)
16 第2導通ビア
17 第3導通ビア(第2銅接続部)
18 第4導通ビア
21 第1銅配線層
22 第2銅配線層
23 第1外層配線パターン
24 第2外層配線パターン
30 部品内蔵基板
Claims (7)
- 絶縁樹脂材料を含む絶縁層と、
第1表面に第1銅端子、及び前記第1表面とは反対側の第2表面に第2銅端子を備えるとともに、前記絶縁層に埋設されたIC部品と、
前記絶縁層の第1表面に形成された第1外層配線パターンと、
前記絶縁層の第1表面とは反対側の第2表面に形成された第2外層配線パターンと、
平面形状が前記第1銅端子に相似し、前記第1銅端子と前記第1外層配線パターンとを電気的に接続する第1銅接続部と、
平面形状が前記第2銅端子に相似し、前記第2銅端子と前記第2外層配線パターンとを電気的に接続する第2銅接続部と、を有し、
前記第1銅端子と前記第1銅接続部と接続面は前記第1銅端子の表面形状に沿って位置し、前記第2銅端子と前記第2銅接続部と接続面は前記第2銅端子の表面形状に沿って位置し、
前記第1銅端子に対する前記第1銅接続部の被覆率、及び前記第2銅端子に対する前記第2銅接続部の被覆率は、50%以上である、部品内蔵基板。 - 前記第1銅端子又は前記第2銅端子のいずれか一方は、前記IC部品の表面全体に形成されているドレイン端子である請求項1に記載の部品内蔵基板。
- 前記第1銅接続部及び第2銅接続部は、単一の接続部材から構成されている請求項1又は2に記載の部品内蔵基板。
- 前記第1銅接続部及び第2銅接続部は、複数の接続部材から構成されている請求項1又は2に記載の部品内蔵基板。
- 第1表面に第1銅端子、及び前記第1表面とは反対側の第2表面に第2銅端子を備えるIC部品を内蔵する部品内蔵基板の製造方法であって、
第1銅端子を支持部材に接触させ、前記IC部品を前記支持部材上に搭載する搭載工程と、
前記IC部品を覆うように絶縁樹脂材料を積層し、前記IC部品を埋設する絶縁層を形成する絶縁層形成工程と、
平面形状が前記第1銅端子に相似し、前記第1銅端子に電気的に接続する第1銅接続部を形成する第1銅接続部形成工程と、
平面形状が前記第2銅端子に相似し、前記第2銅端子に電気的に接続する第2銅接続部を形成する第2銅接続部形成工程と、
前記第1銅接続部に電気的に接続する第1外層配線パターンを前記絶縁層の第1表面上に形成する第1外層配線パターン形成工程と、
前記第2銅接続部に電気的に接続する第2外層配線パターンを前記絶縁層の第2表面上に形成する第2外層配線パターン形成工程と、を有し、
前記第1銅接続部形成工程においては、前記第1銅端子と前記第1銅接続部と接続面を前記第1銅端子の表面形状に沿って位置し、
前記第2銅接続部形成工程においては、前記第2銅端子と前記第2銅接続部と接続面を前記第2銅端子の表面形状に沿って位置し、
前記第1銅接続部形成工程及び前記第2銅接続部形成工程においては、前記第1銅端子に対する前記第1銅接続部の被覆率、及び前記第2銅端子に対する前記第2銅接続部の被覆率を、50%以上とする、部品内蔵基板の製造方法。 - 前記第1銅接続部形成工程及び前記第2銅接続部形成工程においては、単一の接続部材から前記第1銅接続部及び第2銅接続部を形成する請求項5に記載の部品内蔵基板の製造方法。
- 前記第1銅接続部形成工程及び前記第2銅接続部形成工程においては、複数の接続部材から前記第1銅接続部及び第2銅接続部を形成する請求項5に記載の部品内蔵基板の製造方法。
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PCT/JP2016/050745 WO2017122284A1 (ja) | 2016-01-12 | 2016-01-12 | 部品内蔵基板及び部品内蔵基板の製造方法 |
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JP2015015349A (ja) * | 2013-07-04 | 2015-01-22 | 株式会社ジェイテクト | 半導体装置 |
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TW201725946A (zh) | 2017-07-16 |
WO2017122284A1 (ja) | 2017-07-20 |
JPWO2017122284A1 (ja) | 2018-11-01 |
CN108464061A (zh) | 2018-08-28 |
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