JPWO2014136252A1 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 160
- 238000001514 detection method Methods 0.000 claims abstract description 50
- 230000000670 limiting effect Effects 0.000 claims abstract description 36
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 8
- 239000010949 copper Substances 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 229910002601 GaN Inorganic materials 0.000 claims description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 2
- 239000010432 diamond Substances 0.000 claims description 2
- 229910003460 diamond Inorganic materials 0.000 claims description 2
- 239000000463 material Substances 0.000 claims description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 2
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 16
- 230000007423 decrease Effects 0.000 description 15
- 230000000052 comparative effect Effects 0.000 description 9
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 230000002829 reductive effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 5
- 238000000034 method Methods 0.000 description 3
- 230000003068 static effect Effects 0.000 description 3
- 238000001816 cooling Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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Abstract
Description
図1は本発明の実施の形態1による半導体装置を示す回路図である。ここでは、パワー半導体素子1として、MOSFET1(Metal Oxide Semiconductor Field Effect Transistor)を用いているが、IGBT(Insulated Gate Bipolar Transistor)などゲート電極で制御する他のパワー半導体を用いても良い。図1では、パワー半導体素子1に対向して配置される還流ダイオードは省略して図示している。ここで述べる半導体装置は、例えば図13に示す3相インバータ回路など、各種電力変換器に用いることが可能である。
(ゲート電流の最大値)=(駆動回路の電源電圧)÷(ゲート抵抗) (1)
となる。ゲート電圧が上昇するとともにゲート電流は低下し、t2からt3の期間に一定の電流値になる。ゲート電流が一定となるt2からt3の期間をミラー期間と呼び、スイッチング速度はミラー期間のゲート電流によって定まる。一般にパワー半導体素子1の定格電流におけるミラー電圧は11V程度になる。駆動回路6の電源電圧を15Vとすれば、ミラー期間のゲート電流は、
(ミラー期間のゲート電流)=(4V)÷(ゲート抵抗) (2)
となる。t3のタイミングでドレイン電圧の変化が終わるとミラー期間も終了し、再びゲート電圧は上昇し、t4のタイミングで駆動回路6の電源電圧まで上昇する。
Ic=(Vcc−Vce)/Rg (3)
ただし、Icはトランジスタ13のコレクタ電流、Vceはトランジスタ13のコレクタ電圧、Vccは駆動回路6の電源電圧、Rgは駆動回路6内部のゲート抵抗7である。
図12は、本発明の実施の形態2による半導体装置を示す回路図である。図12において、図1と同一符号は、同一または相当する部分を示す。図12に示す回路は、図1の回路にラッチ回路20が付加されている。電流検出部4において、過電流と判断される所定の閾値を超えた電流が検出されると、過電流保護回路8が動作して、パワー半導体素子1の電流が小さくなる。パワー半導体素子1の電流が小さくなると、電流検出部4における電流検出値も小さくなるため、過電流制限回路5への入力も小さくなり、過電流制限回路5のトランジスタ13のコレクタ電圧が上昇する。トランジスタ13のコレクタ電圧が上昇すると、パワー半導体素子1のゲート電圧も上昇し、パワー半導体素子1の電流が大きくなってしまう。再び過電流と判断される所定の閾値まで電流が達すると、過電流保護回路8が動作するというように、パワー半導体素子1の電流の上昇と下降が繰り返される。ラッチ回路20は、一旦電流検出部4において、過電流と判断される所定の閾値を超えた電流が検出されると、電流検出値が下がっても、所定時間、トランジスタ13への出力を下げない、すなわちラッチ動作を行う回路である。
図13は、本発明の半導体装置を適用する電力変換器の一例としての3相インバータ回路を示す回路図である。図13の回路は、交流を直流に変換し、変換された直流をスイッチングして3相の交流に変換してモータMを駆動する電力変換器である。図13の回路では、上側のアーム100a、100b、100c、下側のアーム200a、200b、200cそれぞれに、複数のパワー半導体素子が並列に接続された構成となっている。上側のアーム100aと下側のアーム200aの詳細を図14に示す。下側のアーム200aを例にとって詳細を説明すると、それぞれパワー半導体素子としてのIGBT21a〜28aと、それぞれのIGBTにそれぞれ並列接続されたダイオード31a〜38aのセットが並列接続された構成となっている。さらに、IGBTと並列に接続されたダイオードのセット8個は、IGBTと並列に接続されたダイオードのセット4個ずつを基板201aおよび基板202aに配置した2個のモジュールを並列に接続して実装されている。
4:電流検出部、5:過電流制限回路、6:駆動回路、
8:過電流保護回路、9:過電流検出回路、10:フィルタ回路、
13:トランジスタ、14:ゲート電流制御回路、201a、
202a:基板
Claims (10)
- 第一電極と第二電極の間に流れる主電流をゲートに印加される電圧により制御するパワー半導体素子が主セルと電流センスセルを備え、前記主セルの電流を前記電流センスセルの出力電流により検出して、前記パワー半導体素子の電流が過電流となった場合に前記パワー半導体素子を保護するための過電流保護回路を備えた半導体装置において、
前記過電流保護回路は、前記電流センスセルの出力電流を検出する電流検出部と、この電流検出部の出力信号に応じて前記ゲートに印加される電圧を低下させる過電流制限回路と、前記ゲートに印加される電圧を制御して前記パワー半導体素子のオンオフを制御するための駆動回路と、前記ゲートと前記駆動回路との間に接続され、出力電流が所定の一定値となるように制御するゲート電流制御回路とを備えたことを特徴とする半導体装置。 - 前記所定の一定値は、前記パワー半導体素子の正常動作時のゲート電流の値の90%から110%の範囲の値であることを特徴とする請求項1に記載の半導体装置。
- 前記過電流制限回路は、前記パワー半導体素子のゲートと前記ゲート電流制御回路の出力との接続点にコレクタが接続され、前記主セルの前記第二電極にエミッタが接続され、前記電流検出部の出力がベースに接続されたトランジスタにより構成されたことを特徴とする請求項1に記載の半導体装置。
- 前記過電流制限回路の前記トランジスタのコレクタと前記パワー半導体素子のゲートとの間には、保護用の素子が挿入され、この保護用の素子による電圧降下が2V以下であることを特徴とする請求項3に記載の半導体装置。
- 前記電流検出部と前記過電流制限回路との間に、前記電流検出部が前記パワー半導体素子の過電流を検出した場合、その検出状態を所定時間保持するラッチ回路を備えたことを特徴とする請求項1ないし4のいずれか1項に記載の半導体装置。
- 前記パワー半導体素子は、並列接続された複数のパワー半導体素子により構成されていることを特徴とする請求項1ないし5のいずれか1項に記載の半導体装置。
- 前記複数のパワー半導体素子のうち、一個のパワー半導体素子が前記主セルと前記電流センスセルを備えたパワー半導体素子であることを特徴とする請求項6に記載の半導体装置。
- 前記複数のパワー半導体素子を、銅パターンが形成された1枚の基板上に、前記複数のパワー半導体素子のそれぞれの第一電極が前記銅パターンに接続されるように配置し、前記複数のパワー半導体素子の、前記電流センスセルの第二電極以外のそれぞれの第二電極同士を前記パワー半導体素子以外の部材を介さずに直接接続するワイヤ配線により電気接続することを特徴とする請求項7に記載の半導体装置。
- 前記パワー半導体素子がワイドバンドギャップ半導体により形成されていることを特徴とする請求項1〜8のいずれか1項に記載の半導体装置。
- 前記ワイドバンドギャップ半導体は、炭化珪素、窒化ガリウム系材料、ダイヤモンドのいずれかの半導体であることを特徴とする請求項9に記載の半導体装置。
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