JPWO2014010220A1 - サブマウントおよび封止済み半導体素子ならびにこれらの作製方法 - Google Patents
サブマウントおよび封止済み半導体素子ならびにこれらの作製方法 Download PDFInfo
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- JPWO2014010220A1 JPWO2014010220A1 JP2014524647A JP2014524647A JPWO2014010220A1 JP WO2014010220 A1 JPWO2014010220 A1 JP WO2014010220A1 JP 2014524647 A JP2014524647 A JP 2014524647A JP 2014524647 A JP2014524647 A JP 2014524647A JP WO2014010220 A1 JPWO2014010220 A1 JP WO2014010220A1
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Abstract
Description
図1は、本実施形態に係るサブマウントの構成を示す図である。図1Aは、サブマウントの平面図である。図1Bは、図1Aの断面線IB−IBにおける断面図である。説明のために、図1Aの上部は樹脂108がない状態での平面図であり、図1Aの下部は樹脂108がある状態での平面図である。本願のその他の平面図についても同様に示す平面図があるので留意されたい。
図6は、本実施形態に係る半導体素子の構成を示す図である。図6Aは、半導体素子の平面図である。図6Bは、図6Aの断面線VIB−VIBにおける断面図である。
図9は、本実施形態に係るサブマウントの構成を示す図である。図9に示すように、樹脂108を金バンプ107が隠れるように塗布することができる。本実施形態に係るサブマウント100は、樹脂108が基板101上で全体に亘って塗布されないことにおいて、[第1の実施形態]と相違する。樹脂108を除く他の構成要素については、[第1の実施形態]と同一であるので、説明を省略する。
図10は、本実施形態に係るサブマウントの構成を示す図である。図10に示すように、樹脂108を金バンプ107が隠れるように塗布し、さらに別の樹脂115を基板101上に塗布することができる。本実施形態に係るサブマウント100は、樹脂115をさらに備えたことにおいて、[第3の実施形態]と相違する。樹脂115を除く他の構成要素については、[第3の実施形態]と同一であるので、説明を省略する。
図11は、本実施形態に係る封止済み半導体素子の構成を示す図である。図11に示すように、半導体素子104上で金バンプ106の周りのみに樹脂108を塗布することができる。樹脂108が金バンプ106の周りのみに塗布されること以外は、[第2の実施形態]と同一であるので、説明を省略する。
図12は、本実施形態に係る封止済み半導体素子の構成を示す図である。図12に示すように、金バンプ106を中心に樹脂108を塗布し、さらに別の樹脂115を半導体素子104上に塗布することができる。本実施形態に係る半導体素子は、樹脂115をさらに備えたことにおいて、[第5の実施形態]と相違する。
上記の[第4の実施形態]に係るサブマウントを搭載したモジュールのバリエーションについて、以下に説明する。
図15Aは、本実施形態に係るモジュールの構成を示す平面図であり、図15Bは、図15Aの断面線XVB−XVBにおける断面図である。図15AおよびBに示すように、本実施形態に係るモジュール109は、メイン基板110と、メイン基板110上の電極116と、メイン基板110上のIC111と、メイン基板110上のサブマウント100と、IC111とサブマウント100とを接続するAuワイヤ112と、IC111上の金バンプ113とから構成される。
図16Aは、本実施形態に係るモジュールの構成を示す平面図であり、図16Bは、図16Aの断面線XVIB−XVIBにおける断面図である。図16AおよびBに示すように、本実施形態に係るモジュール109は、メイン基板110と、メイン基板110上の電極116と、メイン基板110上のIC111と、IC111上のスペーサ118と、スペーサ118上のサブマウント100と、金バンプ113、117とから構成される。金バンプ117は、サブマウント100が備えた金バンプ107の露出した切断面と接触している。
上記の[第6の実施形態]に係る封止済み半導体素子を搭載したモジュールのバリエーションについて、以下に説明する。
図18Aは、本実施形態に係るモジュールの構成を示す平面図であり、図18Bは、図18Aの断面線XVIIIB−XVIIIBにおける断面図である。図18AおよびBに示すように、本実施形態に係るモジュール109は、メイン基板110と、メイン基板110上の電極116と、メイン基板110上のIC111と、メイン基板110上の封止済み半導体素子と、IC111と封止済み半導体素子とを接続するAuワイヤ112と、IC111上の金バンプ113とから構成される。
図19Aは、本実施形態に係るモジュールの構成を示す平面図であり、図19Bは、図19Aの断面線XIXB−XIXBにおける断面図である。図19AおよびBに示すように、本実施形態に係るモジュール109は、メイン基板110と、メイン基板110上の電極116と、メイン基板110上のIC111と、メイン基板110上のスペーサ118と、スペーサ118上の封止済み半導体素子と、IC111上の金バンプ113と、金バンプ117とから構成される。
図20は、本実施形態に係る封止済み半導体素子の構成を示す斜視図である。図20に示すように、本実施形態に係る封止済み半導体素子は、半導体素子104と、半導体素子104上の複数の金バンプ106と、複数の金バンプ106を半導体素子104上で封止する樹脂108とから構成される。
図23は、本実施形態に係る封止済み半導体素子の構成を示す斜視図である。図23に示すように、本実施形態に係る封止済み半導体素子は、半導体素子104と、半導体素子104上の複数の金バンプ106と、複数の金バンプ106を半導体素子104上で封止する樹脂108とから構成される。
図28AおよびBは、本実施形態に係るサブマウントの構成を示す図である。図28Bに示すように、本実施形態に係るサブマウント200は、基板201と、電極203と、半導体素子204と、Auワイヤ205と、金バンプ206および207とから構成される。本実施形態に係るサブマウント200は、基板201に溝213を設け、溝213内に半導体素子204を搭載している点で、図9の[第3の実施形態]と相違する。溝213を形成する点および半導体素子204を直接基板201上に搭載する点を除く他の構成要素については、[第3の実施形態]と同一であるので、説明を省略する。
図30は、本実施形態に係るサブマウントの構成を示す図である。図30に示すように、樹脂208を金バンプ207が隠れるように塗布し、さらに別の樹脂215を基板201上に塗布することができる。本実施形態に係るサブマウント300は、樹脂215をさらに備えたことにおいて、[第15の実施形態]と相違する。樹脂215を除く他の構成要素については、[第15の実施形態]と同一であるので、説明を省略する。
101、201:基板
102、103、116、203:電極
104、204:半導体素子
105、112、205:Auワイヤ
106、107、113、117、207:金バンプ
108、115、208、215:樹脂
109:モジュール
110:メイン基板
111:IC
114:ウエハ
118:スペーサ
120:電気的接続
121:半田
122:回路基板
123:バンプ
213、214:溝
Claims (17)
- 基板と、
前記基板上の電極と、
前記基板上の半導体素子と、
前記半導体素子および前記電極を接続するワイヤと、
前記電極上かつ前記ワイヤ上の、1または複数のバンプと
を備えたサブマウントであって、
前記電極と、前記半導体素子と、前記ワイヤと、前記1または複数のバンプとは、前記基板上で樹脂により封止され、
前記1または複数のバンプは、切断面を有し、
前記切断面は、前記サブマウントの表面に露出しており、
前記切断面は、前記サブマウントの電極であることを特徴とするサブマウント。 - 基板と、
前記基板上の電極と、
前記基板上の半導体素子と、
前記半導体素子および前記電極を接続するワイヤと、
前記電極上かつ前記ワイヤ上のバンプと
を備えたサブマウントであって、
前記バンプは、前記基板上で均一に塗布されない第1の樹脂により封止され、
前記バンプは、露出した切断面を有し、
前記露出した切断面は、サブマウントの電極であることを特徴とするサブマウント。 - 前記電極と、前記半導体素子と、前記ワイヤと、前記バンプと、前記第1の樹脂とを、封止する第2の樹脂をさらに備え、
前記第1の樹脂は、前記第2の樹脂より硬いことを特徴とする請求項2に記載のサブマウント。 - 前記基板上に溝を形成し、前記半導体素子は、前記溝内に搭載することを特徴とする請求項1乃至3のいずれか1項に記載のサブマウント。
- メイン基板と、
前記メイン基板上のICと、
前記メイン基板上の電極と、
前記ICおよび前記電極を接続するワイヤと、
前記メイン基板上の電極上の、請求項1乃至4のいずれか1項に記載のサブマウントと
を備えたモジュールであって、
前記サブマウントのバンプの露出した切断面および前記メイン基板上の電極は、導電性接着剤により接着されることを特徴とするモジュール。 - メイン基板と、
前記メイン基板上のICと、
前記メイン基板上の、請求項1乃至4のいずれか1項に記載のサブマウントと
を備えたモジュールであって、
前記メイン基板は、素子搭載面として高い面と低い面とを有し、
前記ICは、前記高い面上に実装され、前記サブマウントは、前記低い面上に実装され、
前記ICおよび前記サブマウントをワイヤボンディングするためのワイヤと
をさらに備えたことを特徴とするモジュール。 - メイン基板と、
前記メイン基板上のICと、
前記IC上のスペーサと、
前記スペーサ上の、請求項1乃至4のいずれか1項に記載のサブマウントと
を備えたモジュールであって、
前記スペーサによって作り出された空間に設置された1または複数のバンプにより、前記ICと前記サブマウントが備えたバンプとの間の電気的接続を実現することを特徴とするモジュール。 - 半導体素子と、
前記半導体素子上のバンプと
を備えた封止済み半導体素子であって、
前記バンプは、前記半導体素子上で樹脂により封止され、
前記バンプは、露出した切断面を有し、
前記露出した切断面は、封止済み半導体素子の電極であることを特徴とする封止済み半導体素子。 - 半導体素子と、
前記半導体素子上のバンプと
を備えた封止済み半導体素子であって、
前記バンプは、前記半導体素子上で前記バンプの周りのみを塗布する第1の樹脂により封止され、
前記バンプは、露出した切断面を有し、
前記露出した切断面は、封止済み半導体素子の電極であることを特徴とする封止済み半導体素子。 - 前記半導体素子と、前記バンプと、前記第1の樹脂とを、封止する第2の樹脂をさらに備え、
前記第1の樹脂は、前記第2の樹脂より硬いことを特徴とする請求項9に記載の封止済み半導体素子。 - メイン基板と、
前記メイン基板上のICと、
前記メイン基板上の電極と、
前記ICおよび前記電極を接続するワイヤと、
前記メイン基板上の電極上の、請求項8乃至10のいずれか1項に記載の封止済み半導体素子と
を備えたモジュールであって、
前記封止済み半導体素子のバンプの露出した切断面および前記メイン基板上の電極は、導電性接着剤により接着されることを特徴とするモジュール。 - メイン基板と、
前記メイン基板上のICと、
前記メイン基板上の、請求項8乃至10のいずれか1項に記載の封止済み半導体素子と
を備えたモジュールであって、
前記メイン基板は、素子搭載面として高い面と低い面とを有し、
前記ICは、前記高い面上に実装され、前記封止済み半導体素子は、前記低い面上に実装され、
前記ICおよび前記封止済み半導体素子をワイヤボンディングするためのワイヤと、
前記封止済み半導体素子が備えたバンプ上のかつ前記ワイヤ上の、バンプと
をさらに備えたことを特徴とするモジュール。 - メイン基板と、
前記メイン基板上のICと、
前記メイン基板上のスペーサと、
前記スペーサ上の、請求項8乃至10のいずれか1項に記載の封止済み半導体素子と
を備えたモジュールであって、
前記スペーサによって作り出された空間に設置された1または複数のバンプにより、前記ICと前記封止済み半導体素子が備えたバンプとの間の電気的接続を実現することを特徴とするモジュール。 - 回路基板と、
請求項8乃至10のいずれか1項に記載の封止済み半導体素子と
を備えたモジュールであって、
前記回路基板および前記封止済み半導体素子は、前記封止済み半導体素子のバンプの露出した切断面に半田付けすることにより、電気的に接続されることを特徴とするモジュール。 - 半導体素子および電極を、基板上で、ワイヤを使用したワイヤボンディングにより接続するステップと、
前記電極上にかつ前記ワイヤ上に、ボールボンディングにより、1または複数のバンプを形成するステップと、
前記半導体素子と、前記電極と、前記ワイヤと、前記バンプとを、前記基板上で樹脂により封止するステップと、
前記樹脂を硬化させるステップと、
前記基板と、前記電極と、前記1または複数のバンプと、前記樹脂とをダイシングラインに沿ってダイシングするステップと
を備えたことを特徴とするサブマウントを作製する方法。 - 前記基板上に溝を形成し、前記半導体素子を前記溝内に搭載するステップをさらに備えることを特徴とする請求項15に記載のサブマウントを作製する方法。
- ウエハ上に、ボールボンディングによりバンプを形成するステップと、
前記バンプを、前記ウエハ上で樹脂により封止するステップと、
前記樹脂を硬化させるステップと、
前記ウエハと、前記バンプと、前記樹脂とをダイシングラインに沿ってダイシングするステップと
を備えたことを特徴とする封止済み半導体素子を作製する方法。
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