US20150108636A1 - Submount, encapsulated semiconductor element, and methods of manufacturing the same - Google Patents

Submount, encapsulated semiconductor element, and methods of manufacturing the same Download PDF

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Publication number
US20150108636A1
US20150108636A1 US14/406,964 US201314406964A US2015108636A1 US 20150108636 A1 US20150108636 A1 US 20150108636A1 US 201314406964 A US201314406964 A US 201314406964A US 2015108636 A1 US2015108636 A1 US 2015108636A1
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Prior art keywords
submount
semiconductor element
main substrate
electrode
bump
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US14/406,964
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US9263411B2 (en
Inventor
Xueliang Song
Nozomu Sato
Genta Kanno
Yohko Makino
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Advanced Photonics Inc
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Advanced Photonics Inc
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Assigned to ADVANCED PHOTONICS, INC. reassignment ADVANCED PHOTONICS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KANNO, Genta, MAKINO, Yohko, SATO, Nozomu, SONG, XUELIANG
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15158—Shape the die mounting substrate being other than a cuboid
    • H01L2924/15159—Side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/157—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • the present invention relates to a submount, an encapsulated semiconductor element, and methods for manufacturing the same.
  • electrodes are formed not only on an element mounting surface of the submount but also on a side surface portion of the submount.
  • Examples of conventional techniques include a module like one shown in FIG. 26 .
  • This module 109 includes a main substrate 110 , an IC 111 on the main substrate 110 , and a submount 100 on the main substrate 110 .
  • the submount 100 includes a semiconductor element 104 on an element mounting surface.
  • a through-hole electrode and an element mounting electrode are formed as an electrode 102 in the submount 100 .
  • An electrical connection between the IC 111 and the semiconductor element 104 is achieved by connecting the IC 111 and the electrode 102 by an AU wire 112 .
  • the electrode 102 is formed over two surfaces of a substrate 101 and an electrode area is large. Accordingly, a parasitic capacitance is large. Furthermore, the module shown in FIG. 26 also includes a through-hole land portion and inevitably has a large pitch, so that there is a problem that a high-density submount cannot be manufactured.
  • An object of the present invention is to provide a high-density submount which has small parasitic capacitance and which does not require formation of a new electrode on a side surface of the submount when electrically connecting an IC and the submount to each other on a substrate.
  • another object of the present invention is to provide an encapsulated semiconductor element which does not require formation of a new electrode on a side surface of the encapsulated semiconductor element when electrically connecting an IC and the encapsulated semiconductor element to each other on a substrate.
  • the present invention provides a submount characterized in that the submount comprises: a substrate; an electrode on the substrate; a semiconductor element on the substrate; a wire connecting the semiconductor element and the electrode to each other; and one or plurality of bumps on the electrode and the wire, the electrode, the semiconductor element, the wire, and the one or plurality of bumps are encapsulated on the substrate by a resin, the one or plurality of bumps have a cut surface, the cut surface is exposed on a surface of the submount, and the cut surface is an electrode of the submount.
  • the present invention provides a submount characterized in that the submount comprises: a substrate; an electrode on the substrate; a semiconductor element on the substrate; a wire connecting the semiconductor element and the electrode to each other; and a bump on the electrode and the wire, the bump is encapsulated by a first resin which is locally applied on the substrate, the bump has an exposed cut surface, and the exposed cut surface is an electrode of the submount.
  • the submount is characterized in that the submount further comprises a second resin encapsulating the electrode, the semiconductor element, the wire, the bump, and the first resin, and the first resin is harder than the second resin. Furthermore, in one embodiment of the present invention, the submount is characterized in that a groove is formed on the substrate and the semiconductor element is mounted in the groove.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; an electrode on the main substrate; a wire connecting the IC and the electrode to each other; and the submount on the electrode on the main substrate, and the exposed cut surface of the bump of the submount and the electrode on the main substrate are bonded to each other by an electrically-conductive adhesive.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; and the submount on the main substrate, the main substrate has an upper surface and a lower surface as element mounting surfaces, the IC is mounted on the upper surface and the submount is mounted on the lower surface, and the module further comprises a wire for wire bonding the IC and the submount to each other.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; a spacer on the IC; and the submount on the spacer, and an electrical connection between the IC and the one or plurality of bumps included in the submount is achieved by one or plurality of bumps placed in a space formed by the spacer.
  • the present invention provides an encapsulated semiconductor element characterized in that the encapsulated semiconductor element comprises: a semiconductor element; and a bump on the semiconductor element, the bump is encapsulated on the semiconductor element by a resin, the bump has an exposed cut surface, and the exposed cut surface is an electrode of the encapsulated semiconductor element.
  • the present invention provides an encapsulated semiconductor element characterized in that the encapsulated semiconductor element comprises: a semiconductor element; and a bump on the semiconductor element, the bump is encapsulated by a first resin applied only to a portion around the bump on the semiconductor element, the bump has an exposed cut surface, and the exposed cut surface is an electrode of the encapsulated semiconductor element.
  • the encapsulated semiconductor element is characterized in that the encapsulated semiconductor element further comprises a second resin encapsulating the semiconductor element, the bump, and the first resin, and the first resin is harder than the second resin.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; an electrode on the main substrate; a wire connecting the IC and the electrode to each other; and the encapsulated semiconductor element on the electrode on the main substrate, and the exposed cut surface of the bump of the encapsulated semiconductor element and the electrode on the main substrate are bonded to each other by an electrically-conductive adhesive.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; and the encapsulated semiconductor element on the main substrate, the main substrate has an upper surface and a lower surface as element mounting surfaces, the IC is mounted on the upper surface and the encapsulated semiconductor element is mounted on the lower surface, and the module further comprises: a wire for wire bonding the IC and the encapsulated semiconductor element to each other; and a bump on the wire and the bump included in the encapsulated semiconductor element.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; a spacer on the main substrate; and the encapsulated semiconductor element on the spacer, an electrical connection between the IC and the bump included in the encapsulated semiconductor element is achieved by one or plurality of bumps placed in a space formed by the spacer.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a circuit board; and the encapsulated semiconductor element, and the circuit board and the encapsulated semiconductor element are electrically connected to each other by soldering the exposed cut surface of the bump of the encapsulated semiconductor element.
  • the present invention is characterized in that the invention comprises the steps of: connecting a semiconductor element and an electrode on a substrate by wire bonding using a wire; forming one or plurality of bumps on the electrode and the wire by ball bonding; encapsulating the semiconductor element, the electrode, the wire, and the bump on the substrate by a resin; curing the resin; and dicing the substrate, the electrode, the one or plurality of bumps, and the resin along a dicing line. Furthermore, the present invention is characterized that the invention comprises the step of forming a groove on the substrate and mounting the semiconductor element in the groove.
  • the present invention is characterized in that the invention comprises the steps of forming a bump on a wafer by ball bonding; encapsulating the bump on the wafer by a resin; curing the resin; and dicing the wafer, the bump, and the resin along a dicing line.
  • an IC and a fine element on a substrate can be efficiently electrically connected to each other.
  • the electrode area can be made smaller than that in conventional techniques, and this contributes to reduction of parasitic capacitance.
  • the submount is a single-layer substrate in the invention of this application. Accordingly, the submount can be manufactured at a lower cost.
  • a fine pattern for electrode formation can be formed. Since the density of the pattern can be increased, the present invention is suitable for high-density application.
  • FIG. 1A is a plan view showing a configuration of a submount in a first embodiment of the present invention
  • FIG. 1B is a cross-sectional view taken along the cross-section line IB-IB of FIG. 1A ;
  • FIG. 2 is a cross-sectional view showing a configuration of a submount in the first embodiment of the present invention
  • FIG. 3A is a view showing a step of manufacturing the submount in the first embodiment of the present invention.
  • FIG. 3B is a view showing a step of manufacturing the submount in the first embodiment of the present invention.
  • FIG. 3C is a view showing a step of manufacturing the submount in the first embodiment of the present invention.
  • FIG. 3D is a view showing a step of manufacturing the submount in the first embodiment of the present invention.
  • FIG. 4A is a plan view showing a configuration of a module including the submount in the first embodiment of the present invention
  • FIG. 4B is a cross-sectional view taken along the cross-section line IVB-IVB of FIG. 4A ;
  • FIG. 5A is a plan view showing a configuration of a module including the submount in the first embodiment of the present invention
  • FIG. 5B is a cross-sectional view taken along the cross-section line VB-VB of FIG. 5A ;
  • FIG. 6A is a plan view showing a configuration of an encapsulated semiconductor element in a second embodiment of the present invention.
  • FIG. 6B is a cross-sectional view taken along the cross-section line VIB-VIB of FIG. 6A ;
  • FIG. 7A is a view showing a step of manufacturing the encapsulated semiconductor element in the second embodiment of the present invention.
  • FIG. 7B is a view showing a step of manufacturing the encapsulated semiconductor element in the second embodiment of the present invention.
  • FIG. 7C is a view showing a step of manufacturing the encapsulated semiconductor element in the second embodiment of the present invention.
  • FIG. 8A is a plan view showing a configuration of a module including the encapsulated semiconductor element in the second embodiment of the present invention.
  • FIG. 8B is a cross-sectional view taken along the cross-section line VIIIB-VIIIB of FIG. 8A ;
  • FIG. 9 is a view showing a configuration of a submount in a third embodiment of the present invention.
  • FIG. 10 is a view showing a configuration of a submount in a fourth embodiment of the present invention.
  • FIG. 11 is a view showing a configuration of an encapsulated semiconductor element in a fifth embodiment of the present invention.
  • FIG. 12 is a view showing a configuration of an encapsulated semiconductor element in a sixth embodiment of the present invention.
  • FIG. 13A is a plan view showing a configuration of a module in a seventh embodiment of the present invention.
  • FIG. 13B is a cross-sectional view taken along the cross-section line XIIIB-XIIIB of FIG. 13A ;
  • FIG. 14 is a cross-sectional view showing a configuration of another module in the seventh embodiment of the present invention.
  • FIG. 15A is a plan view showing a configuration of a module in an eighth embodiment of the present invention.
  • FIG. 15B is a cross-sectional view taken along the cross-section line XVB-XVB of FIG. 15A ;
  • FIG. 16A is a plan view showing a configuration of a module in a ninth embodiment of the present invention.
  • FIG. 16B is a cross-sectional view taken along the cross-section line XVIB-XVIB of FIG. 16A ;
  • FIG. 17A is a plan view showing a configuration of a module in a tenth embodiment of the present invention.
  • FIG. 17B is a cross-sectional view taken along the cross-section line XVIIB-XVIIB of FIG. 17A ;
  • FIG. 18A is a plan view showing a configuration of a module in an eleventh embodiment of the present invention.
  • FIG. 18B is a cross-sectional view taken along the cross-section line XVIIIB-XVIIIB of FIG. 18A ;
  • FIG. 19A is a plan view showing a configuration of a module in a twelfth embodiment of the present invention.
  • FIG. 19B is a cross-sectional view taken along the cross-section line XIXB-XIXB of FIG. 19A ;
  • FIG. 20 is a perspective view showing a configuration of an encapsulated semiconductor element in a thirteenth embodiment of the present invention.
  • FIG. 21A is a plan view showing a configuration of a module including the encapsulated semiconductor element in the thirteenth embodiment of the present invention.
  • FIG. 21B is a cross-sectional view taken along the cross-section line XXIB-XXIB of FIG. 21A ;
  • FIG. 22A is a view showing a step of manufacturing the encapsulated semiconductor element in the thirteenth embodiment of the present invention.
  • FIG. 22B is a view showing a step of manufacturing the encapsulated semiconductor element in the thirteenth embodiment of the present invention.
  • FIG. 22C is a view showing a step of manufacturing the encapsulated semiconductor element in the thirteenth embodiment of the present invention.
  • FIG. 23 is a perspective view showing a configuration of an encapsulated semiconductor element in a fourteenth embodiment of the present invention.
  • FIG. 24A is a plan view showing a configuration of a module including the encapsulated semiconductor element in the fourteenth embodiment of the present invention.
  • FIG. 24B is a cross-sectional view taken along the cross-section line XXIVB-XXIVB of FIG. 24A ;
  • FIG. 25A is a view showing a step of manufacturing the encapsulated semiconductor element in the fourteenth embodiment of the present invention.
  • FIG. 25B is a view showing a step of manufacturing the encapsulated semiconductor element in the fourteenth embodiment of the present invention.
  • FIG. 25C is a view showing a step of manufacturing the encapsulated semiconductor element in the fourteenth embodiment of the present invention.
  • FIG. 26 is a view showing a configuration of a module including a submount of a conventional technique
  • FIG. 27A is a view showing a method of wire bonding in the first embodiment of the present invention.
  • FIG. 27B is a view showing another method of wire bonding in the first embodiment of the present invention.
  • FIG. 28A is a perspective view showing a configuration of a submount in a fifteenth embodiment of the present invention.
  • FIG. 28B is a view showing the configuration of the submount in the fifteenth embodiment of the present invention.
  • FIG. 28C is a view showing a configuration of another submount in the fifteenth embodiment of the present invention.
  • FIG. 29A is a view showing a step of wire bonding in the fifteenth embodiment of the present invention.
  • FIG. 29B is a view showing a step of wire bonding in the fifteenth embodiment of the present invention.
  • FIG. 29C is a view showing a step of wire bonding in the fifteenth embodiment of the present invention.
  • FIG. 29D is a view showing a step of wire bonding in the fifteenth embodiment of the present invention.
  • FIG. 30 is a view showing a configuration of a submount in a sixteenth embodiment of the present invention.
  • FIG. 1 includes views showing a configuration of a submount of the embodiment.
  • FIG. 1A is a plan view of the submount.
  • FIG. 1B is a cross-sectional view taken along the cross-section line IB-IB of FIG. 1A .
  • an upper portion of FIG. 1A is a plan view in which a resin 108 is not illustrated and a lower portion of FIG. 1A is a plan view in which the resin 108 is illustrated. Note that there are other plan views of this application which are illustrated in a similar way.
  • the submount 100 includes a substrate 101 , electrodes 102 , 103 , a semiconductor element 104 , Au wires 105 , and gold bumps 106 , 107 .
  • the electrodes 102 , 103 , the semiconductor element 104 , the Au wires 105 , and the gold bumps 106 , 107 are encapsulated on the substrate 101 by the resin 108 .
  • a rigid substrate such as a glass epoxy substrate, a paper phenol substrate, a paper epoxy substrate, a glass composite substrate, a Teflon (registered trademark) substrate, an alumina substrate, a silicon interposer substrate, or a LTCC substrate as well as a flexible substrate can be used as the substrate 101 .
  • the electrodes are patterned on the substrate.
  • the electrode 102 on which the semiconductor element 104 is formed and the multiple electrodes 103 arranged in a straight line on which the gold bumps 107 are formed respectively.
  • Cu can be used as an electrode material.
  • Cu plated by Ni/Au is used as the electrodes. Note that Ag, Au, and the like can be also used as the electrode material.
  • Ni/Pd/Au plating, Ni/B plating, Ni/P plating, Ag plating, Pd/Ni plating, Pd plating, Ti/Pd/Au plating, Ti/Pt/Au plating, Ti/Pd/Cu/Ni/Au plating, and the like can be also used as the plating.
  • circuit patterns such as electrodes are formed on a surface of the semiconductor element.
  • the semiconductor element 104 of the embodiment is formed on the electrode 102 , it is not necessary to form the semiconductor element on the electrode.
  • the semiconductor element can be formed anywhere on the substrate of the submount.
  • the semiconductor element 104 and the electrodes 103 are connected by wire bonding using the Au wires 105 .
  • types of wire bonding include ball bonding, wedge bonding, and the like, and wires other than the Au wires such as Pt wires, Cu wires, or Al wires can be used as the wires.
  • wire bonding can be achieved by performing (1) step of forming the gold bumps 106 of the Au wires 105 on pads of the semiconductor element 104 by a ball bonder (1st bonding), (2) step of connecting the Au wires 105 to the electrodes 103 on the substrate 101 without cutting the Au wires (2nd bonding), and (3) step of forming the gold bumps 107 on the electrodes 103 and the Au wires 105 connected in the 2nd bonding (see FIG. 27A ).
  • wire bonding can be achieved by performing (1) step of forming the gold bumps 106 of wires on the pads of the semiconductor element 104 and cutting the wires by the ball bonder, (2) step of forming the gold bumps 107 on the electrodes 103 (1st bonding) and connecting the Au wires 105 to the gold bumps 106 without cutting the Au wires (2nd bonding) (see FIG. 27B ).
  • the wire bonding is achieved by using one of these two methods.
  • the gold bumps 107 are formed on the electrodes 103 and the Au wires 105 by ball bonding.
  • the diameter of each gold bump 107 is 20 ⁇ m to 200 ⁇ m, preferably 40 ⁇ m to 100 ⁇ m.
  • the gold bumps 107 have surfaces exposed on a module side surface. These surfaces are exposed due to cut surfaces formed by dicing. A method of manufacturing the submount including dicing and the like is described later.
  • the exposed surfaces of the gold bumps 107 function as side surface electrodes of the submount 100 .
  • bumps other than the gold bumps such as platinum (Pt) bumps and copper (Cu) bumps can be used as the bumps.
  • the resin 108 encapsulates the electrodes 102 , 103 , the semiconductor element 104 , the Au wires 105 , and the gold bumps 106 , 107 on the substrate 101 .
  • a silicone resin, an epoxy resin, an acryl resin, or the like which have a thermosetting property or a UV curing property can be used as the resin 108 .
  • the resin 108 is provided to mechanically protect the semiconductor element 104 or to protect the semiconductor element 104 from environments such as moisture and heat. Considering the fact that the wire bonding is often performed together with heat treatment, a resin with sufficient hardness even in heating is preferably used as the resin 108 .
  • FIG. 2 is a cross-sectional view showing a configuration of another submount of the embodiment.
  • FIG. 1 shows a configuration in which the exposed surface of one gold bump 107 is used as each of the side surface electrodes of the submount, as shown in FIG. 2 , exposed surfaces of multiple bumps may be used as each of the side surface electrodes of the submount.
  • FIGS. 3A to 3D are views showing steps of manufacturing the submount of the embodiment.
  • the semiconductor element 104 and the electrodes 103 are connected by wire bonding using the Au wires 105 ( FIG. 3A ).
  • the gold bumps 107 are formed on the electrodes 103 and the Au wires 105 ( FIG. 3B ).
  • the resin 108 is applied to encapsulate the electrodes 102 , 103 , the semiconductor element 104 , the Au wires 105 , and the gold bumps 106 , 107 on the substrate 101 .
  • the resin 108 is applied onto the substrate 101 ( FIG. 3C ). After the application of the resin, the resin is cured by heating, UV curing, or the like.
  • dicing is performed along dicing lines to expose cut surfaces of the gold bumps 107 ( FIG. 3D ).
  • the exposed surfaces of the gold bumps 107 function as the side surface electrodes of the submount 100 .
  • FIG. 4 shows a configuration of a module including the submount of the embodiment.
  • FIG. 4A is a plan view of the module.
  • FIG. 4B is a cross-sectional view taken along the cross-section line IVB-IVB of FIG. 4A .
  • the module 109 includes a main substrate 110 , an IC 111 , the submount 100 , Au wires 112 , and gold bumps 113 .
  • the IC 111 is formed on the main substrate 110 .
  • the submount 100 is formed on the main substrate 110 .
  • a side surface of the submount 100 on which no gold bumps 107 are provided is bonded to the main substrate 110 by an adhesive or the like.
  • the IC 111 and the side surface electrodes (i.e. the exposed cut surfaces of the gold bumps 107 ) of the submount 100 are connected by wire bonding using the Au wires 112 . It is found that the cut surface of the gold bumps 107 exposed by the dicing function as the side surface electrodes of the submount 100 .
  • FIG. 5 shows another configuration of a module including the submount of the embodiment.
  • FIG. 5A is a plan view of the module.
  • FIG. 5B is a cross-sectional view taken along the cross-section line VB-VB of FIG. 5A .
  • the module 109 includes the main substrate 110 , the IC 111 , the submount 100 , pattern electrodes 116 on the main substrate 110 , bumps 123 , a spacer 118 , and electrical connections 120 .
  • the submount 100 and the IC 111 bonded to the main substrate 110 as in BGA can be electrically connected to each other by the configuration shown in FIG. 5 .
  • the submount 100 is formed on the main substrate 110 .
  • a side surface of the submount 100 on which the gold bumps 107 are provided is arranged to face downward and is connected to the electrodes 116 via the electrical connections 120 .
  • the electrical connections 120 between the gold bumps 107 and the electrodes 116 can be achieved by gold bumps or an electrically-conductive adhesive.
  • Electrical connections between the IC 111 and the electrodes 116 are formed by using the bumps 123 such as solder balls or the like.
  • the IC 111 and the submount 100 can be electrically connected to each other without forming electrode patterns on a side surface of the submount as in the conventional technique (see FIG. 26 ).
  • FIG. 6 includes views showing a configuration of a semiconductor element of the embodiment.
  • FIG. 6A is a plan view of the semiconductor element.
  • FIG. 6B is a cross-sectional view taken along the cross-section line VIB-VIB of FIG. 6A .
  • gold bumps 106 are formed on a surface of the semiconductor element 104 .
  • the gold bumps 106 are encapsulated by a resin 108 on the semiconductor element 104 .
  • the gold bumps 106 are formed on the semiconductor element 104 by ball bonding.
  • the diameter of each gold bump 106 is preferably about 40 ⁇ m to 100 ⁇ m.
  • the gold bumps 106 have exposed side surfaces, and these surfaces are exposed due to cut surfaces formed by dicing. A method of manufacturing the encapsulated semiconductor element including dicing and the like is described later.
  • the exposed surfaces of the gold bumps 106 function as side surface electrodes of the encapsulated semiconductor element. Note that bumps other than the gold bumps such as platinum (Pt) bumps and copper (Cu) bumps can be used as the bumps.
  • a silicone resin, an epoxy resin, an acryl resin, or the like which have a thermosetting property or a UV curing property can be used as the resin 108 .
  • the resin 108 is provided to mechanically protect the semiconductor element 104 or to protect the semiconductor element 104 from environments such as moisture and heat. Considering the fact that the wire bonding involves heat treatment, a resin with sufficient hardness even in wire bonding (heating) needs to be used as the resin 108 .
  • FIGS. 7A to 7C are views showing steps of manufacturing the encapsulated semiconductor element of the embodiment.
  • the gold bumps 106 are formed on surface electrodes of a wafer 114 not subjected to dicing ( FIG. 7A ).
  • the resin 108 is applied to encapsulate the gold bumps 106 on the wafer 114 .
  • the resin 108 is evenly applied to the wafer 114 ( FIG. 7B ).
  • the resin is cured by heating, UV curing, or the like.
  • the wafer 114 is diced along dicing lines into individual semiconductor elements 104 . Cut surfaces of the gold bumps 106 are exposed by the dicing ( FIG. 7C ). The exposed surfaces of the gold bumps 106 function as the side surface electrodes of the encapsulated semiconductor element.
  • FIG. 8 shows a configuration of a module including the encapsulated semiconductor element of the embodiment.
  • FIG. 8A is a plan view of the module.
  • FIG. 8B is a cross-sectional view taken along the cross-section line VIIIB-VIIIB of FIG. 8A .
  • the module 109 includes a main substrate 110 , an IC 111 , the encapsulated semiconductor element (the semiconductor element 104 including the gold bumps 106 encapsulated by the resin 108 ), Au wires 112 , and gold bumps 113 .
  • the IC 111 is formed on the main substrate 110 .
  • the encapsulated semiconductor element is formed on the main substrate 110 .
  • a side surface of the encapsulate semiconductor element on which no gold bumps 106 are provided is bonded to the main substrate 110 .
  • the IC 111 and the side surface electrodes (i.e. the exposed cut surfaces of the gold bumps 106 ) of the encapsulated semiconductor element are connected by wire bonding using the Au wires 112 . It is found that the cut surface of the gold bumps 106 exposed by the dicing function as the side surface electrodes of the encapsulated semiconductor element.
  • types of wire bonding include ball bonding, wedge bonding, and the like, and wires other than the Au wires such as Pt wires, Cu wires, or Al wires can be used as the wires.
  • FIG. 9 is a view showing a configuration of a submount of the embodiment.
  • a resin 108 can be applied in such a way that gold bumps 107 are covered.
  • the submount 100 of the embodiment is different from that of [First Embodiment] in that the resin 108 is not applied over an entire substrate 101 . Since constitutional elements other than the resin 108 is the same as those of [First Embodiment], description thereof is omitted.
  • the semiconductor element 104 is not damaged in the curing of the resin. Moreover, the amount of resin to be applied can be reduced. Note that stress due to resin curing or expansion and shrinkage of the resin caused by temperature fluctuations or the like may damage the semiconductor element.
  • the submount 100 of the embodiment is manufactured by forming the gold bumps 107 on electrodes 103 , applying the resin 108 in such a way that the gold bumps 107 are covered, curing the applied resin 108 by heating, UV curing, or the like, and then performing dicing in such a way that cut surfaces of the gold bumps 107 are exposed.
  • the resin 108 has hardness sufficient to withstand the force of wire bonding.
  • FIG. 10 is a view showing a configuration of a submount of the embodiment. As shown in FIG. 10 , it is possible to apply a resin 108 in such a way that gold bumps 107 are covered, and to apply another resin 115 on a substrate 101 .
  • the submount 100 of the embodiment is different from that of [Third Embodiment] in that the submount 100 further includes the resin 115 . Since constitutional elements other than the resin 115 are the same as those of [Third Embodiment], description thereof is omitted.
  • the submount 100 of the embodiment is manufactured by forming the gold bumps 107 on electrodes 103 , applying the resin 108 in such away that the gold bumps 107 are covered, applying the resin 115 on the substrate 101 , curing the applied resin 115 by heating, UV curing, or the like, and then performing dicing in such a way that cut surfaces of the gold bumps 107 are exposed.
  • the resin 108 has hardness sufficient to withstand force of wire bonding
  • the resin 115 has hardness lower than that of the resin 108 .
  • the semiconductor element 104 may be damaged. However, in the embodiment, since the gold bumps 107 are protected by the hard resin 108 while the semiconductor element 104 is protected by the soft resin 115 , the semiconductor element 104 can be prevented from being damaged.
  • FIG. 11 is a view showing a configuration of an encapsulated semiconductor element of the embodiment.
  • a resin 108 can applied only to portions around gold bumps 106 on the semiconductor element 104 . Since, the embodiment is the same as [Second Embodiment] other than the configuration that the resin 108 is applied only to the portions around the gold bumps 106 , description is omitted.
  • the resin 108 is selectively applied. Selectively applying the resin can reduce portions of the semiconductor element covered with the resin.
  • the embodiment is effective in a case where the semiconductor element is negatively affected by the resin covering the semiconductor element.
  • the encapsulated semiconductor element of the embodiment is manufactured by forming the gold bumps 106 on a wafer, applying the resin 108 on the wafer in such a way that the gold bumps 106 are covered, curing the applied resin 108 by heating, UV curing, or the like, and dicing the wafer into individual semiconductor elements 104 in such a way that cut surfaces of the gold bumps 106 are exposed.
  • the resin 108 has hardness sufficient to withstand force of wire bonding.
  • FIG. 12 is a view showing a configuration of an encapsulated semiconductor element of the embodiment. As shown in FIG. 12 , it is possible to apply a resin 108 about gold bumps 106 and further apply another resin 115 on the semiconductor element 104 .
  • the semiconductor element of the embodiment is different from that of [Fifth Embodiment] in that the semiconductor element further includes the resin 115 .
  • the semiconductor element of the embodiment is manufactured by forming the gold bumps 106 on a wafer, applying the resin 108 on the wafer about the gold bumps 106 in such a way that the gold bumps 106 are covered, applying the resin 115 on the wafer, curing the applied resin 115 by heating, UV curing, or the like, and dicing the wafer into individual semiconductor elements 104 in such a way that cut surfaces of the gold bumps 106 are exposed.
  • the resin 108 has hardness sufficient to withstand the force of wire bonding
  • the resin 115 has hardness lower than that of the resin 108 .
  • the semiconductor element 104 may be damaged. However, in the embodiment, since the gold bumps 106 are protected by the hard resin 108 while the semiconductor element 104 is protected by the soft resin 115 , the semiconductor element 104 can be prevented from being damaged. Note that stress due to resin curing or expansion and shrinkage of the resin caused by temperature fluctuations or the like may damage the semiconductor element.
  • FIG. 13A is a plan view showing a configuration of the module of the embodiment
  • FIG. 13B is a cross-sectional view taken along the cross-section line XIIIB-XIIIB of FIG. 13A
  • the module 109 of the embodiment includes a main substrate 110 , electrodes 116 on the main substrate 110 , an IC 111 on the main substrate 110 , a submount 100 on the main substrate 110 , Au wires 112 connecting the IC 111 and the submount 100 , and gold bumps 113 on the IC 111 .
  • the submount 100 is mounted on the electrodes 116 .
  • gold bumps 107 of the submount 100 and the electrodes 116 are bonded to one another with an electrically-conductive adhesive and are thus electrically connected to one another.
  • electrical connections are achieved by bonding the gold bumps 107 and the electrodes 116 to one another with the electrically-conductive adhesive.
  • FIG. 14 is a cross-sectional view showing a configuration of another module of the embodiment. As shown in FIG. 14 , electrical connections may be achieved by inserting a spacer 118 between the submount 100 and the electrodes 116 and providing bumps 123 in a space formed by the spacer 118 .
  • FIG. 15A is a plan view showing a configuration of a module of the embodiment
  • FIG. 15B is a cross-sectional view taken along the cross-section line XVB-XVB of FIG. 15A
  • the module 109 of the embodiment includes a main substrate 110 , electrodes 116 on the main substrate 110 , an IC 111 on the main substrate 110 , a submount 100 on the main substrate 110 , Au wires 112 connecting the IC 111 and the submount 100 , and gold bumps 113 on the IC 111 .
  • a step is formed in the main substrate 110 by spot-facing, and an element mounting surface of the main substrate 110 has an upper surface and a lower surface.
  • the IC 111 is mounted on the upper surface of the main substrate 110
  • the submount 100 is mounted on the lower surface of the main substrate 110 .
  • the gold bumps 113 are provided on an IC substrate to connect the IC 111 and the submount 100 by using the Au wires 112 .
  • wiring of the Au wires 112 between the gold bumps 113 and the gold bumps 107 is short, and the inductance can be suppressed. Accordingly, it is possible to achieve high-speed lines in the module of the embodiment.
  • FIG. 16A is a plan view showing a configuration of a module of the embodiment
  • FIG. 16B is a cross-sectional view taken along the cross-section line XVIB-XVIB of FIG. 16A
  • the module 109 of the embodiment includes a main substrate 110 , electrodes 116 on the main substrate 110 , an IC 111 on the main substrate 110 , a spacer 118 on the IC 111 , a submount 100 on the spacer 118 , and gold bumps 113 , 117 .
  • the gold bumps 117 are in contact with exposed cut surfaces of gold bumps 107 included in the submount 100 .
  • the spacer 118 is installed between the IC 111 and the submount 100 .
  • the gold bumps 113 on the IC 111 and the gold bumps 117 come into contact with one another in a space formed by the spacer 118 .
  • the IC 111 and the submount 100 can be electrically connected to each other by this configuration.
  • each of the electrical connections between the IC 111 and the submount 100 is achieved by placing two gold bumps in a space formed by the spacer
  • the number of gold bumps placed in the space formed by the spacer to achieve the electrical connection may be any number of one or more.
  • the spacer is provided in such a way that the submount 100 and Au wires 112 subjected to wiring and extending out from pads do not come into contact with each other, and electrical connection is achieved by using any number of gold bumps provided in the space formed by the spacer.
  • FIG. 17A is a plan view showing a configuration of the module of the embodiment
  • FIG. 17B is a cross-sectional view taken along the cross-section line XVIIB-XVIIB of FIG. 17A
  • the module 109 of the embodiment includes a main substrate 110 , electrodes 116 on the main substrate 110 , an IC 111 on the main substrate 110 , the encapsulated semiconductor element on the main substrate 110 , Au wires 112 connecting the IC 111 and the encapsulated semiconductor elements to each other, and gold bumps 113 on the IC 111 .
  • the encapsulated semiconductor element is mounted on the electrodes 116 .
  • the electrodes 116 and gold bumps 106 of the encapsulated semiconductor element are bonded to one another by an electrically-conductive adhesive and are thus electrically connected to one another.
  • the electrical connection is achieved by bonding the gold bumps 106 and the electrodes 116 to one another with the electrically-conductive adhesive.
  • the electrical connection may be achieved by inserting a spacer between the encapsulated semiconductor and the electrodes 116 and providing bumps in a space formed by the spacer 118 .
  • FIG. 18A is a plan view showing a configuration of a module of the embodiment
  • FIG. 18B is a cross-sectional view taken along the cross-section line XVIIIB-XVIIIB of FIG. 18A
  • the module 109 of the embodiment includes a main substrate 110 , electrodes 116 on the main substrate 110 , an IC 111 on the main substrate 110 , an encapsulated semiconductor element on the main substrate 110 , Au wires 112 connecting the IC 111 and the encapsulated semiconductor element to each other, and gold bumps 113 on the IC 111 .
  • a step is formed in the main substrate 110 by spot-facing, and an element mounting surface of the main substrate 110 has an upper surface and a lower surface.
  • the IC 111 is mounted on the upper surface of the main substrate 110
  • the encapsulated semiconductor element is mounted on the lower surface of the main substrate 110 .
  • the gold bumps 113 are provided on the IC 111 to connect the IC 111 and the encapsulated semiconductor element to each other by using the Au wires 112 . Since exposed cut surfaces of the gold bumps 106 function as side surface electrodes of the encapsulated semiconductor element, the IC 111 and the encapsulated semiconductor element can be electrically connected to each other.
  • FIG. 19A is a plan view showing a configuration of a module of the embodiment
  • FIG. 19B is a cross-sectional view taken along the cross-section line XIXB-XIXB of FIG. 19A
  • the module 109 of the embodiment includes a main substrate 110 , electrodes 116 on the main substrate 110 , an IC 111 on the main substrate 110 , a spacer 118 on the main substrate 110 , an encapsulated semiconductor element on the spacer 118 , gold bumps 113 on the IC 111 , and gold bumps 117 .
  • the spacer 118 is installed between the main substrate 110 and the encapsulated semiconductor element, and the module 109 thereby has a space between the IC 111 and the encapsulated semiconductor element.
  • the gold bumps 113 on the IC 111 and the gold bumps 117 are configured to come into contact with one another in the space formed by the spacer 118 .
  • the IC 111 and the encapsulated semiconductor element can be electrically connected to each other by this configuration.
  • each of the electrical connections between the IC 111 and the encapsulated semiconductor element is achieved by employing a configuration in which two gold bumps are placed in a space formed by the spacer
  • the number of gold bumps placed in the space formed by the spacer to achieve the electrical connection may be any number of one or more.
  • FIG. 20 is a perspective view showing a configuration of an encapsulated semiconductor element of the embodiment.
  • the encapsulated semiconductor element of the embodiment includes a semiconductor element 104 , multiple gold bumps 106 on the semiconductor element 104 , and a resin 108 encapsulating the multiple gold bumps 106 on the semiconductor element 104 .
  • FIG. 21A is a plan view of a module including the encapsulated semiconductor element of the embodiment
  • FIG. 21B is a cross-sectional view taken along the cross-section line XXIB-XXIB of FIG. 21A
  • the encapsulated semiconductor element of the embodiment can be mounted on a circuit board 122 by using solder 121 like a CSP (Chip Size Package).
  • An electrically-conductive adhesive can be used instead of the solder 121 .
  • FIGS. 22A to 22C show steps of manufacturing the encapsulated semiconductor element of the embodiment.
  • the multiple gold bumps 106 are formed on surface electrodes of a wafer 114 not subjected to dicing ( FIG. 22A ). As shown in FIG. 22A , the gold bumps 106 are formed to be arranged in straight lines along an x-axis direction and a y-axis direction.
  • the resin 108 is applied to encapsulate the gold bumps 106 on the wafer 114 .
  • the resin 108 is evenly applied to the wafer 114 ( FIG. 22B ).
  • the resin is cured by heating, UV curing, or the like.
  • the wafer is diced along dicing lines into individual semiconductor elements 104 . Cut surfaces of the gold bumps 106 are exposed by the dicing ( FIG. 22C ). The exposed surfaces of the gold bumps 106 function as side surface electrodes of the encapsulated semiconductor element.
  • the encapsulated semiconductor element shown in FIG. 22C has 16 side surface electrodes and the 16 side surface electrodes are linearly arranged in the x direction or the y direction.
  • FIG. 23 is a perspective view showing a configuration of an encapsulated semiconductor element of the embodiment.
  • the encapsulated semiconductor element of the embodiment includes a semiconductor element 104 , multiple gold bumps 106 on the semiconductor element 104 , and a resin 108 encapsulating the multiple gold bumps 106 on the semiconductor element 104 .
  • FIG. 24A is a plan view of a module including the encapsulated semiconductor element of the embodiment
  • FIG. 24B is a cross-sectional view taken along the cross-section line XXIVB-XXIVB of FIG. 24A
  • the encapsulated semiconductor element of the embodiment can be mounted on a circuit board 122 by using solder 121 like a CSP (Chip Size Package).
  • An electrically-conductive adhesive can be used instead of the solder.
  • the encapsulated semiconductor element of the embodiment can be mounted on the main substrate in which a step is formed by spot-facing and an element mounting surface has an upper surface and a lower surface.
  • the IC is mounted on the upper surface of the main substrate, and the encapsulated semiconductor element is mounted on the lower surface of the main substrate.
  • One side surface of the encapsulated semiconductor element is fixed to the lower surface of the main substrate by a non-electrically-conductive adhesive, solder, an electrically-conductive adhesive, or the like.
  • the IC and cut surfaces of the gold bumps exposed on another side surface of the encapsulated semiconductor element are connected by wires.
  • FIGS. 25A to 25C are views showing steps of manufacturing the encapsulated semiconductor element of the embodiment.
  • the multiple gold bumps 106 are formed on surface electrodes of a wafer 114 not subjected to dicing ( FIG. 25A ). As shown in FIG. 25A , the gold bumps 106 are formed to be arranged in straight lines along a y-axis direction.
  • the resin 108 is applied to encapsulate the gold bumps 106 on the wafer 114 .
  • the resin 108 is evenly applied to the wafer 114 ( FIG. 25B ).
  • the resin is cured by heating, UV curing, or the like.
  • the wafer 114 is diced along dicing lines into individual semiconductor elements 104 . Cut surfaces of the gold bumps 106 are exposed by the dicing ( FIG. 25C ). The exposed surfaces of the gold bumps 106 function as side surface electrodes of the encapsulated semiconductor element.
  • the encapsulated semiconductor element shown in FIG. 25C has 12 side surface electrodes, and the 12 side surface electrodes are linearly arranged in the y direction.
  • FIGS. 28A and 28B are views showing a configuration of a submount of the embodiment.
  • the submount 200 of the embodiment includes a substrate 201 , electrodes 203 , a semiconductor element 204 , Au wires 205 , and gold bumps 206 and 207 .
  • the submount 200 of the embodiment is different from the submount of [Third Embodiment] of FIG. 9 in that a groove 213 is provided in the substrate 201 and the semiconductor element 204 is mounted in the groove 213 .
  • Constitutional elements other than the point that the groove 213 is formed and the point that the semiconductor element 204 is directly mounted on the substrate 201 are the same as those of [Third Embodiment]. Accordingly, description thereof is omitted.
  • the groove 213 of the embodiment is formed linearly in an arrangement direction of the gold bumps 207 arranged on a surface of the substrate 201 which faces forward in a y-axis direction, i.e. in an X direction of FIG. 28A .
  • FIG. 28C is a view showing a configuration of another submount of the embodiment.
  • a rectangular recess-shaped groove 214 having a longitudinal direction that is the same as the longitudinal direction (X direction) of the groove 213 of FIG. 28A is formed on the substrate 201 .
  • the semiconductor element 204 is mounted in the recess-shaped groove 214 .
  • FIGS. 29A to 29D are views showing an example of a method of wire bonding in the embodiment.
  • a method of wire bonding in the embodiment is shown below as an example.
  • FIG. 29A shows the substrate 201 before the wire bonding of the embodiment.
  • a first step spot-facing (cutting) is performed on the substrate 201 to form the groove 213 ( FIG. 29B ).
  • the semiconductor element 204 is mounted in the groove 213 ( FIG. 29C ).
  • the gold bumps 206 of the Au wires 205 are formed on pads of the semiconductor element 204 with a ball bonder, and the Au wires 205 are connected from the semiconductor element 204 to the electrodes 203 on the substrate 201 ( FIG. 29C ).
  • the gold bumps 207 are formed on the electrodes 203 and the Au wires 205 connected in the third step with the ball bonder ( FIG. 29D ).
  • the wire bonding can be performed in the steps described above.
  • the submount 200 of the embodiment is manufactured as follows. First, the gold bumps 207 are formed on the electrodes 203 by the aforementioned wire bonding method in the embodiment. After the gold bumps 207 are formed on the electrodes 203 , a resin 208 is applied in such a way that the gold bumps 207 are covered. Then, the applied resin 208 is cured by heating, UV curing, or the like. Thereafter, dicing is performed in such a way that cut surfaces of the gold bumps 207 are exposed. Here, the resin 208 has hardness sufficient to withstand the force of wire bonding. Note that the wire bonding method in the embodiment can be applied to the other embodiments described above.
  • the semiconductor element 204 can be prevented from being damaged during resin curing. Moreover, the amount of resin to be applied can be reduced. Note that stress due to resin curing or expansion and shrinkage of the resin caused by temperature fluctuations or the like may damage the semiconductor element.
  • mounting the semiconductor element 204 in the groove 213 on the substrate 201 can reduce the distance between the semiconductor element 204 and the surface of the substrate 201 compared to that in a submount in which no spot-facing portion is formed in the substrate 201 .
  • the length of wire bonding is thus reduced and lines of higher speed can be achieved.
  • FIG. 30 is a view showing a configuration of a submount of the embodiment. As shown in FIG. 30 , it is possible to apply a resin 208 in such a way that gold bumps 207 are covered, and then apply another resin 215 on a substrate 201 .
  • the submount 300 of the embodiment is different from the submount of [Fifteenth Embodiment] in that the submount 300 further includes the resin 215 . Since constitutional elements other than the resin 215 are the same as those of [Fifteenth Embodiment], description thereof is omitted.
  • the submount 300 of the embodiment is manufactured as follows. First, the gold bumps 207 are formed on electrodes 203 by the wire bonding method of the fifteenth embodiment. After the gold bumps 207 are formed on the electrodes 203 , the resin 208 is applied in such a way that the gold bumps 207 are covered. After the application of the resin 208 , the resin 215 is applied onto the substrate 201 . Then, the applied resin 215 is cured by heating, UV curing, or the like. Thereafter, dicing is performed in such a way that cut surfaces of the gold bumps 207 are exposed. Here, the resin 208 has hardness sufficient to withstand the force of wire bonding, and the resin 215 has hardness lower than that of the resin 208 .
  • the semiconductor element 204 may be damaged. However, in the embodiment, since the gold bumps 207 are protected by the hard resin 208 while the semiconductor element 204 is protected by the soft resin 215 , the semiconductor element 204 can be prevented from being damaged.
  • a drive IC or an optical element such as a laser diode are examples of the semiconductor element in all of the embodiments described above.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Led Device Packages (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The present invention provides a submount which includes a semiconductor element and which can be easily connected to an IC on a main substrate. The submount in one embodiment of the present invention includes: a substrate; electrodes; the semiconductor element; Au wires; and gold bumps. The electrodes, the semiconductor element, the Au wires, and the gold bumps are encapsulated on the substrate by a resin. The gold bumps are formed on the electrodes and the Au wires by ball bonding and are cut by dicing such that side surfaces of the gold bumps are exposed. The exposed surfaces function as side surface electrodes of the submount.

Description

    TECHNICAL FIELD
  • The present invention relates to a submount, an encapsulated semiconductor element, and methods for manufacturing the same.
    • BACKGROUND ART
  • Conventionally, in some semiconductor modules in which submounts are packaged, electrodes are formed not only on an element mounting surface of the submount but also on a side surface portion of the submount.
  • Examples of conventional techniques include a module like one shown in FIG. 26. This module 109 includes a main substrate 110, an IC 111 on the main substrate 110, and a submount 100 on the main substrate 110. The submount 100 includes a semiconductor element 104 on an element mounting surface.
  • In the module shown in FIG. 26, a through-hole electrode and an element mounting electrode are formed as an electrode 102 in the submount 100. An electrical connection between the IC 111 and the semiconductor element 104 is achieved by connecting the IC 111 and the electrode 102 by an AU wire 112.
  • However, in the module shown in FIG. 26, the electrode 102 is formed over two surfaces of a substrate 101 and an electrode area is large. Accordingly, a parasitic capacitance is large. Furthermore, the module shown in FIG. 26 also includes a through-hole land portion and inevitably has a large pitch, so that there is a problem that a high-density submount cannot be manufactured.
    • CITATION LIST Patent Literature
    • PTL 1: Japanese Patent Laid-Open No. H09-051053 (1997)
    SUMMARY OF INVENTION
  • The present invention has been made in view of the problems described above. An object of the present invention is to provide a high-density submount which has small parasitic capacitance and which does not require formation of a new electrode on a side surface of the submount when electrically connecting an IC and the submount to each other on a substrate.
  • Moreover, another object of the present invention is to provide an encapsulated semiconductor element which does not require formation of a new electrode on a side surface of the encapsulated semiconductor element when electrically connecting an IC and the encapsulated semiconductor element to each other on a substrate.
  • The present invention provides a submount characterized in that the submount comprises: a substrate; an electrode on the substrate; a semiconductor element on the substrate; a wire connecting the semiconductor element and the electrode to each other; and one or plurality of bumps on the electrode and the wire, the electrode, the semiconductor element, the wire, and the one or plurality of bumps are encapsulated on the substrate by a resin, the one or plurality of bumps have a cut surface, the cut surface is exposed on a surface of the submount, and the cut surface is an electrode of the submount.
  • The present invention provides a submount characterized in that the submount comprises: a substrate; an electrode on the substrate; a semiconductor element on the substrate; a wire connecting the semiconductor element and the electrode to each other; and a bump on the electrode and the wire, the bump is encapsulated by a first resin which is locally applied on the substrate, the bump has an exposed cut surface, and the exposed cut surface is an electrode of the submount.
  • In one embodiment of the present invention, the submount is characterized in that the submount further comprises a second resin encapsulating the electrode, the semiconductor element, the wire, the bump, and the first resin, and the first resin is harder than the second resin. Furthermore, in one embodiment of the present invention, the submount is characterized in that a groove is formed on the substrate and the semiconductor element is mounted in the groove.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; an electrode on the main substrate; a wire connecting the IC and the electrode to each other; and the submount on the electrode on the main substrate, and the exposed cut surface of the bump of the submount and the electrode on the main substrate are bonded to each other by an electrically-conductive adhesive.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; and the submount on the main substrate, the main substrate has an upper surface and a lower surface as element mounting surfaces, the IC is mounted on the upper surface and the submount is mounted on the lower surface, and the module further comprises a wire for wire bonding the IC and the submount to each other.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; a spacer on the IC; and the submount on the spacer, and an electrical connection between the IC and the one or plurality of bumps included in the submount is achieved by one or plurality of bumps placed in a space formed by the spacer.
  • The present invention provides an encapsulated semiconductor element characterized in that the encapsulated semiconductor element comprises: a semiconductor element; and a bump on the semiconductor element, the bump is encapsulated on the semiconductor element by a resin, the bump has an exposed cut surface, and the exposed cut surface is an electrode of the encapsulated semiconductor element.
  • The present invention provides an encapsulated semiconductor element characterized in that the encapsulated semiconductor element comprises: a semiconductor element; and a bump on the semiconductor element, the bump is encapsulated by a first resin applied only to a portion around the bump on the semiconductor element, the bump has an exposed cut surface, and the exposed cut surface is an electrode of the encapsulated semiconductor element.
  • In one embodiment of the present invention, the encapsulated semiconductor element is characterized in that the encapsulated semiconductor element further comprises a second resin encapsulating the semiconductor element, the bump, and the first resin, and the first resin is harder than the second resin.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; an electrode on the main substrate; a wire connecting the IC and the electrode to each other; and the encapsulated semiconductor element on the electrode on the main substrate, and the exposed cut surface of the bump of the encapsulated semiconductor element and the electrode on the main substrate are bonded to each other by an electrically-conductive adhesive.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; and the encapsulated semiconductor element on the main substrate, the main substrate has an upper surface and a lower surface as element mounting surfaces, the IC is mounted on the upper surface and the encapsulated semiconductor element is mounted on the lower surface, and the module further comprises: a wire for wire bonding the IC and the encapsulated semiconductor element to each other; and a bump on the wire and the bump included in the encapsulated semiconductor element.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a main substrate; an IC on the main substrate; a spacer on the main substrate; and the encapsulated semiconductor element on the spacer, an electrical connection between the IC and the bump included in the encapsulated semiconductor element is achieved by one or plurality of bumps placed in a space formed by the spacer.
  • One embodiment of the present invention provides a module characterized in that the module comprises: a circuit board; and the encapsulated semiconductor element, and the circuit board and the encapsulated semiconductor element are electrically connected to each other by soldering the exposed cut surface of the bump of the encapsulated semiconductor element.
  • The present invention is characterized in that the invention comprises the steps of: connecting a semiconductor element and an electrode on a substrate by wire bonding using a wire; forming one or plurality of bumps on the electrode and the wire by ball bonding; encapsulating the semiconductor element, the electrode, the wire, and the bump on the substrate by a resin; curing the resin; and dicing the substrate, the electrode, the one or plurality of bumps, and the resin along a dicing line. Furthermore, the present invention is characterized that the invention comprises the step of forming a groove on the substrate and mounting the semiconductor element in the groove.
  • The present invention is characterized in that the invention comprises the steps of forming a bump on a wafer by ball bonding; encapsulating the bump on the wafer by a resin; curing the resin; and dicing the wafer, the bump, and the resin along a dicing line.
  • According to the present invention, an IC and a fine element on a substrate can be efficiently electrically connected to each other.
  • Specifically, in the electrode of the submount in the present invention, the electrode area can be made smaller than that in conventional techniques, and this contributes to reduction of parasitic capacitance.
  • Moreover, although the conventional submount described above is a two-layer substrate, the submount is a single-layer substrate in the invention of this application. Accordingly, the submount can be manufactured at a lower cost.
  • Furthermore, in the electrode of the submount in the present invention, a fine pattern for electrode formation can be formed. Since the density of the pattern can be increased, the present invention is suitable for high-density application.
    • BRIEF DESCRIPTION OF DRAWINGS
  • FIG. 1A is a plan view showing a configuration of a submount in a first embodiment of the present invention;
  • FIG. 1B is a cross-sectional view taken along the cross-section line IB-IB of FIG. 1A;
  • FIG. 2 is a cross-sectional view showing a configuration of a submount in the first embodiment of the present invention;
  • FIG. 3A is a view showing a step of manufacturing the submount in the first embodiment of the present invention;
  • FIG. 3B is a view showing a step of manufacturing the submount in the first embodiment of the present invention;
  • FIG. 3C is a view showing a step of manufacturing the submount in the first embodiment of the present invention;
  • FIG. 3D is a view showing a step of manufacturing the submount in the first embodiment of the present invention;
  • FIG. 4A is a plan view showing a configuration of a module including the submount in the first embodiment of the present invention;
  • FIG. 4B is a cross-sectional view taken along the cross-section line IVB-IVB of FIG. 4A;
  • FIG. 5A is a plan view showing a configuration of a module including the submount in the first embodiment of the present invention;
  • FIG. 5B is a cross-sectional view taken along the cross-section line VB-VB of FIG. 5A;
  • FIG. 6A is a plan view showing a configuration of an encapsulated semiconductor element in a second embodiment of the present invention;
  • FIG. 6B is a cross-sectional view taken along the cross-section line VIB-VIB of FIG. 6A;
  • FIG. 7A is a view showing a step of manufacturing the encapsulated semiconductor element in the second embodiment of the present invention;
  • FIG. 7B is a view showing a step of manufacturing the encapsulated semiconductor element in the second embodiment of the present invention;
  • FIG. 7C is a view showing a step of manufacturing the encapsulated semiconductor element in the second embodiment of the present invention;
  • FIG. 8A is a plan view showing a configuration of a module including the encapsulated semiconductor element in the second embodiment of the present invention;
  • FIG. 8B is a cross-sectional view taken along the cross-section line VIIIB-VIIIB of FIG. 8A;
  • FIG. 9 is a view showing a configuration of a submount in a third embodiment of the present invention;
  • FIG. 10 is a view showing a configuration of a submount in a fourth embodiment of the present invention;
  • FIG. 11 is a view showing a configuration of an encapsulated semiconductor element in a fifth embodiment of the present invention;
  • FIG. 12 is a view showing a configuration of an encapsulated semiconductor element in a sixth embodiment of the present invention;
  • FIG. 13A is a plan view showing a configuration of a module in a seventh embodiment of the present invention.
  • FIG. 13B is a cross-sectional view taken along the cross-section line XIIIB-XIIIB of FIG. 13A;
  • FIG. 14 is a cross-sectional view showing a configuration of another module in the seventh embodiment of the present invention;
  • FIG. 15A is a plan view showing a configuration of a module in an eighth embodiment of the present invention.
  • FIG. 15B is a cross-sectional view taken along the cross-section line XVB-XVB of FIG. 15A;
  • FIG. 16A is a plan view showing a configuration of a module in a ninth embodiment of the present invention.
  • FIG. 16B is a cross-sectional view taken along the cross-section line XVIB-XVIB of FIG. 16A;
  • FIG. 17A is a plan view showing a configuration of a module in a tenth embodiment of the present invention.
  • FIG. 17B is a cross-sectional view taken along the cross-section line XVIIB-XVIIB of FIG. 17A;
  • FIG. 18A is a plan view showing a configuration of a module in an eleventh embodiment of the present invention;
  • FIG. 18B is a cross-sectional view taken along the cross-section line XVIIIB-XVIIIB of FIG. 18A;
  • FIG. 19A is a plan view showing a configuration of a module in a twelfth embodiment of the present invention.
  • FIG. 19B is a cross-sectional view taken along the cross-section line XIXB-XIXB of FIG. 19A;
  • FIG. 20 is a perspective view showing a configuration of an encapsulated semiconductor element in a thirteenth embodiment of the present invention;
  • FIG. 21A is a plan view showing a configuration of a module including the encapsulated semiconductor element in the thirteenth embodiment of the present invention;
  • FIG. 21B is a cross-sectional view taken along the cross-section line XXIB-XXIB of FIG. 21A;
  • FIG. 22A is a view showing a step of manufacturing the encapsulated semiconductor element in the thirteenth embodiment of the present invention;
  • FIG. 22B is a view showing a step of manufacturing the encapsulated semiconductor element in the thirteenth embodiment of the present invention;
  • FIG. 22C is a view showing a step of manufacturing the encapsulated semiconductor element in the thirteenth embodiment of the present invention;
  • FIG. 23 is a perspective view showing a configuration of an encapsulated semiconductor element in a fourteenth embodiment of the present invention;
  • FIG. 24A is a plan view showing a configuration of a module including the encapsulated semiconductor element in the fourteenth embodiment of the present invention;
  • FIG. 24B is a cross-sectional view taken along the cross-section line XXIVB-XXIVB of FIG. 24A;
  • FIG. 25A is a view showing a step of manufacturing the encapsulated semiconductor element in the fourteenth embodiment of the present invention;
  • FIG. 25B is a view showing a step of manufacturing the encapsulated semiconductor element in the fourteenth embodiment of the present invention;
  • FIG. 25C is a view showing a step of manufacturing the encapsulated semiconductor element in the fourteenth embodiment of the present invention;
  • FIG. 26 is a view showing a configuration of a module including a submount of a conventional technique;
  • FIG. 27A is a view showing a method of wire bonding in the first embodiment of the present invention;
  • FIG. 27B is a view showing another method of wire bonding in the first embodiment of the present invention;
  • FIG. 28A is a perspective view showing a configuration of a submount in a fifteenth embodiment of the present invention;
  • FIG. 28B is a view showing the configuration of the submount in the fifteenth embodiment of the present invention;
  • FIG. 28C is a view showing a configuration of another submount in the fifteenth embodiment of the present invention;
  • FIG. 29A is a view showing a step of wire bonding in the fifteenth embodiment of the present invention;
  • FIG. 29B is a view showing a step of wire bonding in the fifteenth embodiment of the present invention;
  • FIG. 29C is a view showing a step of wire bonding in the fifteenth embodiment of the present invention;
  • FIG. 29D is a view showing a step of wire bonding in the fifteenth embodiment of the present invention; and
  • FIG. 30 is a view showing a configuration of a submount in a sixteenth embodiment of the present invention.
    •  DESCRIPTION OF EMBODIMENTS
  • Embodiments of the present invention are described below with reference to the drawings.
    • First Embodiment
  • FIG. 1 includes views showing a configuration of a submount of the embodiment. FIG. 1A is a plan view of the submount. FIG. 1B is a cross-sectional view taken along the cross-section line IB-IB of FIG. 1A. For the sake of description, an upper portion of FIG. 1A is a plan view in which a resin 108 is not illustrated and a lower portion of FIG. 1A is a plan view in which the resin 108 is illustrated. Note that there are other plan views of this application which are illustrated in a similar way.
  • As shown in FIG. 1, the submount 100 includes a substrate 101, electrodes 102, 103, a semiconductor element 104, Au wires 105, and gold bumps 106, 107. The electrodes 102, 103, the semiconductor element 104, the Au wires 105, and the gold bumps 106, 107 are encapsulated on the substrate 101 by the resin 108.
  • A rigid substrate such as a glass epoxy substrate, a paper phenol substrate, a paper epoxy substrate, a glass composite substrate, a Teflon (registered trademark) substrate, an alumina substrate, a silicon interposer substrate, or a LTCC substrate as well as a flexible substrate can be used as the substrate 101.
  • The electrodes are patterned on the substrate. In the embodiment, as shown in FIG. 1, there are patterned the electrode 102 on which the semiconductor element 104 is formed and the multiple electrodes 103 arranged in a straight line on which the gold bumps 107 are formed respectively. Cu can be used as an electrode material. Cu plated by Ni/Au is used as the electrodes. Note that Ag, Au, and the like can be also used as the electrode material. Moreover, Ni/Pd/Au plating, Ni/B plating, Ni/P plating, Ag plating, Pd/Ni plating, Pd plating, Ti/Pd/Au plating, Ti/Pt/Au plating, Ti/Pd/Cu/Ni/Au plating, and the like can be also used as the plating.
  • As shown in FIG. 1A, circuit patterns such as electrodes are formed on a surface of the semiconductor element. Although the semiconductor element 104 of the embodiment is formed on the electrode 102, it is not necessary to form the semiconductor element on the electrode. The semiconductor element can be formed anywhere on the substrate of the submount.
  • The semiconductor element 104 and the electrodes 103 are connected by wire bonding using the Au wires 105. Note that types of wire bonding include ball bonding, wedge bonding, and the like, and wires other than the Au wires such as Pt wires, Cu wires, or Al wires can be used as the wires.
  • Examples of a method of wire bonding are shown in FIGS. 27A and 27B. For example, wire bonding can be achieved by performing (1) step of forming the gold bumps 106 of the Au wires 105 on pads of the semiconductor element 104 by a ball bonder (1st bonding), (2) step of connecting the Au wires 105 to the electrodes 103 on the substrate 101 without cutting the Au wires (2nd bonding), and (3) step of forming the gold bumps 107 on the electrodes 103 and the Au wires 105 connected in the 2nd bonding (see FIG. 27A).
  • In another example, wire bonding can be achieved by performing (1) step of forming the gold bumps 106 of wires on the pads of the semiconductor element 104 and cutting the wires by the ball bonder, (2) step of forming the gold bumps 107 on the electrodes 103 (1st bonding) and connecting the Au wires 105 to the gold bumps 106 without cutting the Au wires (2nd bonding) (see FIG. 27B). In the embodiment, the wire bonding is achieved by using one of these two methods.
  • The gold bumps 107 are formed on the electrodes 103 and the Au wires 105 by ball bonding. The diameter of each gold bump 107 is 20 μm to 200 μm, preferably 40 μm to 100 μm. As shown in FIG. 1B, the gold bumps 107 have surfaces exposed on a module side surface. These surfaces are exposed due to cut surfaces formed by dicing. A method of manufacturing the submount including dicing and the like is described later. The exposed surfaces of the gold bumps 107 function as side surface electrodes of the submount 100. Note that bumps other than the gold bumps such as platinum (Pt) bumps and copper (Cu) bumps can be used as the bumps.
  • The resin 108 encapsulates the electrodes 102, 103, the semiconductor element 104, the Au wires 105, and the gold bumps 106, 107 on the substrate 101. A silicone resin, an epoxy resin, an acryl resin, or the like which have a thermosetting property or a UV curing property can be used as the resin 108. The resin 108 is provided to mechanically protect the semiconductor element 104 or to protect the semiconductor element 104 from environments such as moisture and heat. Considering the fact that the wire bonding is often performed together with heat treatment, a resin with sufficient hardness even in heating is preferably used as the resin 108.
  • FIG. 2 is a cross-sectional view showing a configuration of another submount of the embodiment. Although FIG. 1 shows a configuration in which the exposed surface of one gold bump 107 is used as each of the side surface electrodes of the submount, as shown in FIG. 2, exposed surfaces of multiple bumps may be used as each of the side surface electrodes of the submount.
  • FIGS. 3A to 3D are views showing steps of manufacturing the submount of the embodiment.
  • First, the semiconductor element 104 and the electrodes 103 are connected by wire bonding using the Au wires 105 (FIG. 3A).
  • Next, the gold bumps 107 are formed on the electrodes 103 and the Au wires 105 (FIG. 3B).
  • Then, the resin 108 is applied to encapsulate the electrodes 102, 103, the semiconductor element 104, the Au wires 105, and the gold bumps 106, 107 on the substrate 101. The resin 108 is applied onto the substrate 101 (FIG. 3C). After the application of the resin, the resin is cured by heating, UV curing, or the like.
  • Lastly, dicing is performed along dicing lines to expose cut surfaces of the gold bumps 107 (FIG. 3D). The exposed surfaces of the gold bumps 107 function as the side surface electrodes of the submount 100.
  • FIG. 4 shows a configuration of a module including the submount of the embodiment. FIG. 4A is a plan view of the module. FIG. 4B is a cross-sectional view taken along the cross-section line IVB-IVB of FIG. 4A.
  • The module 109 includes a main substrate 110, an IC 111, the submount 100, Au wires 112, and gold bumps 113.
  • The IC 111 is formed on the main substrate 110.
  • The submount 100 is formed on the main substrate 110. A side surface of the submount 100 on which no gold bumps 107 are provided is bonded to the main substrate 110 by an adhesive or the like.
  • The IC 111 and the side surface electrodes (i.e. the exposed cut surfaces of the gold bumps 107) of the submount 100 are connected by wire bonding using the Au wires 112. It is found that the cut surface of the gold bumps 107 exposed by the dicing function as the side surface electrodes of the submount 100.
  • FIG. 5 shows another configuration of a module including the submount of the embodiment. FIG. 5A is a plan view of the module. FIG. 5B is a cross-sectional view taken along the cross-section line VB-VB of FIG. 5A.
  • The module 109 includes the main substrate 110, the IC 111, the submount 100, pattern electrodes 116 on the main substrate 110, bumps 123, a spacer 118, and electrical connections 120.
  • The submount 100 and the IC 111 bonded to the main substrate 110 as in BGA can be electrically connected to each other by the configuration shown in FIG. 5.
  • The submount 100 is formed on the main substrate 110. A side surface of the submount 100 on which the gold bumps 107 are provided is arranged to face downward and is connected to the electrodes 116 via the electrical connections 120.
  • The electrical connections 120 between the gold bumps 107 and the electrodes 116 can be achieved by gold bumps or an electrically-conductive adhesive.
  • Electrical connections between the IC 111 and the electrodes 116 are formed by using the bumps 123 such as solder balls or the like.
  • In the embodiment, the IC 111 and the submount 100 can be electrically connected to each other without forming electrode patterns on a side surface of the submount as in the conventional technique (see FIG. 26).
    • Second Embodiment
  • FIG. 6 includes views showing a configuration of a semiconductor element of the embodiment. FIG. 6A is a plan view of the semiconductor element. FIG. 6B is a cross-sectional view taken along the cross-section line VIB-VIB of FIG. 6A.
  • As shown in FIG. 6, gold bumps 106 are formed on a surface of the semiconductor element 104. The gold bumps 106 are encapsulated by a resin 108 on the semiconductor element 104.
  • The gold bumps 106 are formed on the semiconductor element 104 by ball bonding. The diameter of each gold bump 106 is preferably about 40 μm to 100 μm. As shown in FIG. 6B, the gold bumps 106 have exposed side surfaces, and these surfaces are exposed due to cut surfaces formed by dicing. A method of manufacturing the encapsulated semiconductor element including dicing and the like is described later. The exposed surfaces of the gold bumps 106 function as side surface electrodes of the encapsulated semiconductor element. Note that bumps other than the gold bumps such as platinum (Pt) bumps and copper (Cu) bumps can be used as the bumps.
  • A silicone resin, an epoxy resin, an acryl resin, or the like which have a thermosetting property or a UV curing property can be used as the resin 108. The resin 108 is provided to mechanically protect the semiconductor element 104 or to protect the semiconductor element 104 from environments such as moisture and heat. Considering the fact that the wire bonding involves heat treatment, a resin with sufficient hardness even in wire bonding (heating) needs to be used as the resin 108.
  • FIGS. 7A to 7C are views showing steps of manufacturing the encapsulated semiconductor element of the embodiment.
  • First, the gold bumps 106 are formed on surface electrodes of a wafer 114 not subjected to dicing (FIG. 7A).
  • Next, the resin 108 is applied to encapsulate the gold bumps 106 on the wafer 114. The resin 108 is evenly applied to the wafer 114 (FIG. 7B). After the application of the resin, the resin is cured by heating, UV curing, or the like.
  • Lastly, the wafer 114 is diced along dicing lines into individual semiconductor elements 104. Cut surfaces of the gold bumps 106 are exposed by the dicing (FIG. 7C). The exposed surfaces of the gold bumps 106 function as the side surface electrodes of the encapsulated semiconductor element.
  • FIG. 8 shows a configuration of a module including the encapsulated semiconductor element of the embodiment. FIG. 8A is a plan view of the module. FIG. 8B is a cross-sectional view taken along the cross-section line VIIIB-VIIIB of FIG. 8A.
  • The module 109 includes a main substrate 110, an IC 111, the encapsulated semiconductor element (the semiconductor element 104 including the gold bumps 106 encapsulated by the resin 108), Au wires 112, and gold bumps 113.
  • The IC 111 is formed on the main substrate 110.
  • The encapsulated semiconductor element is formed on the main substrate 110. A side surface of the encapsulate semiconductor element on which no gold bumps 106 are provided is bonded to the main substrate 110.
  • The IC 111 and the side surface electrodes (i.e. the exposed cut surfaces of the gold bumps 106) of the encapsulated semiconductor element are connected by wire bonding using the Au wires 112. It is found that the cut surface of the gold bumps 106 exposed by the dicing function as the side surface electrodes of the encapsulated semiconductor element. Note that types of wire bonding include ball bonding, wedge bonding, and the like, and wires other than the Au wires such as Pt wires, Cu wires, or Al wires can be used as the wires.
  • In [First Embodiment] and [Second Embodiment] described above, one type of resin is applied onto the substrate or the semiconductor element. However, other variations of encapsulation by resin application exist, and these variations are described in the following embodiments.
    • Third Embodiment
  • FIG. 9 is a view showing a configuration of a submount of the embodiment. As shown in FIG. 9, a resin 108 can be applied in such a way that gold bumps 107 are covered. The submount 100 of the embodiment is different from that of [First Embodiment] in that the resin 108 is not applied over an entire substrate 101. Since constitutional elements other than the resin 108 is the same as those of [First Embodiment], description thereof is omitted.
  • In the embodiment, the semiconductor element 104 is not damaged in the curing of the resin. Moreover, the amount of resin to be applied can be reduced. Note that stress due to resin curing or expansion and shrinkage of the resin caused by temperature fluctuations or the like may damage the semiconductor element.
  • The submount 100 of the embodiment is manufactured by forming the gold bumps 107 on electrodes 103, applying the resin 108 in such a way that the gold bumps 107 are covered, curing the applied resin 108 by heating, UV curing, or the like, and then performing dicing in such a way that cut surfaces of the gold bumps 107 are exposed. Here, the resin 108 has hardness sufficient to withstand the force of wire bonding.
    • Fourth Embodiment
  • FIG. 10 is a view showing a configuration of a submount of the embodiment. As shown in FIG. 10, it is possible to apply a resin 108 in such a way that gold bumps 107 are covered, and to apply another resin 115 on a substrate 101. The submount 100 of the embodiment is different from that of [Third Embodiment] in that the submount 100 further includes the resin 115. Since constitutional elements other than the resin 115 are the same as those of [Third Embodiment], description thereof is omitted.
  • The submount 100 of the embodiment is manufactured by forming the gold bumps 107 on electrodes 103, applying the resin 108 in such away that the gold bumps 107 are covered, applying the resin 115 on the substrate 101, curing the applied resin 115 by heating, UV curing, or the like, and then performing dicing in such a way that cut surfaces of the gold bumps 107 are exposed. Here, the resin 108 has hardness sufficient to withstand force of wire bonding, and the resin 115 has hardness lower than that of the resin 108.
  • If the hardness of the resin is too high, the semiconductor element 104 may be damaged. However, in the embodiment, since the gold bumps 107 are protected by the hard resin 108 while the semiconductor element 104 is protected by the soft resin 115, the semiconductor element 104 can be prevented from being damaged.
    • Fifth Embodiment
  • FIG. 11 is a view showing a configuration of an encapsulated semiconductor element of the embodiment. As shown in FIG. 11, a resin 108 can applied only to portions around gold bumps 106 on the semiconductor element 104. Since, the embodiment is the same as [Second Embodiment] other than the configuration that the resin 108 is applied only to the portions around the gold bumps 106, description is omitted.
  • In the embodiment, the resin 108 is selectively applied. Selectively applying the resin can reduce portions of the semiconductor element covered with the resin. The embodiment is effective in a case where the semiconductor element is negatively affected by the resin covering the semiconductor element.
  • The encapsulated semiconductor element of the embodiment is manufactured by forming the gold bumps 106 on a wafer, applying the resin 108 on the wafer in such a way that the gold bumps 106 are covered, curing the applied resin 108 by heating, UV curing, or the like, and dicing the wafer into individual semiconductor elements 104 in such a way that cut surfaces of the gold bumps 106 are exposed. Here, the resin 108 has hardness sufficient to withstand force of wire bonding.
    • Sixth Embodiment
  • FIG. 12 is a view showing a configuration of an encapsulated semiconductor element of the embodiment. As shown in FIG. 12, it is possible to apply a resin 108 about gold bumps 106 and further apply another resin 115 on the semiconductor element 104. The semiconductor element of the embodiment is different from that of [Fifth Embodiment] in that the semiconductor element further includes the resin 115.
  • The semiconductor element of the embodiment is manufactured by forming the gold bumps 106 on a wafer, applying the resin 108 on the wafer about the gold bumps 106 in such a way that the gold bumps 106 are covered, applying the resin 115 on the wafer, curing the applied resin 115 by heating, UV curing, or the like, and dicing the wafer into individual semiconductor elements 104 in such a way that cut surfaces of the gold bumps 106 are exposed. Here, the resin 108 has hardness sufficient to withstand the force of wire bonding, and the resin 115 has hardness lower than that of the resin 108.
  • If the hardness of the resin covering the semiconductor element 104 is too high, the semiconductor element 104 may be damaged. However, in the embodiment, since the gold bumps 106 are protected by the hard resin 108 while the semiconductor element 104 is protected by the soft resin 115, the semiconductor element 104 can be prevented from being damaged. Note that stress due to resin curing or expansion and shrinkage of the resin caused by temperature fluctuations or the like may damage the semiconductor element.
    • Seventh Embodiment
  • Description is given below of a variation of a module on which the submount of [Fourth Embodiment] described above is mounted.
  • FIG. 13A is a plan view showing a configuration of the module of the embodiment, and FIG. 13B is a cross-sectional view taken along the cross-section line XIIIB-XIIIB of FIG. 13A. As shown in FIGS. 13A and 13B, the module 109 of the embodiment includes a main substrate 110, electrodes 116 on the main substrate 110, an IC 111 on the main substrate 110, a submount 100 on the main substrate 110, Au wires 112 connecting the IC 111 and the submount 100, and gold bumps 113 on the IC 111.
  • The submount 100 is mounted on the electrodes 116. In this case, gold bumps 107 of the submount 100 and the electrodes 116 are bonded to one another with an electrically-conductive adhesive and are thus electrically connected to one another. In the structure shown in FIG. 13, electrical connections are achieved by bonding the gold bumps 107 and the electrodes 116 to one another with the electrically-conductive adhesive.
  • FIG. 14 is a cross-sectional view showing a configuration of another module of the embodiment. As shown in FIG. 14, electrical connections may be achieved by inserting a spacer 118 between the submount 100 and the electrodes 116 and providing bumps 123 in a space formed by the spacer 118.
    • Eighth Embodiment
  • FIG. 15A is a plan view showing a configuration of a module of the embodiment, and FIG. 15B is a cross-sectional view taken along the cross-section line XVB-XVB of FIG. 15A. As shown in FIGS. 15A and 15B, the module 109 of the embodiment includes a main substrate 110, electrodes 116 on the main substrate 110, an IC 111 on the main substrate 110, a submount 100 on the main substrate 110, Au wires 112 connecting the IC 111 and the submount 100, and gold bumps 113 on the IC 111.
  • As shown in FIG. 15B, a step is formed in the main substrate 110 by spot-facing, and an element mounting surface of the main substrate 110 has an upper surface and a lower surface. The IC 111 is mounted on the upper surface of the main substrate 110, and the submount 100 is mounted on the lower surface of the main substrate 110.
  • The gold bumps 113 are provided on an IC substrate to connect the IC 111 and the submount 100 by using the Au wires 112.
  • In the embodiment, wiring of the Au wires 112 between the gold bumps 113 and the gold bumps 107 is short, and the inductance can be suppressed. Accordingly, it is possible to achieve high-speed lines in the module of the embodiment.
    • Ninth Embodiment
  • FIG. 16A is a plan view showing a configuration of a module of the embodiment, and FIG. 16B is a cross-sectional view taken along the cross-section line XVIB-XVIB of FIG. 16A. As shown in FIGS. 16A and 16B, the module 109 of the embodiment includes a main substrate 110, electrodes 116 on the main substrate 110, an IC 111 on the main substrate 110, a spacer 118 on the IC 111, a submount 100 on the spacer 118, and gold bumps 113, 117. The gold bumps 117 are in contact with exposed cut surfaces of gold bumps 107 included in the submount 100.
  • The spacer 118 is installed between the IC 111 and the submount 100. The gold bumps 113 on the IC 111 and the gold bumps 117 come into contact with one another in a space formed by the spacer 118. The IC 111 and the submount 100 can be electrically connected to each other by this configuration.
  • In the embodiment, although each of the electrical connections between the IC 111 and the submount 100 is achieved by placing two gold bumps in a space formed by the spacer, the number of gold bumps placed in the space formed by the spacer to achieve the electrical connection may be any number of one or more. The spacer is provided in such a way that the submount 100 and Au wires 112 subjected to wiring and extending out from pads do not come into contact with each other, and electrical connection is achieved by using any number of gold bumps provided in the space formed by the spacer.
    • Tenth Embodiment
  • Description is given below of a variation of a module on which the encapsulated semiconductor element of [Sixth Embodiment] described above is mounted.
  • FIG. 17A is a plan view showing a configuration of the module of the embodiment, and FIG. 17B is a cross-sectional view taken along the cross-section line XVIIB-XVIIB of FIG. 17A. As shown in FIGS. 17A and 17B, the module 109 of the embodiment includes a main substrate 110, electrodes 116 on the main substrate 110, an IC 111 on the main substrate 110, the encapsulated semiconductor element on the main substrate 110, Au wires 112 connecting the IC 111 and the encapsulated semiconductor elements to each other, and gold bumps 113 on the IC 111.
  • The encapsulated semiconductor element is mounted on the electrodes 116. In this case, the electrodes 116 and gold bumps 106 of the encapsulated semiconductor element are bonded to one another by an electrically-conductive adhesive and are thus electrically connected to one another.
  • In the structure shown in FIG. 17, the electrical connection is achieved by bonding the gold bumps 106 and the electrodes 116 to one another with the electrically-conductive adhesive. However, the electrical connection may be achieved by inserting a spacer between the encapsulated semiconductor and the electrodes 116 and providing bumps in a space formed by the spacer 118.
    • Eleventh Embodiment
  • FIG. 18A is a plan view showing a configuration of a module of the embodiment, and FIG. 18B is a cross-sectional view taken along the cross-section line XVIIIB-XVIIIB of FIG. 18A. As shown in FIGS. 18A and 18B, the module 109 of the embodiment includes a main substrate 110, electrodes 116 on the main substrate 110, an IC 111 on the main substrate 110, an encapsulated semiconductor element on the main substrate 110, Au wires 112 connecting the IC 111 and the encapsulated semiconductor element to each other, and gold bumps 113 on the IC 111.
  • A step is formed in the main substrate 110 by spot-facing, and an element mounting surface of the main substrate 110 has an upper surface and a lower surface. The IC 111 is mounted on the upper surface of the main substrate 110, and the encapsulated semiconductor element is mounted on the lower surface of the main substrate 110.
  • The gold bumps 113 are provided on the IC 111 to connect the IC 111 and the encapsulated semiconductor element to each other by using the Au wires 112. Since exposed cut surfaces of the gold bumps 106 function as side surface electrodes of the encapsulated semiconductor element, the IC 111 and the encapsulated semiconductor element can be electrically connected to each other.
    • Twelfth Embodiment
  • FIG. 19A is a plan view showing a configuration of a module of the embodiment, and FIG. 19B is a cross-sectional view taken along the cross-section line XIXB-XIXB of FIG. 19A. As shown in FIGS. 19A and 19B, the module 109 of the embodiment includes a main substrate 110, electrodes 116 on the main substrate 110, an IC 111 on the main substrate 110, a spacer 118 on the main substrate 110, an encapsulated semiconductor element on the spacer 118, gold bumps 113 on the IC 111, and gold bumps 117.
  • The spacer 118 is installed between the main substrate 110 and the encapsulated semiconductor element, and the module 109 thereby has a space between the IC 111 and the encapsulated semiconductor element. The gold bumps 113 on the IC 111 and the gold bumps 117 are configured to come into contact with one another in the space formed by the spacer 118. The IC 111 and the encapsulated semiconductor element can be electrically connected to each other by this configuration.
  • In the embodiment described above, although each of the electrical connections between the IC 111 and the encapsulated semiconductor element is achieved by employing a configuration in which two gold bumps are placed in a space formed by the spacer, the number of gold bumps placed in the space formed by the spacer to achieve the electrical connection may be any number of one or more.
    • Thirteenth Embodiment
  • FIG. 20 is a perspective view showing a configuration of an encapsulated semiconductor element of the embodiment. As shown in FIG. 20, the encapsulated semiconductor element of the embodiment includes a semiconductor element 104, multiple gold bumps 106 on the semiconductor element 104, and a resin 108 encapsulating the multiple gold bumps 106 on the semiconductor element 104.
  • FIG. 21A is a plan view of a module including the encapsulated semiconductor element of the embodiment, and FIG. 21B is a cross-sectional view taken along the cross-section line XXIB-XXIB of FIG. 21A. As shown in FIGS. 21A and 21B, the encapsulated semiconductor element of the embodiment can be mounted on a circuit board 122 by using solder 121 like a CSP (Chip Size Package). An electrically-conductive adhesive can be used instead of the solder 121.
  • FIGS. 22A to 22C show steps of manufacturing the encapsulated semiconductor element of the embodiment.
  • First, the multiple gold bumps 106 are formed on surface electrodes of a wafer 114 not subjected to dicing (FIG. 22A). As shown in FIG. 22A, the gold bumps 106 are formed to be arranged in straight lines along an x-axis direction and a y-axis direction.
  • Next, the resin 108 is applied to encapsulate the gold bumps 106 on the wafer 114. The resin 108 is evenly applied to the wafer 114 (FIG. 22B). After the application of the resin 108, the resin is cured by heating, UV curing, or the like.
  • Lastly, the wafer is diced along dicing lines into individual semiconductor elements 104. Cut surfaces of the gold bumps 106 are exposed by the dicing (FIG. 22C). The exposed surfaces of the gold bumps 106 function as side surface electrodes of the encapsulated semiconductor element. The encapsulated semiconductor element shown in FIG. 22C has 16 side surface electrodes and the 16 side surface electrodes are linearly arranged in the x direction or the y direction.
    • Fourteenth Embodiment
  • FIG. 23 is a perspective view showing a configuration of an encapsulated semiconductor element of the embodiment. As shown in FIG. 23, the encapsulated semiconductor element of the embodiment includes a semiconductor element 104, multiple gold bumps 106 on the semiconductor element 104, and a resin 108 encapsulating the multiple gold bumps 106 on the semiconductor element 104.
  • FIG. 24A is a plan view of a module including the encapsulated semiconductor element of the embodiment, and FIG. 24B is a cross-sectional view taken along the cross-section line XXIVB-XXIVB of FIG. 24A. As shown in FIGS. 24A and 24B, the encapsulated semiconductor element of the embodiment can be mounted on a circuit board 122 by using solder 121 like a CSP (Chip Size Package). An electrically-conductive adhesive can be used instead of the solder.
  • Moreover, the encapsulated semiconductor element of the embodiment can be mounted on the main substrate in which a step is formed by spot-facing and an element mounting surface has an upper surface and a lower surface. The IC is mounted on the upper surface of the main substrate, and the encapsulated semiconductor element is mounted on the lower surface of the main substrate. One side surface of the encapsulated semiconductor element is fixed to the lower surface of the main substrate by a non-electrically-conductive adhesive, solder, an electrically-conductive adhesive, or the like. The IC and cut surfaces of the gold bumps exposed on another side surface of the encapsulated semiconductor element are connected by wires.
  • FIGS. 25A to 25C are views showing steps of manufacturing the encapsulated semiconductor element of the embodiment.
  • First, the multiple gold bumps 106 are formed on surface electrodes of a wafer 114 not subjected to dicing (FIG. 25A). As shown in FIG. 25A, the gold bumps 106 are formed to be arranged in straight lines along a y-axis direction.
  • Next, the resin 108 is applied to encapsulate the gold bumps 106 on the wafer 114. The resin 108 is evenly applied to the wafer 114 (FIG. 25B). After the application of the resin 108, the resin is cured by heating, UV curing, or the like.
  • Lastly, the wafer 114 is diced along dicing lines into individual semiconductor elements 104. Cut surfaces of the gold bumps 106 are exposed by the dicing (FIG. 25C). The exposed surfaces of the gold bumps 106 function as side surface electrodes of the encapsulated semiconductor element. The encapsulated semiconductor element shown in FIG. 25C has 12 side surface electrodes, and the 12 side surface electrodes are linearly arranged in the y direction.
    • Fifteenth Embodiment
  • FIGS. 28A and 28B are views showing a configuration of a submount of the embodiment. As shown in FIG. 28B, the submount 200 of the embodiment includes a substrate 201, electrodes 203, a semiconductor element 204, Au wires 205, and gold bumps 206 and 207. The submount 200 of the embodiment is different from the submount of [Third Embodiment] of FIG. 9 in that a groove 213 is provided in the substrate 201 and the semiconductor element 204 is mounted in the groove 213. Constitutional elements other than the point that the groove 213 is formed and the point that the semiconductor element 204 is directly mounted on the substrate 201 are the same as those of [Third Embodiment]. Accordingly, description thereof is omitted.
  • As shown in FIG. 28A, the groove 213 of the embodiment is formed linearly in an arrangement direction of the gold bumps 207 arranged on a surface of the substrate 201 which faces forward in a y-axis direction, i.e. in an X direction of FIG. 28A.
  • FIG. 28C is a view showing a configuration of another submount of the embodiment. As shown in FIG. 28C, in a submount 300 of the embodiment, a rectangular recess-shaped groove 214 having a longitudinal direction that is the same as the longitudinal direction (X direction) of the groove 213 of FIG. 28A is formed on the substrate 201. The semiconductor element 204 is mounted in the recess-shaped groove 214.
  • FIGS. 29A to 29D are views showing an example of a method of wire bonding in the embodiment. A method of wire bonding in the embodiment is shown below as an example. FIG. 29A shows the substrate 201 before the wire bonding of the embodiment.
  • In a first step, spot-facing (cutting) is performed on the substrate 201 to form the groove 213 (FIG. 29B). Ina second step, the semiconductor element 204 is mounted in the groove 213 (FIG. 29C). In a third step, the gold bumps 206 of the Au wires 205 are formed on pads of the semiconductor element 204 with a ball bonder, and the Au wires 205 are connected from the semiconductor element 204 to the electrodes 203 on the substrate 201 (FIG. 29C). In a fourth step, the gold bumps 207 are formed on the electrodes 203 and the Au wires 205 connected in the third step with the ball bonder (FIG. 29D). The wire bonding can be performed in the steps described above.
  • The submount 200 of the embodiment is manufactured as follows. First, the gold bumps 207 are formed on the electrodes 203 by the aforementioned wire bonding method in the embodiment. After the gold bumps 207 are formed on the electrodes 203, a resin 208 is applied in such a way that the gold bumps 207 are covered. Then, the applied resin 208 is cured by heating, UV curing, or the like. Thereafter, dicing is performed in such a way that cut surfaces of the gold bumps 207 are exposed. Here, the resin 208 has hardness sufficient to withstand the force of wire bonding. Note that the wire bonding method in the embodiment can be applied to the other embodiments described above.
  • In the embodiment, as in the third embodiment, the semiconductor element 204 can be prevented from being damaged during resin curing. Moreover, the amount of resin to be applied can be reduced. Note that stress due to resin curing or expansion and shrinkage of the resin caused by temperature fluctuations or the like may damage the semiconductor element.
  • Furthermore, in the submount 200 of the embodiment, mounting the semiconductor element 204 in the groove 213 on the substrate 201 can reduce the distance between the semiconductor element 204 and the surface of the substrate 201 compared to that in a submount in which no spot-facing portion is formed in the substrate 201. The length of wire bonding is thus reduced and lines of higher speed can be achieved.
    • Sixteenth Embodiment
  • FIG. 30 is a view showing a configuration of a submount of the embodiment. As shown in FIG. 30, it is possible to apply a resin 208 in such a way that gold bumps 207 are covered, and then apply another resin 215 on a substrate 201. The submount 300 of the embodiment is different from the submount of [Fifteenth Embodiment] in that the submount 300 further includes the resin 215. Since constitutional elements other than the resin 215 are the same as those of [Fifteenth Embodiment], description thereof is omitted.
  • The submount 300 of the embodiment is manufactured as follows. First, the gold bumps 207 are formed on electrodes 203 by the wire bonding method of the fifteenth embodiment. After the gold bumps 207 are formed on the electrodes 203, the resin 208 is applied in such a way that the gold bumps 207 are covered. After the application of the resin 208, the resin 215 is applied onto the substrate 201. Then, the applied resin 215 is cured by heating, UV curing, or the like. Thereafter, dicing is performed in such a way that cut surfaces of the gold bumps 207 are exposed. Here, the resin 208 has hardness sufficient to withstand the force of wire bonding, and the resin 215 has hardness lower than that of the resin 208.
  • If the hardness of the resin is too high, the semiconductor element 204 may be damaged. However, in the embodiment, since the gold bumps 207 are protected by the hard resin 208 while the semiconductor element 204 is protected by the soft resin 215, the semiconductor element 204 can be prevented from being damaged.
  • A drive IC or an optical element such as a laser diode are examples of the semiconductor element in all of the embodiments described above.
    • REFERENCE SIGNS LIST
    • 100, 200, 300, 400: submount
    • 101, 201: substrate
    • 102, 103, 116, 203: electrode
    • 104, 204: semiconductor element
    • 105, 112, 205: Au wire
    • 106, 107, 113, 117, 207: gold bump
    • 108, 115, 208, 215: resin
    • 109: module
    • 110: main substrate
    • 111: IC
    • 114: wafer
    • 118: spacer
    • 120: electrical connection
    • 121: solder
    • 122: circuit board
    • 123: bump
    • 213, 214: groove

Claims (21)

1-17. (canceled)
18. A submount comprises:
a substrate;
an electrode on the substrate;
a semiconductor element on the substrate;
a wire connecting the semiconductor element and the electrode to each other; and
one or plurality of first bumps on the electrode and the wire, wherein
the electrode, the semiconductor element, the wire, and the one or plurality of first bumps are encapsulated on the substrate by a resin,
the one or plurality of first bumps have a cut surface,
the cut surface is exposed on a surface of the submount, and
the cut surface is an electrode of the submount.
19. The submount according to claim 18, wherein
a groove is formed on the substrate, and
the semiconductor element is mounted in the groove.
20. A module comprises:
a main substrate;
an IC on the main substrate;
the submount according to claim 18 which is provided on the main substrate; and
a wire for wire bonding a second bump on the IC and the first bump included in the submount to each other.
21. A module comprises:
a main substrate;
an IC on the main substrate;
an electrode on the main substrate;
a wire connecting a second bump on the IC and the electrode to each other; and
the submount according to claim 18 which is provided on the electrode on the main substrate,
wherein the exposed cut surface of the first bump of the submount and the electrode on the main substrate are bonded to each other by an electrically-conductive adhesive.
22. A module comprises:
a main substrate;
an IC on the main substrate;
an electrode on the main substrate;
a wire connecting a second bump on the IC and the electrode to each other;
a spacer on the electrode; and
the submount according to claim 18 which is provided on the spacer,
wherein an electrical connection between the second bump on the IC and the first bump included in the submount is achieved by third bumps and the electrode placed in a space formed by the spacer.
23. A module comprises:
a main substrate;
an IC on the main substrate; and
the submount according to claim 18 which is provided on the main substrate,
wherein
the main substrate has an upper surface and a lower surface as element mounting surfaces,
the IC is mounted on the upper surface and the submount is mounted on the lower surface, and
the module further comprises a wire for wire bonding a second bump on the IC and the first bump included in the submount to each other.
24. A module comprises:
a main substrate;
an IC on the main substrate;
a spacer on the IC; and
the submount according to claim 18 which is provided on the spacer,
wherein an electrical connection between a second bump on the IC and the one or plurality of first bumps included in the submount is achieved by one or plurality of third bumps placed in a space formed by the spacer.
25. A module comprises:
a main substrate;
an electrode on the main substrate;
an IC on the electrode;
a spacer on the electrode; and
the submount according to claim 18 which is provided on the spacer,
wherein an electrical connection between a second bump on the IC and the first bump included in the submount is achieved by third bumps and the electrode placed in a space formed by the spacer.
26. A submount comprises:
a substrate;
an electrode on the substrate;
a semiconductor element on the substrate;
a wire connecting the semiconductor element and the electrode to each other; and
a first bump on the electrode and the wire,
wherein
the first bump is encapsulated by a first resin which is locally applied on the substrate,
the first bump has an exposed cut surface, and
the exposed cut surface is an electrode of the submount.
27. The submount according to claim 26, the submount further comprises:
a second resin encapsulating the electrode, the semiconductor element, the wire, the first bump, and the first resin, and
the first resin is harder than the second resin.
28. The submount according to claim 26, wherein
a groove is formed on the substrate, and
the semiconductor element is mounted in the groove.
29. A module comprises:
a main substrate;
an IC on the main substrate;
the submount according to claim 26 which is provided on the main substrate; and
a wire for wire bonding a second bump on the IC and the first bump included in the submount to each other.
30. A module comprises:
a main substrate;
an IC on the main substrate;
an electrode on the main substrate;
a wire connecting a second bump on the IC and the electrode to each other; and
the submount according to claim 26 which is provided on the electrode on the main substrate,
wherein the exposed cut surface of the first bump of the submount and the electrode on the main substrate are bonded to each other by an electrically-conductive adhesive.
31. A module comprises:
a main substrate;
an IC on the main substrate;
an electrode on the main substrate;
a wire connecting a second bump on the IC and the electrode to each other;
a spacer on the electrode; and
the submount according to claim 26 which is provided on the spacer,
wherein an electrical connection between the second bump on the IC and the first bump included in the submount is achieved by third bumps and the electrode placed in a space formed by the spacer.
32. A module comprises:
a main substrate;
an IC on the main substrate; and
the submount according to claim 26 which is provided on the main substrate,
wherein
the main substrate has an upper surface and a lower surface as element mounting surfaces,
the IC is mounted on the upper surface and the submount is mounted on the lower surface, and
the module further comprises a wire for wire bonding a second bump on the IC and the first bump included in the submount to each other.
33. A module comprises:
a main substrate;
an IC on the main substrate;
a spacer on the IC; and
the submount according to claim 26 which is provided on the spacer,
wherein an electrical connection between a second bump on the IC and the first bump included in the submount is achieved by one or plurality of third bumps placed in a space formed by the spacer.
34. A module comprises:
a main substrate;
an electrode on the main substrate;
an IC on the electrode;
a spacer on the electrode; and
the submount according to claim 26 which is provided on the spacer,
wherein an electrical connection between a second bump on the IC and the first bump included in the submount is achieved by third bumps and the electrode placed in a space formed by the spacer.
35. A module comprises:
a main substrate;
an IC on the main substrate; and
an encapsulated semiconductor element on the main substrate,
wherein
the main substrate has an upper surface and a lower surface as element mounting surfaces,
the IC is mounted on the upper surface and the encapsulated semiconductor element is mounted on the lower surface, and
the module further comprises a wire for wire bonding a second bump on the IC and the first bump included in the encapsulated semiconductor element to each other; and
the encapsulated semiconductor element comprises:
a semiconductor element; and
a first bump on the semiconductor element, wherein
the first bump is encapsulated on the semiconductor element by a resin,
the first bump has an exposed cut surface, and
the exposed cut surface is an electrode of the encapsulated semiconductor element.
36. The module according to claim 35, wherein the first bump is encapsulated by a first resin applied only to a portion around the first bump on the semiconductor element.
37. The module according to claim 36, wherein
the encapsulated semiconductor element further comprises a second resin encapsulating the semiconductor element, the first bump, and the first resin, and
the first resin is harder than the second resin.
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