JPWO2013061381A1 - 薄膜半導体装置及び薄膜半導体装置の製造方法 - Google Patents
薄膜半導体装置及び薄膜半導体装置の製造方法 Download PDFInfo
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Abstract
Description
図1及び図2を参照して、本発明の実施の形態に係る有機EL(Electro Luminescence)ディスプレイ(有機EL表示パネル)10及び画像表示装置用の薄膜トランジスタアレイ装置(以下、単に「薄膜トランジスタアレイ装置」と表記する)20を説明する。なお、図1は、薄膜半導体アレイ基板1を示す図である。図2は、本発明の実施の形態に係る表示装置の一例である有機ELディスプレイ10の斜視図である。
次に、図8を参照して、上記の実施の形態の変形例1を説明する。図8は、図5に対応する図である。なお、上記の実施の形態との共通点の説明は省略し、相違点を中心に説明する。
次に、図9及び図10を参照して、上記の実施の形態の変形例2を説明する。図9及び図10は、それぞれ図4及び図6Aに対応する図である。なお、上記の実施の形態との共通点の説明は省略し、相違点を中心に説明する。
10 有機ELディスプレイ
11 層間絶縁膜
12 陽極
13 有機EL層
14 透明陰極
15 バンク
20 薄膜トランジスタアレイ装置
21,21’ ゲート配線
21a 第1ゲート配線
21b 第2ゲート配線
22 ソース配線
23 電源配線
30,900 画素回路
40 第1のトランジスタ
41,51,921 ゲート電極
41a,51a 第1ゲート電極
41b,51b 第2ゲート電極
42,53,981 ソース電極
43,52,982 ドレイン電極
44,54,941 結晶シリコン層
45,55,951 非結晶シリコン層
50 第2のトランジスタ
51M 遮光性導電性材料
54M 結晶シリコン薄膜
55M 非結晶シリコン薄膜
60 キャパシタ
61,922 第1容量電極
61M 透明導電性材料
62,983 第2容量電極
90 マスク
100,100’ 画素
110,910 基板
120,930 ゲート絶縁膜
131,132,960 チャネル保護層
131M 絶縁膜
141,142,971,972 コンタクト層
141M コンタクト層用薄膜
143 シリコン層
942 第1シリコン層
952 第2シリコン層
973 第3シリコン層
Claims (14)
- 基板と、前記基板上に互いに離間して形成される半導体素子部及び容量部とを備える薄膜半導体装置であって、
前記半導体素子部は、
前記基板上に形成された遮光性のゲート電極と、
前記ゲート電極上に形成された第1絶縁層と、
前記第1絶縁層上に形成されたチャネル層と、
前記チャネル層上に形成された第2絶縁層と、
前記第2絶縁層上に形成されたソース電極及びドレイン電極とを備え、
前記容量部は、
透明導電性材料で前記基板上に形成された第1容量電極と、
前記第1絶縁層と同一の材料で、前記第1容量電極上に形成された誘電体層と、
前記ソース電極及び前記ドレイン電極の少なくとも一方と同一の導電性材料で、前記誘電体層上に形成された第2容量電極とを備え、
前記ゲート電極、前記チャネル層、および前記第2絶縁層は、上面視したときに外形輪郭線が一致するように積層される
薄膜半導体装置。 - 前記ゲート電極は、
前記透明導電性材料で形成された第1ゲート電極と、
遮光性導電性材料で前記第1ゲート電極上に形成された第2ゲート電極とで構成される
請求項1に記載の薄膜半導体装置。 - 前記半導体素子部は、さらに、前記第2絶縁層と前記ソース電極との間、及び前記第2絶縁層と前記ドレイン電極との間に介在し、前記チャネル層の側面とコンタクトするコンタクト層を備える
請求項1又は2に記載の薄膜半導体装置。 - 前記容量部は、さらに、前記誘電体層と前記第2容量電極との間に、前記コンタクト層と同じ材料で形成された中間層を備える
請求項3に記載の薄膜半導体装置。 - 前記チャネル層は、結晶性シリコン薄膜で形成されている
請求項1〜4のいずれか1項に記載の薄膜半導体装置。 - 前記半導体素子部は、さらに、前記チャネル層上に非結晶性の真性シリコン薄膜を備える
請求項1〜5のいずれか1項に記載の薄膜半導体装置。 - 前記第2ゲート電極、前記チャネル層、前記非結晶性の真性シリコン薄膜、および前記第2絶縁層は、上面視したときに外形輪郭線が一致するように積層される
請求項6に記載の薄膜半導体装置。 - 前記第2絶縁層は、有機材料で形成される
請求項1〜7のいずれか1項に記載の薄膜半導体装置。 - 基板を準備する第1工程と、
前記基板上に、遮光性導電性材料でゲート電極を形成すると共に、前記ゲート電極と離間した位置に透明導電性材料で第1容量電極を形成する第2工程と、
前記ゲート電極上および前記第1容量電極上に、第1絶縁層を形成する第3工程と、
前記第1絶縁層上に半導体層を形成する第4工程と、
前記半導体層上に、第2絶縁層を形成する第5工程と、
前記半導体層をエッチングすることにより、前記ゲート電極に重畳する位置にチャネル層を形成する第6工程と、
前記第2絶縁層上の前記チャネル層に重畳する位置にソース電極及びドレイン電極を形成すると共に、前記第1絶縁層上の前記第1容量電極に重畳する位置に第2容量電極を形成する第7工程とを含み、
前記第5工程では、前記半導体層上に前記第2絶縁層を形成した後に、前記基板の前記ゲート電極および前記第1容量電極が形成された面と反対側の面から、前記第2絶縁層に対して前記ゲート電極をマスクに用いて前記第2絶縁層を感光させる光で露光する露光工程と、前記第2絶縁層を現像する現像工程とによって、前記ゲート電極に重畳する位置の前記第2絶縁層を残し、且つ前記第1容量電極に重畳する位置の前記第2絶縁層を除去し、
前記第6工程では、前記ゲート電極に重畳する位置に残された前記第2絶縁層をマスクとして前記半導体層をエッチングする工程によって、前記半導体層を前記ゲート電極に重畳する位置の前記チャネル層として残し、且つ前記第1容量電極に重畳する位置からは前記半導体層を除去することにより、前記ゲート電極、前記チャネル層、および前記第2絶縁層は、上面視したときに外形輪郭線が一致するように形成される
薄膜半導体装置の製造方法。 - 前記ゲート電極は、第1ゲート電極と、前記第1ゲート電極上に形成される第2ゲート電極とで構成され、
前記第2工程は、
前記基板上に、前記透明導電性材料で前記第1ゲート電極と前記第1容量電極とを同時に形成する工程と、
前記第1ゲート電極上に、遮光性導電性材料で前記第2ゲート電極を形成する工程とを含む
請求項9に記載の薄膜半導体装置の製造方法。 - 前記半導体層は、前記光を透過する厚みである
請求項9又は10に記載の薄膜半導体装置の製造方法。 - 前記半導体層の厚みは、30nm以上、200nm以下である
請求項11に記載の薄膜半導体装置の製造方法。 - 前記半導体層は、結晶シリコン層と非結晶シリコン層とを積層して形成され、
前記非結晶シリコン層の厚みは、50nm以下である
請求項11又は12に記載の薄膜半導体装置の製造方法。 - 前記ゲート電極は、前記透明導電性材料で前記第1容量電極と一体形成される第1ゲート電極と、前記第1ゲート電極上に前記遮光性導電性材料で形成される第2ゲート電極とで構成され、
前記第2工程では、ハーフトーンマスクを用いて前記第1ゲート電極、前記第2ゲート電極、及び前記第1容量電極を同時に形成する
請求項9〜13のいずれか1項に記載の薄膜半導体装置の製造方法。
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WO2013061381A1 (ja) | 2013-05-02 |
KR101846589B1 (ko) | 2018-04-06 |
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