JPWO2012018073A1 - パワーモジュールおよび出力回路 - Google Patents
パワーモジュールおよび出力回路 Download PDFInfo
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- JPWO2012018073A1 JPWO2012018073A1 JP2012527763A JP2012527763A JPWO2012018073A1 JP WO2012018073 A1 JPWO2012018073 A1 JP WO2012018073A1 JP 2012527763 A JP2012527763 A JP 2012527763A JP 2012527763 A JP2012527763 A JP 2012527763A JP WO2012018073 A1 JPWO2012018073 A1 JP WO2012018073A1
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- Prior art keywords
- gate
- switching element
- land
- short
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 239000000758 substrate Substances 0.000 claims description 213
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 32
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 229910052802 copper Inorganic materials 0.000 claims description 25
- 239000010949 copper Substances 0.000 claims description 25
- 238000001514 detection method Methods 0.000 claims description 16
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 10
- 239000011889 copper foil Substances 0.000 claims description 10
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 9
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 8
- 239000000919 ceramic Substances 0.000 claims description 5
- 229910052737 gold Inorganic materials 0.000 claims description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 18
- 238000006073 displacement reaction Methods 0.000 description 13
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 10
- 239000004065 semiconductor Substances 0.000 description 10
- 229910052759 nickel Inorganic materials 0.000 description 9
- 239000000463 material Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 230000000630 rising effect Effects 0.000 description 4
- 102100034579 Desmoglein-1 Human genes 0.000 description 3
- 102100034578 Desmoglein-2 Human genes 0.000 description 3
- 101000924316 Homo sapiens Desmoglein-1 Proteins 0.000 description 3
- 101000924314 Homo sapiens Desmoglein-2 Proteins 0.000 description 3
- 239000008186 active pharmaceutical agent Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- -1 DMG2 Proteins 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000005549 size reduction Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
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Abstract
Description
ハーフブリッジ出力回路101は、ハイサイドの第1のMOSFET(Metal Oxide Semiconductor Field Effect Transistor)102と、第1のMOSFET102に直列に接続されたローサイドの第2のMOSFET103と、これらのMOSFET102,103を駆動するためのゲート駆動回路104と、ゲート駆動回路104を制御する制御部105とを含んでいる。第1のMOSFET102と第2のMOSFET103とは、電源106に直列に接続されている。
この発明の目的は、直列に接続された2つのスイッチング素子のうちの一方のスイッチング素子がターンオンしたときに、他方のスイッチング素子のゲート・ソース間電圧の上昇を抑制または防止できるパワーモジュールおよび出力回路を提供することである。
この発明の一実施形態では、前記第1のパワースイッチング素子および前記第2のパワースイッチング素子は、IGBT(Insulated Gate Bipolar Transistor)からなる。
この発明の一実施形態では、前記第1のパワースイッチング素子と前記第1のゲート短絡用スイッチング素子とが同一の実装基板上に実装されており、前記第2のパワースイッチング素子と前記第2のゲート短絡用スイッチング素子とが同一の実装基板上に実装されている。この構成によれば、パワーモジュールの小型化を図ることが可能となる。また、各パワースイッチング素子とそれに対応するゲート短絡用スイッチング素子とを接続するための配線を短くすることができる。このため、各パワースイッチング素子とそれに対応するゲート短絡用スイッチング素子との間のインピーダンスを小さくすることができる。これにより、各パワースイッチング素子のゲート・ソース間電圧の上昇抑制効果を向上させることができる。
この発明の一実施形態では、前記第1のパワースイッチング素子と前記第1のゲート短絡用スイッチング素子とが同一のチップに設けられており、前記第2のパワースイッチング素子と前記第2のゲート短絡用スイッチング素子とが同一のチップに設けられている。この構成によれば、パワーモジュールのさらなる小型化を図ることが可能となる。また、各パワースイッチング素子とそれに対応するゲート短絡用スイッチング素子との間のインピーダンスをより小さくすることができる。これにより、各パワースイッチング素子のゲート・ソース間電圧の上昇抑制効果をさらに向上させることができる。
この発明の一実施形態では、前記第1のパワースイッチング素子と前記第1のゲート短絡用スイッチング素子とを接続するための第1の接続金属部材と、前記第2のパワースイッチング素子と前記第2のゲート短絡用スイッチング素子とを接続するための第2の接続金属部材とを含む。前記第1の接続金属部材および前記第2の接続金属部材は、Au,Cu,またはAlからなるワイヤ状、フレーム状またはリボン状であってもよい。
図1は、本発明の一実施形態に係るパワーモジュールを適用したハーフブリッジ出力回路1を示す電気回路図である。
ハーフブリッジ出力回路1は、パワーモジュール2と、ゲート駆動回路3と、制御部4を含む。パワーモジュール2は、第1の電源端子11と、第2の電源端子(第2の出力端子)12と、第1の主回路用ゲート端子13と、第1の短絡用ゲート端子14と、第1のソースセンス端子15と、第2の主回路用ゲート端子16と、第2の短絡用ゲート端子17と、第2のソースセンス端子18と、第1の出力端子19とを含んでいる。
パワーモジュール2は、絶縁性基板51と、絶縁性基板51の一方表面に固定されたケース52とを含む。絶縁性基板51は、平面視において一方向に長い矩形に形成されている。ケース52は、下面が開口した略直方体形状に形成されており、樹脂材料で構成されている。
第2の主回路用ゲート・ランド82は、平面視において絶縁性基板51の幅方向に長い矩形であり、第2の主回路用ドレイン・ランド部72に対して絶縁性基板51の第2短辺51b側において、第2の主回路用ドレイン・ランド部72に隣接して配置されている。第2のソースセンス・ランド83は、平面視において第2の主回路用ドレイン・ランド部72に比べて長さおよび幅が小さい矩形であり、第2の主回路用ドレイン・ランド部72の切除部72a内に配置されている。第2の短絡用ゲート・ランド84は、平面視において絶縁性基板51の幅方向に長い矩形であり、第2の主回路用ゲート・ランド82と絶縁性基板51の第2短辺51bとの間に配置されている。
図3は、制御部4によって生成される各ゲート制御信号を示すタイムチャートである。
図3の例では、各ゲート制御信号の組合せの状態には0〜7の状態がある。そして、0〜7の状態が繰り返される。
状態2では、第2の主回路用ゲート制御信号MG2がLレベルからHレベルに反転する。これにより、ローサイドの第2の主回路用MOSFET22がターンオンする。ローサイドの第2の主回路用MOSFET22がターンオンすると、ハイサイドの第1の主回路用MOSFET21に電源電圧が印加されるので、第1の主回路用MOSFET21のドレイン・ソース間電圧VDSが急激に上昇する。したがって、第1の主回路用MOSFET21のドレインからゲートに向かって変位電流IDGが流れる。第1の主回路用MOSFET21のドレイン・ゲート間電圧をVDGとし、第1の主回路用MOSFET21のドレイン・ゲート間の寄生容量をCDGとすると、変位電流IDGはIDG=CDG・dVDG/dtとなる。dVDG/dtの値は、第2の主回路用MOSFET22のターンオン時上昇時間(立ち上がり時間tr)で決定される。
状態4では、第1の短絡用ゲート制御信号SG1がHレベルからLレベルに反転する。これにより、第1の短絡用MOSFET25がターンオフする。
状態5では、第2の短絡用ゲート制御信号SG2がLレベルからHレベルに反転する。これにより、ローサイドの第2の短絡用MOSFET26がオンする。これにより、ローサイドの第2の主回路用MOSFET22のゲート・ソース間が、第2の短絡用MOSFET26によって短絡される。
状態7に続く状態0では、第2の短絡用ゲート制御信号SG2がHレベルからLレベルに反転する。これにより、ローサイドの第2の短絡用MOSFET26がターンオフする。
また、前述の実施形態では、短絡用MOSFET25,26は、主回路用MOSFET21,22が実装された絶縁性基板51上に実装されているが、短絡用MOSFET25,26を絶縁性基板51上に実装しなくてもよい。たとえば、第1の短絡用MOSFET25が形成されたチップを、ケース51内またはケース51外において、第1の主回路用MOSFET21のゲート電極が接続された端子(主回路用ゲート端子13)と、第1の主回路用MOSFET21のソース電極が接続された端子(第1のソースセンス端子15または第1の出力端子19)との間に接続するようにしてもよい。より具体的には、第1の短絡用MOSFET25が形成されたチップのドレイン端子をリード線等の導電線によって主回路用ゲート端子13に電気的に接続し、当該チップのソース端子をリード線等の導電線によって第1のソースセンス端子15または第1の出力端子19に接続してもよい。当該チップがケース51内に配置されている場合には、当該チップのゲート端子にリードを接続してケース51の外側に引き出してもよい。
平面視において、絶縁性基板151の一方の短辺を「第1短辺151a」といい、他方の短辺を「第2短辺151b」ということにする。また、平面視において、絶縁性基板151の一方の長辺を「第1長辺151c」といい、他方の長辺を「第2長辺151d」ということにする。また、絶縁性基板151の長辺151c,151dに沿う方向を「絶縁性基板151の長さ方向」といい、絶縁性基板151の短辺151a,151bに沿う方向を、「絶縁性基板151の幅方向」ということにする。
第1アッセンブリ160は、第1の主回路用ソース・ランド部171と、絶縁性基板151上に形成された他の複数のランド161〜163と、第1の主回路用MOSFET21(第1のダイオード23を内蔵したもの)と、複数の端子11,13,15とを含む。複数のランド161〜163は、第1の主回路用ドレイン・ランド161、第1の主回路用ゲート・ランド162および第1のソースセンス・ランド163を含んでいる。これらのランド161〜163は、銅またはアルミニウムの板状体からなる。
第1のソースセンス・ランド163は、平面視において絶縁性基板151の長さ方向に長い略矩形であり、かつその長さは第1の主回路用ドレイン・ランド161の幅より短い。第1のソースセンス・ランド163は、第1の主回路用ドレイン・ランド161の切除部161a内に、第1の主回路用ゲート・ランド162に対して絶縁性基板151の第1長辺151cとは反対側において、第1の主回路用ゲート・ランド162に隣接して配置されている。
第1の主回路用MOSFET21のソース電極21Sは、複数のボンディングワイヤ(接続金属部材)165によって、第1の主回路用ソース・ランド部171に電気的に接続されている。また、第1の主回路用MOSFET21のソース電極21S(電流検出部27)は、ボンディングワイヤ(接続金属部材)166によって、第1のソースセンス・ランド163に電気的に接続されている。第1の主回路用MOSFET21のゲート電極21Gは、ボンディングワイヤ(接続金属部材)168によって、第1の主回路用ゲート・ランド162に電気的に接続されている。
第2アッセンブリ180は、第2の主回路用ドレイン・ランド部172と、絶縁性基板151上に形成された他の複数のランド181〜183と、第2の主回路用MOSFET22(第2のダイオード24を内蔵したもの)と、複数の端子12,16,18とを含む。複数のランド181〜183は、第2の主回路用ソース・ランド181、第2の主回路用ゲート・ランド182および第2のソースセンス・ランド183を含んでいる。これらのランド181〜183は、銅またはアルミニウムの板状体からなる。
第2の主回路用ゲート・ランド182は、平面視において絶縁性基板151の長さ方向に長い略矩形であり、その長さは第2の主回路用ドレイン・ランド部172の幅とほぼ等しい。第2の主回路用ゲート・ランド182は、第2の主回路用ドレイン・ランド部172に対して絶縁性基板151の第1長辺151cとは反対側において、第2の主回路用ドレイン・ランド部172に隣接して配置されている。
第2の主回路用MOSFET22のソース電極22Sは、複数のボンディングワイヤ(接続金属部材)185によって、第2の主回路用ソース・ランド181に電気的に接続されている。また、第2の主回路用MOSFET22のソース電極22S(電流検出部28)は、ボンディングワイヤ(接続金属部材)186によって、第2のソースセンス・ランド183に電気的に接続されている。第2の主回路用MOSFET22のゲート電極22Gは、ボンディングワイヤ(接続金属部材)188によって、第2の主回路用ゲート・ランド182に電気的に接続されている。
共通ランド170における連結部173の表面の長さ中央部には、第1の出力端子19の基端部が接合されている。第1の出力端子19は、導電性の板状体からなる。第1の出力端子19は、図2に示される第1の出力端子19と同様に、絶縁性基板151の長さ方向から見てクランク形状である。第1の出力端子19の先端部は、ケース152における絶縁性基板151の第1長辺151c側の側壁を貫通して、ケース152外方に突出している。
ゲート駆動回路実装基板300上における端子13,15の近傍には、第1の短絡用MOSFET25が形成されたチップ25Aが取り付けられている。また、ゲート駆動回路実装基板300における端子16,18の近傍には、第2の短絡用MOSFET26が形成されたチップ26Aが取り付けられている。
チップ91内には、第1の主回路用MOSFET21と第1の短絡用MOSFET25とが設けられている。このチップ91は、一方の表面に第1の主回路用MOSFET21のドレイン電極21Dを有している。また、このチップ91は、他方の表面に、第1の主回路用MOSFET21のソース電極21Sおよびゲート電極21Gと、第1の短絡用MOSFET25のゲート電極25Gとを有している。
図7Aおよび図7Bは、図2のパワーモジュールの他の例を示している。図7Aは、パワーモジュールの内部構造を示す図解的な平面図である。図7Bは、パワーモジュールの外観を示す図解的な平面図である。
パワーモジュール2Cは、絶縁性基板251と、絶縁性基板251の一方表面に固定されたケース252とを含む。絶縁性基板251は、平面視において一方向に長い矩形に形成されている。ケース252は、下面が開口した略直方体形状に形成されており、樹脂材料で構成されている。
第1の主回路用ドレイン・ランド262の表面には、各第1の主回路用MOSFET21のドレイン電極が接合されている。各第1の主回路用MOSFET21は、第1の主回路用ドレイン・ランド262とは反対側の表面にソース電極21Sおよびゲート電極21Gを有している。第1の主回路用ゲート・ランド263の表面には、各第1の短絡用MOSFET25のドレイン電極が接合されている。各第1の短絡用MOSFET25は、第1の主回路用ゲート・ランド263とは反対側の表面にソース電極25Sおよびゲート電極25Gを有している。
第1の主回路用ドレイン・ランド262は、複数のボンディングワイヤ276によって、第1の電源端子接続用ランド266に電気的に接続されている。第1の電源端子接続用ランド266には、第1の電源端子11(図7B参照)が電気的に接続されている。第1の電源端子11の先端部は、ケース252における絶縁性基板251の第2短辺251b側の側壁を貫通して、ケース252外方に突出している。
第2の主回路用ドレイン・ランド282の表面には、各第2の主回路用MOSFET22のドレイン電極が接合されている。各第2の主回路用MOSFET22は、第2の主回路用ドレイン・ランド282とは反対側の表面にソース電極22Sおよびゲート電極22Gを有している。第2の主回路用ゲート・ランド283の表面には、各第2の短絡用MOSFET26のドレイン電極が接合されている。各第2の短絡用MOSFET26は、第2の主回路用ゲート・ランド283とは反対側の表面にソース電極26Sおよびゲート電極26Gを有している。
第2の主回路用ドレイン・ランド282は、複数のボンディングワイヤ298によって、第1の主回路用ソース・ランド261に電気的に接続されている。また、第2の主回路用ドレイン・ランド282は、複数のボンディングワイヤ296によって、第1の出力端子接続用ランド286に電気的に接続されている。第1の出力端子接続用ランド286には、第1の出力端子19(図7B参照)が電気的に接続されている。第1の出力端子19は、ケース252内において途中から二股に分岐しており、2つの先端部を有している。各先端部は、ケース252における絶縁性基板251の第1短辺251a側の側壁を貫通して、ケース252外方に突出している。
前述の実施形態では、第1および第2の主回路用MOSFET21,22と、第1および第2の短絡用MOSFET25,26は、SiCデバイスであるが、Si(シリコン)を半導体材料として用いたSiデバイスでMOSFET21,22,25,26を構成してもよい。また、前述した実施形態では、パワースイッチング素子21,22としてMOSFETが用いられているが、パワースイッチング素子21,22としてIGBT(Insulated Gate Bipolar Transistor)等の他の形態のスイッチング素子が適用されてもよい。また、前述の実施形態では、MOSFET21,22,25,26がワイヤを用いて接続された例を説明したが、リボン状、リード状の接続金属部材を代わりに用いてもよい。また、これらの接続金属部材の材料は、Au,Cu,Al等であってもよい。
この出願は、2010年8月4日に日本国特許庁に提出された特願2010−175403号に対応しており、これらの出願の全開示はここに引用により組み込まれるものとする。
3 ゲート駆動回路
4 制御部
21 第1の主回路用MOSFET
22 第2の主回路用MOSFET
25 第1の短絡用MOSFET
26 第2の短絡用MOSFET
51,151,251 絶縁性基板
Claims (18)
- 第1のパワースイッチング素子と、
前記第1のパワースイッチング素子に直列に接続された第2のパワースイッチング素子と、
前記第1のパワースイッチング素子のゲートとソースとの間に接続された第1のゲート短絡用スイッチング素子と、
前記第2のパワースイッチング素子のゲートとソースとの間に接続された第2のゲート短絡用スイッチング素子と、
を含むパワーモジュール。 - 前記第1のパワースイッチング素子および前記第2のパワースイッチング素子は、炭化珪素を主成分とするスイッチング素子である、請求項1に記載のパワーモジュール。
- 前記第1のパワースイッチング素子および前記第2のパワースイッチング素子は、IGBTからなる、請求項1に記載のパワーモジュール。
- 前記第1のパワースイッチング素子と前記第1のゲート短絡用スイッチング素子とが同一の実装基板上に実装されており、
前記第2のパワースイッチング素子と前記第2のゲート短絡用スイッチング素子とが同一の実装基板上に実装されている、請求項1〜3のいずれか一項に記載のパワーモジュール。 - 前記第1のパワースイッチング素子と前記第1のゲート短絡用スイッチング素子とが実装されている実装基板と、前記第2のパワースイッチング素子と前記第2のゲート短絡用スイッチング素子とが実装されている実装基板とが、同一の実装基板である、請求項4に記載のパワーモジュール。
- 前記実装基板上に形成され、前記第1のパワースイッチング素子および第2のパワースイッチング素子のうちの一方のパワースイッチング素子のソースが電気的に接続されるとともに他方のパワースイッチング素子のドレインが電気的に接続される導電性の共通ランドをさらに含み、
前記共通ランドは、平面視略U形の板状体からなる、請求項5に記載のパワーモジュール。 - 前記実装基板上に形成され、前記第1のパワースイッチング素子および第2のパワースイッチング素子のうちの一方のパワースイッチング素子のソースが電気的に接続されるとともに他方のパワースイッチング素子のドレインが電気的に接続される導電性の共通ランドをさらに含み、
前記共通ランドは、銅またはアルミニウム製の板状体からなる、請求項5に記載のパワーモジュール。 - 前記実装基板上に形成され、前記第1のパワースイッチング素子のゲートが電気的に接続されるとともに、前記第1のゲート短絡用スイッチング素子が接合される第1のゲート・ランドと、
前記実装基板上に形成され、前記第1のゲート短絡用スイッチング素子のゲートが電気的に接続される第1の短絡用ゲート・ランドと、
前記実装基板上に形成され、前記第2のパワースイッチング素子のゲートが電気的に接続されるとともに、前記第2のゲート短絡用スイッチング素子が接合される第2のゲート・ランドと、
前記実装基板上に形成され、前記第2のゲート短絡用スイッチング素子のゲートが電気的に接続される第2の短絡用ゲート・ランドとをさらに含み、
前記共通ランドは、一対の腕部とそれらを連結する連結部とを含み、
前記第1のゲート・ランドおよび前記第1の短絡用ゲート・ランドの組と、前記第2のゲート・ランドおよび前記第2の短絡用ゲート・ランドの組とのうち、一方の組は前記共通ランドの一対の腕部の間に配置され、他方の組は前記共通ランドの一方の腕部に対して前記一方の組と反対側に配置されている、請求項6または7に記載のパワーモジュール。 - 前記第1のゲート・ランドと前記第1の短絡用ゲート・ランドとは、前記共通ランドの連結部の延びる方向に沿って隣接して配置されており、
前記第2のゲート・ランドと前記第2の短絡用ゲート・ランドとは、前記共通ランドの連結部の延びる方向に沿って隣接して配置されている、請求項8に記載のパワーモジュール。 - 前記実装基板が、セラミックス上に銅箔が直接接合されたDBC基板であり、前記共通ランドと、前記第1のゲート・ランドと、前記第1の短絡用ゲート・ランドと、前記第2のゲート・ランドと、前記第2の短絡用ゲート・ランドとは、前記銅箔によって形成されている、請求項8または9に記載のパワーモジュール。
- 前記第1のパワースイッチング素子と前記第1のゲート短絡用スイッチング素子とが同一のチップに設けられており、前記第2のパワースイッチング素子と前記第2のゲート短絡用スイッチング素子とが同一のチップに設けられている、請求項1〜3のいずれか一項に記載のパワーモジュール。
- 前記第1のパワースイッチング素子と前記第2のパワースイッチング素子とは、デッドタイムを挟んで交互にオンされ、
第1のゲート短絡用スイッチング素子は、前記第2のパワースイッチング素子がオンするよりも前にオンされ、前記第2のパワースイッチング素子がオンしてから第1の所定期間が経過した後であって、前記第1のパワースイッチング素子がオンされる前にオフされ、
第2のゲート短絡用スイッチング素子は、前記第1のパワースイッチング素子がオンするよりも前にオンされ、前記第1のパワースイッチング素子がオンしてから第2の所定期間が経過した後であって、前記第2のパワースイッチング素子がオンされる前にオフされる、請求項1〜11のいずれか一項に記載のパワーモジュール。 - 前記第1の所定期間は、前記第2のパワースイッチング素子がオンしてから前記第1のパワースイッチング素子のドレイン・ソース間電圧が上昇する時間以上に設定され、前記第2の所定期間は、前記第1のパワースイッチング素子がオンしてから前記第2のパワースイッチング素子のドレイン・ソース間電圧が上昇する時間以上に設定される、請求項12に記載のパワーモジュール。
- 前記第1の所定期間は200nsec以上に設定され、前記第2の所定期間は200nsec以上に設定される、請求項12または13に記載のパワーモジュール。
- 前記第1のパワースイッチング素子と前記第1のゲート短絡用スイッチング素子とを接続するための第1の接続金属部材と、
前記第2のパワースイッチング素子と前記第2のゲート短絡用スイッチング素子とを接続するための第2の接続金属部材とを含み、
前記第1接続金属部材および前記第2の接続金属部材が、Au,Cu,またはAlからなるワイヤ状、フレーム状またはリボン状である、請求項4〜10のいずれか一項に記載のパワーモジュール。 - 第1のパワースイッチングは第1の電流検出部を含み、
第2のパワースイッチングは第2の電流検出部を含み、
前記第1の電流検出部が接続される第1のソースセンス端子と、
前記第2の電流検出部が接続される第2のソースセンス端子とをさらに含む、請求項1〜15のいずれか一項に記載のパワーモジュール。 - 前記請求項1〜16のいずれか一項に記載のパワーモジュールと、
前記第1のパワースイッチング素子、前記第2のパワースイッチング素子、前記第1のゲート短絡用スイッチング素子および前記第2のゲート短絡用スイッチング素子を駆動するためのゲート駆動回路と、
前記ゲート駆動回路を制御する制御部とを含み、
前記制御部がマイクロコンピュータからなる、出力回路。 - 前記制御部は、前記前記第1のパワースイッチング素子、前記第2のパワースイッチング素子、前記第1のゲート短絡用スイッチング素子および前記第2のゲート短絡用スイッチング素子に対するゲート制御信号をそれぞれ生成する手段を含み、
前記ゲート駆動回路は、前記制御部によって生成されたゲート制御信号に応じたゲート駆動信号を生成して、対応するスイッチング素子のゲートに供給するものである、請求項17に記載の、出力回路。
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