JPWO2011122407A1 - 金属ベース基板 - Google Patents
金属ベース基板 Download PDFInfo
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- JPWO2011122407A1 JPWO2011122407A1 JP2012508231A JP2012508231A JPWO2011122407A1 JP WO2011122407 A1 JPWO2011122407 A1 JP WO2011122407A1 JP 2012508231 A JP2012508231 A JP 2012508231A JP 2012508231 A JP2012508231 A JP 2012508231A JP WO2011122407 A1 JPWO2011122407 A1 JP WO2011122407A1
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- low
- sintered ceramic
- temperature sintered
- metal plate
- ceramic layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B32—LAYERED PRODUCTS
- B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
- B32B7/00—Layered products characterised by the relation between layers; Layered products characterised by the relative orientation of features between layers, or by the relative values of a measurable parameter between layers, i.e. products comprising layers having different physical, chemical or physicochemical properties; Layered products characterised by the interconnection of layers
- B32B7/02—Physical, chemical or physicochemical properties
- B32B7/027—Thermal properties
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- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/142—Metallic substrates having insulating layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
- H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
- H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
- H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45147—Copper (Cu) as principal constituent
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0183—Dielectric layers
- H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/049—Wire bonding
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T428/00—Stock material or miscellaneous articles
- Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
- Y10T428/24942—Structurally defined web or sheet [e.g., overall dimension, etc.] including components having same physical characteristic in differing degree
- Y10T428/2495—Thickness [relative or absolute]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Thermal Sciences (AREA)
- Inorganic Chemistry (AREA)
- Structure Of Printed Boards (AREA)
- Laminated Bodies (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
Description
BaCO3、Al2O3(コランダム)、およびSiO2(クオーツ)の各粉末を用意し、これらを混合した混合粉末を840℃の温度で120分間仮焼することによって、BaO:37.0重量%、Al2O3:11.0重量%、およびSiO2:52.0重量%の含有比率となる原料粉末1を作製した。
上記複合グリーンシートを10枚積層し、温度80℃、圧力150MPaの条件でプレスし、平面寸法30mm□の未焼成の第1の評価用試料を作製した。
上記第1、第2および第3の評価用試料を、還元性雰囲気中、表2の「焼成温度」の欄に示す温度で180分間焼成した。
表2に示すように、「焼成収縮率」、「熱膨張係数」、「ヤング率」および「抗折強度」を、第1の評価用試料によって評価した。
12 金属ベース基板
14 金属板
15 低温焼結セラミック層
16 拘束層
Claims (2)
- 金属板と、
前記金属板の上に形成された低温焼結セラミック層と
を備え、
前記金属板の熱膨張係数は前記低温焼結セラミック層の熱膨張係数より大きく、前記金属板と前記低温焼結セラミック層との25〜400℃での平均熱膨張係数差が9ppm/℃以下であり、かつ、
前記低温焼結セラミック層のヤング率が120GPa未満であり、かつ抗折強度が200MPa以上である、
金属ベース基板。 - 前記平均熱膨張係数差は4ppm/℃以上である、請求項1に記載の金属ベース基板。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012508231A JP5648682B2 (ja) | 2010-03-30 | 2011-03-23 | 金属ベース基板 |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010076686 | 2010-03-30 | ||
JP2010076686 | 2010-03-30 | ||
JP2012508231A JP5648682B2 (ja) | 2010-03-30 | 2011-03-23 | 金属ベース基板 |
PCT/JP2011/056914 WO2011122407A1 (ja) | 2010-03-30 | 2011-03-23 | 金属ベース基板 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2011122407A1 true JPWO2011122407A1 (ja) | 2013-07-08 |
JP5648682B2 JP5648682B2 (ja) | 2015-01-07 |
Family
ID=44712117
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012508231A Expired - Fee Related JP5648682B2 (ja) | 2010-03-30 | 2011-03-23 | 金属ベース基板 |
Country Status (3)
Country | Link |
---|---|
US (1) | US20130266782A1 (ja) |
JP (1) | JP5648682B2 (ja) |
WO (1) | WO2011122407A1 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9863831B2 (en) * | 2013-03-25 | 2018-01-09 | Endress + Hauser Gmbh + Co. Kg | Sintered body comprising a plurality of materials and pressure measuring instrument comprising such a sintered body |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015160359A1 (en) * | 2014-04-18 | 2015-10-22 | Halliburton Energy Services, Inc. | High-temperature cycling bga packaging |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5256469A (en) * | 1991-12-18 | 1993-10-26 | General Electric Company | Multi-layered, co-fired, ceramic-on-metal circuit board for microelectronic packaging |
US6709749B1 (en) * | 1995-06-06 | 2004-03-23 | Lamina Ceramics, Inc. | Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate |
US6143432A (en) * | 1998-01-09 | 2000-11-07 | L. Pierre deRochemont | Ceramic composites with improved interfacial properties and methods to make such composites |
JPH10139560A (ja) * | 1996-11-14 | 1998-05-26 | Nippon Chemicon Corp | セラミック基板 |
JP2000082774A (ja) * | 1998-06-30 | 2000-03-21 | Sumitomo Electric Ind Ltd | パワ―モジュ―ル用基板およびその基板を用いたパワ―モジュ―ル |
JP2001015930A (ja) * | 1999-06-30 | 2001-01-19 | Kyocera Corp | 多層配線基板およびその製造方法 |
JP3666321B2 (ja) * | 1999-10-21 | 2005-06-29 | 株式会社村田製作所 | 多層セラミック基板およびその製造方法 |
JP2001244376A (ja) * | 2000-02-28 | 2001-09-07 | Hitachi Ltd | 半導体装置 |
JP2002368422A (ja) * | 2001-04-04 | 2002-12-20 | Murata Mfg Co Ltd | 多層セラミック基板及びその製造方法 |
JP4029163B2 (ja) * | 2002-07-18 | 2008-01-09 | 株式会社村田製作所 | 積層型セラミック電子部品およびその製造方法 |
JP4549029B2 (ja) * | 2003-02-25 | 2010-09-22 | 京セラ株式会社 | ガラスセラミック組成物、ガラスセラミック焼結体、ガラスセラミック焼結体の製造方法、および配線基板 |
US7186461B2 (en) * | 2004-05-27 | 2007-03-06 | Delaware Capital Formation, Inc. | Glass-ceramic materials and electronic packages including same |
JP2006237268A (ja) * | 2005-01-28 | 2006-09-07 | Kyocera Corp | 配線基板 |
JP4583224B2 (ja) * | 2005-04-05 | 2010-11-17 | 京セラ株式会社 | 測定用配線基板、プローブカード及び評価装置 |
US7547369B2 (en) * | 2006-08-31 | 2009-06-16 | Ferro Corporation | Method of making multilayer structures using tapes on non-densifying substrates |
KR100825766B1 (ko) * | 2007-04-26 | 2008-04-29 | 한국전자통신연구원 | Ltcc 패키지 및 그 제조방법 |
CN101784502B (zh) * | 2007-08-17 | 2013-03-27 | 株式会社村田制作所 | 陶瓷组合物及其制造方法、陶瓷基板、以及陶瓷生坯层的制造方法 |
JP5213477B2 (ja) * | 2008-02-26 | 2013-06-19 | 京セラ株式会社 | ガラスセラミックスの製造方法 |
-
2011
- 2011-03-23 WO PCT/JP2011/056914 patent/WO2011122407A1/ja active Application Filing
- 2011-03-23 JP JP2012508231A patent/JP5648682B2/ja not_active Expired - Fee Related
-
2012
- 2012-09-28 US US13/630,044 patent/US20130266782A1/en not_active Abandoned
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9863831B2 (en) * | 2013-03-25 | 2018-01-09 | Endress + Hauser Gmbh + Co. Kg | Sintered body comprising a plurality of materials and pressure measuring instrument comprising such a sintered body |
Also Published As
Publication number | Publication date |
---|---|
US20130266782A1 (en) | 2013-10-10 |
JP5648682B2 (ja) | 2015-01-07 |
WO2011122407A1 (ja) | 2011-10-06 |
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