JPWO2008139606A1 - 試験装置 - Google Patents
試験装置 Download PDFInfo
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- JPWO2008139606A1 JPWO2008139606A1 JP2009513940A JP2009513940A JPWO2008139606A1 JP WO2008139606 A1 JPWO2008139606 A1 JP WO2008139606A1 JP 2009513940 A JP2009513940 A JP 2009513940A JP 2009513940 A JP2009513940 A JP 2009513940A JP WO2008139606 A1 JPWO2008139606 A1 JP WO2008139606A1
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- Prior art keywords
- test
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- signals
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5602—Interface to device under test
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C2029/5606—Error catch memory
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
Claims (6)
- 複数の端子から出力されるべき信号を一のテスト端子から順次出力するテスト機能を備える被試験デバイスを試験する試験装置であって、
試験信号を前記被試験デバイスに供給し、前記試験信号に応じて前記テスト端子から順次出力される信号を受け取る試験部と、
前記試験部が順次受け取った信号のそれぞれが、前記被試験デバイスのいずれの端子から出力されるべき信号であるかの対応関係を特定する特定部と、
前記試験部が順次受け取った信号のうち不良と判定される信号の数を、前記特定部が特定した前記対応関係に基づいて、前記被試験デバイスの端子毎に計数する計数部と
を備える試験装置。 - 前記計数部は、
前記被試験デバイスの複数の端子と一対一に対応して設けられ、それぞれ対応する端子から出力されるべき信号の不良の数を記憶する複数の計数レジスタと、
前記試験部が受け取った信号が不良と判定された場合に、当該信号を出力すべき端子として前記特定部が特定する端子に対応する前記計数レジスタの格納値を増加させる加算部と
を有する請求項1に記載の試験装置。 - 前記試験部が順次受け取った信号が期待値に一致するか否かを順次比較して、それぞれの信号についての比較結果を順次出力する論理比較部を更に備え、
前記加算部は、前記複数の計数レジスタと一対一に対応して設けられ、前記論理比較部が順次出力する前記比較結果と、与えられる制御信号との論理積に基づいて、対応する前記計数レジスタの格納値を増加させる複数の論理積回路を有し、
前記特定部は、それぞれの前記論理積回路に、それぞれの前記対応関係に基づくタイミングでH論理を示す前記制御信号を供給する
請求項2に記載の試験装置。 - 前記試験部は、複数の前記論理積回路に供給すべき、H論理を示すタイミングがそれぞれ異なる複数の前記制御信号を更に生成し、
前記特定部は、
前記複数の論理積回路と一対一に対応して設けられ、それぞれの前記対応関係に基づいて、いずれかの前記制御信号を選択して、対応する前記論理積回路に供給する制御信号選択部と
を有する請求項3に記載の試験装置。 - 前記制御信号選択部は、
複数の前記制御信号を並列に受け取り、いずれかの前記制御信号を選択して、対応する前記論理積回路に供給するマルチプレクサと、
前記対応関係に基づいて、前記マルチプレクサが選択すべき前記制御信号を示す情報を格納して、前記マルチプレクサに供給する選択制御レジスタと
を有する請求項4に記載の試験装置。 - 前記試験部は、前記試験信号の出力タイミングに応じたタイミングで、前記複数の制御信号をそれぞれの前記選択部に供給する
請求項4に記載の試験装置。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2007/059877 WO2008139606A1 (ja) | 2007-05-14 | 2007-05-14 | 試験装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPWO2008139606A1 true JPWO2008139606A1 (ja) | 2010-07-29 |
JP4874391B2 JP4874391B2 (ja) | 2012-02-15 |
Family
ID=40001837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009513940A Expired - Fee Related JP4874391B2 (ja) | 2007-05-14 | 2007-05-14 | 試験装置 |
Country Status (4)
Country | Link |
---|---|
US (1) | US8072232B2 (ja) |
JP (1) | JP4874391B2 (ja) |
KR (1) | KR101184312B1 (ja) |
WO (1) | WO2008139606A1 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20100083364A (ko) * | 2009-01-13 | 2010-07-22 | 삼성전자주식회사 | 전기적 특성 검사 장치 |
JP2022115179A (ja) * | 2021-01-28 | 2022-08-09 | キオクシア株式会社 | 半導体集積回路装置及びその動作方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01308978A (ja) * | 1988-06-08 | 1989-12-13 | Hitachi Electron Eng Co Ltd | パターンデータ発生回路 |
JPH0328596U (ja) * | 1989-07-20 | 1991-03-22 | ||
JP2864880B2 (ja) * | 1992-07-13 | 1999-03-08 | 日本電気株式会社 | 半導体メモリic試験装置 |
JPH0933615A (ja) | 1995-07-19 | 1997-02-07 | Advantest Corp | 半導体メモリ試験装置のメモリ不良解析装置 |
JP3237579B2 (ja) * | 1997-08-07 | 2001-12-10 | 日本電気株式会社 | メモリテスト回路 |
CN1141593C (zh) | 1997-11-20 | 2004-03-10 | 株式会社爱德万测试 | 集成电路测试方法和采用该测试方法的集成电路测试装置 |
US6404220B1 (en) | 1997-11-20 | 2002-06-11 | Advantest Corporation | IC testing method and IC testing device using the same |
JPH11223660A (ja) * | 1998-02-06 | 1999-08-17 | Toshiba Microelectronics Corp | 半導体試験装置およびこれを用いた半導体試験方法 |
KR100363936B1 (ko) | 1999-07-10 | 2002-12-16 | 가부시키가이샤 아드반테스트 | Ic 시험방법 및 이 시험방법을 이용한 ic 시험장치 |
JP2001043700A (ja) * | 1999-08-02 | 2001-02-16 | Fujitsu Ltd | 半導体記憶装置 |
US6377065B1 (en) * | 2000-04-13 | 2002-04-23 | Advantest Corp. | Glitch detection for semiconductor test system |
-
2007
- 2007-05-14 JP JP2009513940A patent/JP4874391B2/ja not_active Expired - Fee Related
- 2007-05-14 WO PCT/JP2007/059877 patent/WO2008139606A1/ja active Application Filing
- 2007-05-14 KR KR1020097025770A patent/KR101184312B1/ko active IP Right Grant
-
2009
- 2009-11-13 US US12/618,619 patent/US8072232B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP4874391B2 (ja) | 2012-02-15 |
KR101184312B1 (ko) | 2012-09-21 |
WO2008139606A1 (ja) | 2008-11-20 |
US20100148815A1 (en) | 2010-06-17 |
KR20100013321A (ko) | 2010-02-09 |
US8072232B2 (en) | 2011-12-06 |
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