JPWO2008035598A1 - 相補型mis半導体装置 - Google Patents
相補型mis半導体装置 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 230000000295 complement effect Effects 0.000 title claims abstract description 23
- 239000000463 material Substances 0.000 claims abstract description 47
- 229910052759 nickel Inorganic materials 0.000 claims description 16
- 229910052710 silicon Inorganic materials 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 150000001875 compounds Chemical class 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 42
- 239000000758 substrate Substances 0.000 description 36
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 32
- 239000007772 electrode material Substances 0.000 description 18
- 238000000034 method Methods 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 13
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 239000011229 interlayer Substances 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 229910021334 nickel silicide Inorganic materials 0.000 description 10
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 10
- 238000002955 isolation Methods 0.000 description 8
- 239000000203 mixture Substances 0.000 description 8
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000005669 field effect Effects 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 4
- 229910005487 Ni2Si Inorganic materials 0.000 description 3
- 229910005883 NiSi Inorganic materials 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 239000013078 crystal Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000005855 radiation Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- VEQPNABPJHWNSG-UHFFFAOYSA-N Nickel(2+) Chemical compound [Ni+2] VEQPNABPJHWNSG-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- -1 oxygen ions Chemical class 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
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Abstract
Description
一般に、MOSFETのしきい値電圧は、完全空乏型のSOI構造では式(1)のVth1で表わされ、式(2)で表わされる部分空乏型SOIあるいはバルク構造のMOSFETのVth2よりも絶対値が小さくなる。
Vth1=VFB+2φF+(qNt/Cox) ・・・・・ (1)
Vth2=VFB+2φF+2(qεSiφFN)1/2/Cox ・・・・・ (2)
(VFBはフラットバンド電圧、φFはSiのフェルミ電位、qは電気素量、Nはチャネル不純物濃度、tはSOI膜厚、Coxはゲート絶縁膜容量、εSiはSiの誘電率を示す)
また、スレッシュホールド電圧はゲート電極材料の仕事関数によって決まるから、ゲート電極材料として適当な仕事関数を持つものを選び、p型あるいはn型のスレッシュホールド電圧の絶対値の大きい方だけをSOI構造とすることによって、1種類のゲート電極材料を使って、p型MOSFETとn型MOSFETのスレッシュホールド電圧の絶対値を同じにすることができる。また、式(1)および(2)からわかるように、MOSFETのスレッシュホールド電圧はチャネルドーピングの濃度や、SOI構造にした場合にはSOIの膜厚によっても変化する。したがって、SOI構造とするだけではスレッシュホールド電圧が所望の値に十分近づかない場合には、さらにSOIの膜厚を調整したり、チャネルドーピングの濃度を調整したりすることによって、スレッシュホールド電圧を調整することができる。
図1から図6を参照して第1の実施形態例の半導体装置について説明する。図1は、本発明の半導体装置の製造手順の一部を示したものである。本発明においては、まず、図1Aに示すようなSOI基板を用意する。図1AのSOI基板は、支持基板201、埋め込み酸化膜層202、SOI層203より構成されている。次に図1Bに示すように、このSOI基板に素子分離領域204を形成した後に、p型MOSFETが形成される領域のSOI層と埋め込み酸化膜層をエッチングによって除去して、表面に支持基板層が現れるようにする。次に図1Cに示すように、図1Bで露出した支持基板層の上に、Si層205をエピタキシャル成長させる。この時、n型MOSFETが形成される領域は、Siがエピタキシャル成長しないように、シリコンの酸化膜等で覆っておく。ここまでで、p型MOSFETが形成される領域は通常のバルク基板構造、n型MOSFETが形成される領域はSOI構造とすることができる。
次に、本発明の第2の実施形態例を図7A及び7Bを参照して説明する。第2の実施形態例においては、まず、図7Aに示すように、支持基板801、素子分離領域802、第1の埋め込み酸化膜層803、第2の埋め込み酸化膜層804、第1のSOI層805、および第2のSOI層806からなる基板を用意する。ここで、第1のSOI層805と第2のSOI層806は、それぞれn型MOSFETおよびp型MOSFETが形成される領域であり、最終的な厚さによってスレッシュホールド電圧が決定される。このような基板は、例えば、酸素イオン注入を用いたSIMOX法において、n型MOSFET領域とp型MOSFET領域とで酸素イオン注入のエネルギーおよびドーズ量を変えることによって得ることができる。
本発明の第3の実施形態例を、図8A〜8C、図9、図10を参照して説明する。図8A〜8Cは、本発明の第3の実施形態例の半導体装置の製造工程を順次に示したものである。第3の実施形態例においては、まず、図8Aに示すように、(110)面を主面とする支持基板901の上に、埋め込み酸化膜層902を挟んで(100)面を主面とするSOI層903が具備されているような基板を用意する。このような基板は、ハイブリッド基板と呼ばれるもので、(110)面を主面とするウェーハと(100)面を主面とするウェーハを、酸化膜を介して張り合わせることによって得ることができる。なお、本発明において(110)面または(100)面と言った場合には、面方位が実質的に(110)あるいは(100)および結晶学的にそれらと等価な面方位であることを意味しており、面方位が(110)あるいは(100)と完全に一致しなければいけないというものではない。
p型MOSFETとn型MOSFETの両方を完全空乏型のSOI構造とすることができる。また、ゲート電極としてメタルゲート電極を用い、ゲート絶縁膜として高誘電率絶縁膜を用いることができる。さらに、p型MOSFETを(110)面に作成することができる。したがって、一種類の電極材料でしきい値電圧をn型MOSFETとp型MOSFETとで対称に制御すると同時に、寄生容量の低下や放射線耐性の向上を実現し、なおかつ低消費電力化や高速化を実現した半導体装置を提供することができる。
Claims (10)
- p型トランジスタ及びn型トランジスタの何れか一方が、完全空乏型SOI構造を有する相補型MIS半導体装置において、
前記p型トランジスタ及びn型トランジスタのゲート電極が同一の材料で構成され、かつ前記材料は、p型トランジスタ及びn型トランジスタの閾値電圧の絶対値を実質的に同じとすることができる仕事関数を有する材料である、ことを特徴とする半導体装置。 - p型トランジスタ及びn型トランジスタの何れか一方が、完全空乏型SOI構造を有する相補型MIS半導体装置において、
前記p型トランジスタ及びn型トランジスタのゲート電極が同一の材料で構成され、かつ前記材料は、p型トランジスタ及びn型トランジスタの閾値電圧の絶対値のうち、大きい方の絶対値と小さい方の絶対値との差が、大きい方の絶対値の20%以下とすることができる仕事関数を有する材料である、ことを特徴とする半導体装置。 - p型トランジスタ及びn型トランジスタの他方が、バルク構造を有することを特徴とする請求項1または2に記載の半導体装置。
- p型トランジスタ及びn型トランジスタの双方が、完全空乏型SOI構造を有する相補型MIS半導体装置において、
前記p型トランジスタ及びn型トランジスタのSOI層が異なる膜厚を有し、
前記p型トランジスタ及びn型トランジスタのゲート電極が同一の材料で構成され、かつ前記材料は、p型トランジスタ及びn型トランジスタの閾値電圧の絶対値を実質的に同じにすることができる仕事関数を有する材料である、ことを特徴とする半導体装置。 - p型、n型の両方が完全空乏型SOI構造を有する相補型MIS半導体装置において、
前記相補型MIS半導体装置のp型、n型のSOI層が、それぞれ異なる膜厚で構成され、
前記相補型MIS半導体装置のp型、n型のゲート電極が同一の材料で構成され、かつ前記材料は、p型、n型の閾値電圧の絶対値のうち、大きい方の絶対値と小さい方の絶対値の差が、大きい方の絶対値の20%以下とすることができる仕事関数を有する材料である、ことを特徴とする半導体装置。 - 前記ゲート電極の材料が、金属であることを特徴とする請求項1乃至5のいずれか1項に記載の半導体装置。
- 前記ゲート電極の材料が、NiとSiの化合物であることを特徴とする、請求項1乃至6のいずれか1項に記載の半導体装置。
- 前記p型トランジスタ及びn型トランジスタのゲート絶縁膜が、高誘電率絶縁膜であることを特徴とする、請求項1乃至7のいずれか1項に記載の半導体装置。
- 前記高誘電率絶縁膜がHfを含むことを特徴とする、請求項8に記載の半導体装置。
- 前記p型トランジスタの半導体活性層の表面は、(110)面または(110)面と等価な面であり、n型トランジスタの半導体活性層の表面が、(100)面または(100)面と等価な面であることを特徴とする、請求項1乃至9のいずれか1項に記載の半導体装置。
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JPH03239358A (ja) * | 1990-02-16 | 1991-10-24 | Matsushita Electron Corp | 半導体装置 |
JPH05243510A (ja) * | 1992-02-29 | 1993-09-21 | Nec Corp | 半導体集積回路装置及びその製造方法 |
JP2005158998A (ja) * | 2003-11-26 | 2005-06-16 | Toshiba Corp | 半導体装置の製造方法 |
JP2006229047A (ja) * | 2005-02-18 | 2006-08-31 | Renesas Technology Corp | 半導体装置及び半導体装置の製造方法 |
WO2007004535A1 (ja) * | 2005-07-05 | 2007-01-11 | Renesas Technology Corp. | 半導体装置およびその製造方法 |
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JPH05315557A (ja) * | 1992-09-29 | 1993-11-26 | Toshiba Corp | 半導体集積回路装置の製造方法 |
JP2006032712A (ja) * | 2004-07-16 | 2006-02-02 | Nec Corp | 半導体装置及びその製造方法 |
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JPH03239358A (ja) * | 1990-02-16 | 1991-10-24 | Matsushita Electron Corp | 半導体装置 |
JPH05243510A (ja) * | 1992-02-29 | 1993-09-21 | Nec Corp | 半導体集積回路装置及びその製造方法 |
JP2005158998A (ja) * | 2003-11-26 | 2005-06-16 | Toshiba Corp | 半導体装置の製造方法 |
JP2006229047A (ja) * | 2005-02-18 | 2006-08-31 | Renesas Technology Corp | 半導体装置及び半導体装置の製造方法 |
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